| * | 2008 |
|---|
| 11 | EE | Smruti R. Sarangi,
Brian Greskamp,
Abhishek Tiwari,
Josep Torrellas:
EVAL: Utilizing processors with variation-induced timing errors.
MICRO 2008: 423-434 |
| 2007 |
|---|
| 10 | EE | Abhishek Tiwari,
Smruti R. Sarangi,
Josep Torrellas:
ReCycle: : pipeline adaptation to tolerate process variation.
ISCA 2007: 323-334 |
| 9 | EE | Brian Greskamp,
Smruti R. Sarangi,
Josep Torrellas:
Threshold Voltage Variation Effects on Aging-Related Hard Failure Rates.
ISCAS 2007: 1261-1264 |
| 8 | EE | Smruti R. Sarangi,
Brian Greskamp,
Josep Torrellas:
A Model for Timing Errors in Processors with Parameter Variation.
ISQED 2007: 647-654 |
| 7 | EE | Smruti R. Sarangi,
Satish Narayanasamy,
Bruce Carneal,
Abhishek Tiwari,
Brad Calder,
Josep Torrellas:
Patching Processor Design Errors with Programmable Hardware.
IEEE Micro 27(1): 12-25 (2007) |
| 2006 |
|---|
| 6 | EE | Smruti R. Sarangi,
Brian Greskamp,
Josep Torrellas:
CADRE: Cycle-Accurate Deterministic Replay for Hardware Debugging.
DSN 2006: 301-312 |
| 5 | EE | Smruti R. Sarangi,
Abhishek Tiwari,
Josep Torrellas:
Phoenix: Detecting and Recovering from Permanent Processor Design Bugs with Programmable Hardware.
MICRO 2006: 26-37 |
| 4 | EE | Jose Renau,
Karin Strauss,
Luis Ceze,
Wei Liu,
Smruti R. Sarangi,
James Tuck,
Josep Torrellas:
Energy-Efficient Thread-Level Speculation.
IEEE Micro 26(1): 80-91 (2006) |
| 2005 |
|---|
| 3 | EE | Jose Renau,
Karin Strauss,
Luis Ceze,
Wei Liu,
Smruti R. Sarangi,
James Tuck,
Josep Torrellas:
Thread-Level Speculation on a CMP can be energy efficient.
ICS 2005: 219-228 |
| 2 | EE | Smruti R. Sarangi,
Wei Liu,
Yuanyuan Zhou:
ReSlice: Selective Re-Execution of Long-Retired Misspeculated Instructions Using Forward Slicing.
MICRO 2005: 257-270 |
| 2003 |
|---|
| 1 | | Smruti R. Sarangi,
P. N. Sireesh,
Sudebkumar Prasant Pal:
A scalable, efficient and general Monte Carlo scheme for generating synthetic web request streams.
Comput. Syst. Sci. Eng. 18(3): 121-128 (2003) |
