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Sachin S. Sapatnekar Vis

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*2009
195EEPingqiang Zhou, Karthikk Sridharan, Sachin S. Sapatnekar: Congestion-aware power grid optimization for 3D circuits using MIM and CMOS decoupling capacitors. ASP-DAC 2009: 179-184
194EESanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar: Adaptive techniques for overcoming performance degradation due to aging in digital circuits. ASP-DAC 2009: 284-289
193EESachin S. Sapatnekar: Addressing thermal and power delivery bottlenecks in 3D circuits. ASP-DAC 2009: 423-428
192EESachin S. Sapatnekar: Technical perspective - Where the chips may fall. Commun. ACM 52(8): 94 (2009)
191EEHushrav Mogal, Haifeng Qian, Sachin S. Sapatnekar, Kia Bazargan: Fast and Accurate Statistical Criticality Computation Under Process Variations. IEEE Trans. on CAD of Integrated Circuits and Systems 28(3): 350-363 (2009)
2008
190EESachin S. Sapatnekar, Eshel Haritan, Kurt Keutzer, Anirudh Devgan, Desmond Kirkpatrick, Stephen Meier, Duaine Pryor, Tom Spyrou: Reinventing EDA with manycore processors. DAC 2008: 126-127
189EEPing-Hung Yuh, Sachin S. Sapatnekar, Chia-Lin Yang, Yao-Wen Chang: A progressive-ILP based routing algorithm for cross-referencing biochips. DAC 2008: 284-289
188EESanjay V. Kumar, Chandramouli V. Kashyap, Sachin S. Sapatnekar: A framework for block-based timing sensitivity analysis. DAC 2008: 688-693
187EEYong Zhan, Sanjay V. Kumar, Sachin S. Sapatnekar: Thermally Aware Design. Foundations and Trends in Electronic Design Automation 2(3): 255-370 (2008)
186EESachin S. Sapatnekar: Building your yield of dreams. IEEE Design & Test of Computers 25(2): 194-195 (2008)
185EESachin S. Sapatnekar: Adapting to the times [review of Adaptive Techniques for Dynamic Processor Optimization: Theory and Practice (Wang, A. and Naffziger, S., Eds.; 2008)]. IEEE Design & Test of Computers 25(5): 496-497 (2008)
184EEJie Gu, John Keane, Sachin S. Sapatnekar, Chris H. Kim: Statistical Leakage Estimation of Double Gate FinFET Devices Considering the Width Quantization Property. IEEE Trans. VLSI Syst. 16(2): 206-209 (2008)
183EESanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar: Body Bias Voltage Computations for Process and Temperature Compensation. IEEE Trans. VLSI Syst. 16(3): 249-262 (2008)
182EEJohn Keane, Hanyong Eom, Tae-Hyoung Kim, Sachin S. Sapatnekar, Chris H. Kim: Stack Sizing for Optimal Current Drivability in Subthreshold Circuits. IEEE Trans. VLSI Syst. 16(5): 598-602 (2008)
181EEJaskirat Singh, Sachin S. Sapatnekar: A Scalable Statistical Static Timing Analyzer Incorporating Correlated Non-Gaussian and Gaussian Parameter Variations. IEEE Trans. on CAD of Integrated Circuits and Systems 27(1): 160-173 (2008)
180EEShrirang K. Karandikar, Sachin S. Sapatnekar: Technology Mapping Using Logical Effort for Solving the Load-Distribution Problem. IEEE Trans. on CAD of Integrated Circuits and Systems 27(1): 45-58 (2008)
179EEJaskirat Singh, Zhi-Quan Luo, Sachin S. Sapatnekar: A Geometric Programming-Based Worst Case Gate Sizing Method Incorporating Spatial Correlation. IEEE Trans. on CAD of Integrated Circuits and Systems 27(2): 295-308 (2008)
178EETianpei Zhang, Sachin S. Sapatnekar: Buffering global interconnects in structured ASIC design. Integration 41(2): 171-182 (2008)
177EEYong Zhan, Sachin S. Sapatnekar: Automated module assignment in stacked-Vdd designs for high-efficiency power delivery. JETC 4(4): (2008)
176EEHaifeng Qian, Sachin S. Sapatnekar: Stochastic Preconditioning for Diagonally Dominant Matrices. SIAM J. Scientific Computing 30(3): 1178-1204 (2008)
2007
175EEFelipe S. Marques, Leomar S. da Rosa Jr., Renato P. Ribas, Sachin S. Sapatnekar, André Inácio Reis: DAG based library-free technology mapping. ACM Great Lakes Symposium on VLSI 2007: 293-298
174EESachin S. Sapatnekar: Computer-aided design of 3d integrated circuits. ACM Great Lakes Symposium on VLSI 2007: 317
173EESanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar: NBTI-Aware Synthesis of Digital Circuits. DAC 2007: 370-375
172EEQunzeng Liu, Sachin S. Sapatnekar: Confidence Scalable Post-Silicon Statistical Delay Prediction under Process Variations. DAC 2007: 497-502
171EEBrent Goplen, Sachin S. Sapatnekar: Placement of 3D ICs with Thermal and Interlayer Via Considerations. DAC 2007: 626-631
170EEJie Gu, Sachin S. Sapatnekar, Chris H. Kim: Width-dependent Statistical Leakage Modeling for Random Dopant Induced Threshold Voltage Shift. DAC 2007: 87-92
169EEHushrav Mogal, Haifeng Qian, Sachin S. Sapatnekar, Kia Bazargan: Clustering based pruning for statistical criticality computation under process variations. ICCAD 2007: 340-343
168EEDmitry Bufistov, Jordi Cortadella, Michael Kishinevsky, Sachin S. Sapatnekar: A general model for performance optimization of sequential systems. ICCAD 2007: 362-369
167EEYong Zhan, Tianpei Zhang, Sachin S. Sapatnekar: Module assignment for pin-limited designs under the stacked-Vdd paradigm. ICCAD 2007: 656-659
166EEZhuo Li, Charles J. Alpert, Stephen T. Quay, Sachin S. Sapatnekar, Weiping Shi: Probabilistic Congestion Prediction with Partial Blockages. ISQED 2007: 841-846
165EEHongliang Chang, Sachin S. Sapatnekar: Prediction of leakage power under process uncertainties. ACM Trans. Design Autom. Electr. Syst. 12(2): (2007)
164EESachin S. Sapatnekar: Book Review: An Assay of Biochips. IEEE Design & Test of Computers 24(4): 402-403 (2007)
163EESachin S. Sapatnekar, Leon Stok: DAC Highlights. IEEE Design & Test of Computers 24(5): 502-504 (2007)
162EETianpei Zhang, Sachin S. Sapatnekar: Simultaneous Shield and Buffer Insertion for Crosstalk Noise Reduction in Global Routing. IEEE Trans. VLSI Syst. 15(6): 624-636 (2007)
161EEGustavo de Veciana, Marcello Lajolo, Chen He, Enrico Macii, Sachin S. Sapatnekar: In Memoriam: Margarida F. Jacome. IEEE Trans. on CAD of Integrated Circuits and Systems 26(9): 1549-1550 (2007)
160EEYong Zhan, Sachin S. Sapatnekar: High-Efficiency Green Function-Based Thermal Simulation Algorithms. IEEE Trans. on CAD of Integrated Circuits and Systems 26(9): 1661-1675 (2007)
159EEKrishnendu Chakrabarty, Sachin S. Sapatnekar: Editorial to special issue DAC 2006. JETC 3(3): (2007)
2006
158EEYong Zhan, Brent Goplen, Sachin S. Sapatnekar: Electrothermal analysis and optimization techniques for nanoscale integrated circuits. ASP-DAC 2006: 219-222
157EETianpei Zhang, Yong Zhan, Sachin S. Sapatnekar: Temperature-aware routing in 3D ICs. ASP-DAC 2006: 309-314
156EESanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar: Mathematically assisted adaptive body bias (ABB) for temperature compensation in gigascale LSI systems. ASP-DAC 2006: 559-564
155EEYong Zhan, Yan Feng, Sachin S. Sapatnekar: A fixed-die floorplanning algorithm using an analytical approach. ASP-DAC 2006: 771-776
154EEJaskirat Singh, Sachin S. Sapatnekar: Statistical timing analysis with correlated non-gaussian parameters using independent component analysis. DAC 2006: 155-160
153EEJohn Keane, Hanyong Eom, Tae-Hyoung Kim, Sachin S. Sapatnekar, Chris H. Kim: Subthreshold logical effort: a systematic framework for optimal subthreshold device sizing. DAC 2006: 425-428
152EESanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar: An analytical model for negative bias temperature instability. ICCAD 2006: 493-496
151EEVidyasagar Nookala, David J. Lilja, Sachin S. Sapatnekar: Temperature-aware floorplanning of microarchitecture blocks with IPC-power dependence modeling and transient analysis. ISLPED 2006: 298-303
150EEVidyasagar Nookala, Ying Chen, David J. Lilja, Sachin S. Sapatnekar: Comparing simulation techniques for microarchitecture-aware floorplanning. ISPASS 2006: 80-88
149EESanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar: Impact of NBTI on SRAM Read Stability and Design for Reliability. ISQED 2006: 210-218
148EEKeith A. Bowman, Michael Orshansky, Sachin S. Sapatnekar: Tutorial II: Variability and Its Impact on Design. ISQED 2006: 5
147EELeomar S. da Rosa Jr., Felipe S. Marques, Tiago Muller Gil Cardoso, Renato P. Ribas, Sachin S. Sapatnekar, André Inácio Reis: Fast disjoint transistor networks from BDDs. SBCCI 2006: 137-142
146EESachin S. Sapatnekar, Grant Martin: DAC Highlights. IEEE Design & Test of Computers 23(3): 182-184 (2006)
145EESachin S. Sapatnekar: Book Reviews: Plumbing the Depths of Leakage. IEEE Design & Test of Computers 23(4): 318-319 (2006)
144EERupesh S. Shelar, Prashant Saxena, Sachin S. Sapatnekar: Technology Mapping Algorithm Targeting Routing Congestion Under Delay Constraints. IEEE Trans. on CAD of Integrated Circuits and Systems 25(4): 625-636 (2006)
143EEJaskirat Singh, Sachin S. Sapatnekar: Partition-Based Algorithm for Power Grid Design Using Locality. IEEE Trans. on CAD of Integrated Circuits and Systems 25(4): 664-677 (2006)
142EEBrent Goplen, Sachin S. Sapatnekar: Placement of Thermal Vias in 3-D ICs Using Various Thermal Objectives. IEEE Trans. on CAD of Integrated Circuits and Systems 25(4): 692-709 (2006)
141EECharles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Cliff C. N. Sze: Accurate estimation of global buffer delay within a floorplan. IEEE Trans. on CAD of Integrated Circuits and Systems 25(6): 1140-1145 (2006)
2005
140EEFelipe S. Marques, Renato P. Ribas, Sachin S. Sapatnekar, André Inácio Reis: A new approach to the use of satisfiability in false path detection. ACM Great Lakes Symposium on VLSI 2005: 308-311
139EETianpei Zhang, Sachin S. Sapatnekar: Buffering global interconnects in structured ASIC design. ASP-DAC 2005: 23-26
138EEYong Zhan, Sachin S. Sapatnekar: Fast computation of the temperature distribution in VLSI chips using the discrete cosine transform and table look-up. ASP-DAC 2005: 87-92
137EEJaskirat Singh, Vidyasagar Nookala, Zhi-Quan Luo, Sachin S. Sapatnekar: Robust gate sizing by geometric programming. DAC 2005: 315-320
136EEBrent Goplen, Prashant Saxena, Sachin S. Sapatnekar: Net weighting to reduce repeater counts during placement. DAC 2005: 503-508
135EEHongliang Chang, Sachin S. Sapatnekar: Full-chip analysis of leakage power under process variations, including spatial correlations. DAC 2005: 523-528
134EEVidyasagar Nookala, Ying Chen, David J. Lilja, Sachin S. Sapatnekar: Microarchitecture-aware floorplanning using a statistical design of experiments approach. DAC 2005: 579-584
133 Yong Zhan, Sachin S. Sapatnekar: A high efficiency full-chip thermal simulation algorithm. ICCAD 2005: 635-638
132 Haifeng Qian, Sachin S. Sapatnekar: A hybrid linear equation solver and its application in quadratic placement. ICCAD 2005: 905-909
131EEFelipe Ribeiro Schneider, Renato P. Ribas, Sachin S. Sapatnekar, André Inácio Reis: Exact lower bound for the number of switches in series to implement a combinational logic cell. ICCD 2005: 357-362
130EEVidyasagar Nookala, Sachin S. Sapatnekar: Designing optimized pipelined global interconnects: algorithms and methodology impact. ISCAS (1) 2005: 608-611
129EEShrirang K. Karandikar, Sachin S. Sapatnekar: Fast estimation of area-delay trade-offs in circuit sizing. ISCAS (4) 2005: 3575-3578
128EERupesh S. Shelar, Prashant Saxena, Xinning Wang, Sachin S. Sapatnekar: An efficient technology mapping algorithm targeting routing congestion under delay constraints. ISPD 2005: 137-144
127EEBrent Goplen, Sachin S. Sapatnekar: Thermal via placement in 3D ICs. ISPD 2005: 167-174
126EEJaskirat Singh, Sachin S. Sapatnekar: A fast algorithm for power grid design. ISPD 2005: 70-77
125EESachin S. Sapatnekar, Jaijeet S. Roychowdhury, Ramesh Harjani: High-Speed Interconnect Technology: On-Chip and Off-Chip. VLSI Design 2005: 7-
124EESachin S. Sapatnekar: An EDA compendium. IEEE Design & Test of Computers 22(1): 74-75 (2005)
123EESachin S. Sapatnekar: Empowering the designer. IEEE Design & Test of Computers 22(3): 280-281 (2005)
122EESachin S. Sapatnekar, Kevin J. Nowka: Guest Editors' Introduction: New Dimensions in 3D Integration. IEEE Design & Test of Computers 22(6): 496-497 (2005)
121EECristinel Ababei, Yan Feng, Brent Goplen, Hushrav Mogal, Tianpei Zhang, Kia Bazargan, Sachin S. Sapatnekar: Placement and Routing in 3D Integrated Circuits. IEEE Design & Test of Computers 22(6): 520-531 (2005)
120EESachin S. Sapatnekar: Designing "Vary" Good Circuitry. IEEE Design & Test of Computers 22(6): 596-597 (2005)
119EEShrirang K. Karandikar, Sachin S. Sapatnekar: Fast comparisons of circuit implementations. IEEE Trans. VLSI Syst. 13(12): 1329-1339 (2005)
118EEAnup Kumar Sultania, Dennis Sylvester, Sachin S. Sapatnekar: Gate oxide leakage and delay tradeoffs for dual-T/sub ox/ circuits. IEEE Trans. VLSI Syst. 13(12): 1362-1375 (2005)
117EERupesh S. Shelar, Sachin S. Sapatnekar: BDD decomposition for delay oriented pass transistor logic synthesis. IEEE Trans. VLSI Syst. 13(8): 957-970 (2005)
116EEHaifeng Qian, Sani R. Nassif, Sachin S. Sapatnekar: Early-stage power grid analysis for uncertain working modes. IEEE Trans. on CAD of Integrated Circuits and Systems 24(5): 676-682 (2005)
115EEJaskirat Singh, Sachin S. Sapatnekar: Congestion-aware topology optimization of structured power/ground networks. IEEE Trans. on CAD of Integrated Circuits and Systems 24(5): 683-695 (2005)
114EERupesh S. Shelar, Sachin S. Sapatnekar, Prashant Saxena, Xinning Wang: A predictive distributed congestion metric with application to technology mapping. IEEE Trans. on CAD of Integrated Circuits and Systems 24(5): 696-710 (2005)
113EEHaifeng Qian, Sani R. Nassif, Sachin S. Sapatnekar: Power grid analysis using random walks. IEEE Trans. on CAD of Integrated Circuits and Systems 24(8): 1204-1224 (2005)
112EEHongliang Chang, Sachin S. Sapatnekar: Statistical timing analysis under spatial correlations. IEEE Trans. on CAD of Integrated Circuits and Systems 24(9): 1467-1482 (2005)
2004
111EEHaifeng Qian, Sachin S. Sapatnekar: Hierarchical random-walk algorithms for power grid analysis. ASP-DAC 2004: 499-504
110EEVidyasagar Nookala, Sachin S. Sapatnekar: A method for correcting the functionality of a wire-pipelined circuit. DAC 2004: 570-575
109EEAnup Kumar Sultania, Dennis Sylvester, Sachin S. Sapatnekar: Tradeoffs between date oxide leakage and delay for dual Tox circuits. DAC 2004: 761-766
108EEYong Zhan, Sachin S. Sapatnekar: Optimization of Integrated Spiral Inductors Using Sequential Quadratic Programming. DATE 2004: 622-629
107EEShrirang K. Karandikar, Sachin S. Sapatnekar: Fast Comparisons of Circuit Implementations. DATE 2004: 910-915
106EEHaifeng Qian, Joseph N. Kozhaya, Sani R. Nassif, Sachin S. Sapatnekar: A chip-level electrostatic discharge simulation strategy. ICCAD 2004: 315-318
105EEShrirang K. Karandikar, Sachin S. Sapatnekar: Logical effort based technology mapping. ICCAD 2004: 419-422
104EECharles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Cliff C. N. Sze: Accurate estimation of global buffer delay within a floorplan. ICCAD 2004: 706-711
103EEAnup Kumar Sultania, Dennis Sylvester, Sachin S. Sapatnekar: Transistor and Pin Reordering for Gate Oxide Leakage Reduction in Dual T{ox} Circuits. ICCD 2004: 228-233
102EETianpei Zhang, Sachin S. Sapatnekar: Simultaneous Shield and Buffer Insertion for Crosstalk Noise Reduction in Global Routing. ICCD 2004: 93-98
101EEJaskirat Singh, Sachin S. Sapatnekar: Topology optimization of structured power/ground networks. ISPD 2004: 116-123
100EEHaifeng Qian, Sani R. Nassif, Sachin S. Sapatnekar: Early-stage power grid analysis for uncertain working modes. ISPD 2004: 132-137
99EERupesh S. Shelar, Sachin S. Sapatnekar, Prashant Saxena, Xinning Wang: A predictive distributed congestion metric and its application to technology mapping. ISPD 2004: 210-217
98EEHongliang Chang, Haifeng Qian, Sachin S. Sapatnekar: The Certainty of Uncertainty: Randomness in Nanometer Design. PATMOS 2004: 36-47
97EESachin S. Sapatnekar: High-Performance Power Grids For Nanometer Technologies. VLSI Design 2004: 839-844
96EEVijay Sundararajan, Sachin S. Sapatnekar, Keshab K. Parhi: A new approach for integration of min-area retiming and min-delay padding for simultaneously addressing short-path and long-path constraints. ACM Trans. Design Autom. Electr. Syst. 9(3): 273-289 (2004)
95EEHaihua Su, Jiang Hu, Sachin S. Sapatnekar, Sani R. Nassif: A methodology for the simultaneous design of supply and signal networks. IEEE Trans. on CAD of Integrated Circuits and Systems 23(12): 1614-1624 (2004)
2003
94EEHaifeng Qian, Sani R. Nassif, Sachin S. Sapatnekar: Random walks in a supply network. DAC 2003: 93-98
93EEHongliang Chang, Sachin S. Sapatnekar: Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal. ICCAD 2003: 621-626
92EEBrent Goplen, Sachin S. Sapatnekar: Efficient Thermal Placement of Standard Cells in 3D ICs using a Force Directed Approach. ICCAD 2003: 86-90
91EEVenkatesan Rajappan, Sachin S. Sapatnekar: An Efficient Algorithm for Calculating the Worst-case Delay due to Crosstalk. ICCD 2003: 76-
90EEHaitian Hu, David Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar: Table look-up based compact modeling for on-chip interconnect timing and noise analysis. ISCAS (4) 2003: 668-671
89EEGuoqiang Chen, Sachin S. Sapatnekar: Partition-driven standard cell thermal placement. ISPD 2003: 75-80
88EESachin S. Sapatnekar, Haihua Su: Analysis and Optimization of Power Grids. IEEE Design & Test of Computers 20(3): 7-15 (2003)
87EEShrirang K. Karandikar, Sachin S. Sapatnekar: Technology mapping for SOI domino logic incorporating solutions for the parasitic bipolar effect. IEEE Trans. VLSI Syst. 11(6): 1094-1105 (2003)
86EEHaitian Hu, David T. Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar: Fast on-chip inductance simulation using a precorrected-FFT method. IEEE Trans. on CAD of Integrated Circuits and Systems 22(1): 49-66 (2003)
85EEHaihua Su, Kaushik Gala, Sachin S. Sapatnekar: Analysis and optimization of structured power/ground networks. IEEE Trans. on CAD of Integrated Circuits and Systems 22(11): 1533-1544 (2003)
84EECharles J. Alpert, Sachin S. Sapatnekar: Guest editorial. IEEE Trans. on CAD of Integrated Circuits and Systems 22(4): 385-386 (2003)
83EEHaihua Su, Sachin S. Sapatnekar, Sani R. Nassif: Optimal decoupling capacitor sizing and placement for standard-cell layout designs. IEEE Trans. on CAD of Integrated Circuits and Systems 22(4): 428-436 (2003)
82EECharles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Paul Villarrubia: A practical methodology for early buffer and wire resource allocation. IEEE Trans. on CAD of Integrated Circuits and Systems 22(5): 573-583 (2003)
2002
81EEHaihua Su, Jiang Hu, Sachin S. Sapatnekar, Sani R. Nassif: Congestion-driven codesign of power and signal networks. DAC 2002: 64-69
80EEHaitian Hu, David Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar: A precorrected-FFT method for simulating on-chip inductance. ICCAD 2002: 221-227
79EEMahesh Ketkar, Sachin S. Sapatnekar: Standby power optimization via transistor sizing and dual threshold voltage assignment. ICCAD 2002: 375-378
78EEHaitian Hu, Sachin S. Sapatnekar: Efficient PEEC-Based Inductance Extraction Using Circuit-Aware Techniques. ICCD 2002: 434-
77EEHaihua Su, Sachin S. Sapatnekar, Sani R. Nassif: An algorithm for optimal decoupling capacitor sizing and placement for standard cell layouts. ISPD 2002: 68-73
76 Rupesh S. Shelar, Sachin S. Sapatnekar: Efficient Layout Synthesis Algorithm for Pass Transistor Logic Circuits. IWLS 2002: 209-214
75EETianpei Zhang, Sachin S. Sapatnekar: Optimized pin assignment for lower routing congestion after floorplanning phase. SLIP 2002: 17-21
74EERupesh S. Shelar, Sachin S. Sapatnekar: An Efficient Algorithm for Low Power Pass Transistor Logic Synthesis. VLSI Design 2002: 87-92
73EEMin Zhao, Sachin S. Sapatnekar: Technology mapping algorithms for domino logic. ACM Trans. Design Autom. Electr. Syst. 7(2): 306-335 (2002)
72EEJatuchai Pangjun, Sachin S. Sapatnekar: Low-power clock distribution using multiple voltages and reduced swings. IEEE Trans. VLSI Syst. 10(3): 309-318 (2002)
71EEHaitian Hu, Sachin S. Sapatnekar: Efficient inductance extraction using circuit-aware techniques. IEEE Trans. VLSI Syst. 10(6): 746-761 (2002)
70EEMin Zhao, Rajendran Panda, Sachin S. Sapatnekar, David T. Blaauw: Hierarchical analysis of power distribution networks. IEEE Trans. on CAD of Integrated Circuits and Systems 21(2): 159-168 (2002)
69EEVijay Sundararajan, Sachin S. Sapatnekar, Keshab K. Parhi: Fast and exact transistor sizing based on iterative relaxation. IEEE Trans. on CAD of Integrated Circuits and Systems 21(5): 568-581 (2002)
68EEJiang Hu, Sachin S. Sapatnekar: A timing-constrained simultaneous global routing algorithm. IEEE Trans. on CAD of Integrated Circuits and Systems 21(9): 1025-1036 (2002)
67EESuresh Raman, Sachin S. Sapatnekar, Charles J. Alpert: Probability-driven routing in a datapath environment. Integration 31(2): 159-182 (2002)
2001
66EECharles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Paul Villarrubia: A Practical Methodology for Early Buffer and Wire Resource Allocation. DAC 2001: 189-194
65EEMin Zhao, Sachin S. Sapatnekar: A New Structural Pattern Matching Algorithm for Technology Mapping. DAC 2001: 371-376
64EEShrirang K. Karandikar, Sachin S. Sapatnekar: Technology Mapping for SOI Domino Logic Incorporating Solutions for the Parasitic Bipolar Effect. DAC 2001: 377-382
63EEHaihua Su, Sachin S. Sapatnekar: Hybrid Structured Clock Network Construction. ICCAD 2001: 333-336
62EERupesh S. Shelar, Sachin S. Sapatnekar: Recursive Bipartitioning of BDDs for Performance Driven Synthesis of Pass Transistor Logic Circuits. ICCAD 2001: 449-452
61 Jiang Hu, Sachin S. Sapatnekar: Performance Driven Global Routing Through Gradual Refinement. ICCD 2001: 481-483
60EECharles J. Alpert, Gopal Gandham, Jiang Hu, José Luis Neves, Stephen T. Quay, Sachin S. Sapatnekar: Steiner tree optimization for buffers. Blockages and bays. ISCAS (5) 2001: 399-402
59EECharles J. Alpert, Milos Hrkic, Jiang Hu, Andrew B. Kahng, John Lillis, Bao Liu, Stephen T. Quay, Sachin S. Sapatnekar, A. J. Sullivan, Paul Villarrubia: Buffered Steiner trees for difficult instances. ISPD 2001: 4-9
58 Noel Menezes, Sachin S. Sapatnekar: Optimization and Analysis Techniques for the Deep Submicron Regime. VLSI Design 2001: 3-4
57EEYanbin Jiang, Sachin S. Sapatnekar, Cyrus Bamji: Technology mapping for high-performance static CMOS and pass transistor logic designs. IEEE Trans. VLSI Syst. 9(5): 577-589 (2001)
56EECharles J. Alpert, Gopal Gandham, Jiang Hu, José Luis Neves, Stephen T. Quay, Sachin S. Sapatnekar: Steiner tree optimization for buffers, blockages, and bays. IEEE Trans. on CAD of Integrated Circuits and Systems 20(4): 556-562 (2001)
55EEMartin Kuhlmann, Sachin S. Sapatnekar: Exact and efficient crosstalk estimation. IEEE Trans. on CAD of Integrated Circuits and Systems 20(7): 858-866 (2001)
54EEJiang Hu, Sachin S. Sapatnekar: A survey on multi-net global routing for integrated circuits. Integration 31(1): 1-49 (2001)
2000
53EEMin Zhao, Rajendran Panda, Sachin S. Sapatnekar, Tim Edwards, Rajat Chaudhry, David Blaauw: Hierarchical analysis of power distribution networks. DAC 2000: 150-155
52EEVijay Sundararajan, Sachin S. Sapatnekar, Keshab K. Parhi: MINFLOTRANSIT: min-cost flow based transistor sizing tool. DAC 2000: 649-664
51EEMahesh Ketkar, Kishore Kasamsetty, Sachin S. Sapatnekar: Convex delay models for transistor sizing. DAC 2000: 655-660
50 Haihua Su, Kaushik Gala, Sachin S. Sapatnekar: Fast Analysis and Optimization of Power/Ground Networks. ICCAD 2000: 477-480
49 Jiang Hu, Sachin S. Sapatnekar: A Timing-Constrained Algorithm for Simultaneous Global Routing of Multiple Nets. ICCAD 2000: 99-103
48EESuresh Raman, Sachin S. Sapatnekar, Charles J. Alpert: Datapath routing based on a decongestion metric. ISPD 2000: 122-127
47EESachin S. Sapatnekar: Capturing the Effect of Crosstalk on Delay. VLSI Design 2000: 364-369
46EESachin S. Sapatnekar, Weitong Chuang: Power-delay optimizations in gate sizing. ACM Trans. Design Autom. Electr. Syst. 5(1): 98-114 (2000)
45EEMin Zhao, Sachin S. Sapatnekar: Timing-driven partitioning and timing optimization of mixedstatic-domino implementations. IEEE Trans. on CAD of Integrated Circuits and Systems 19(11): 1322-1336 (2000)
44EEJiang Hu, Sachin S. Sapatnekar: Algorithms for non-Hanan-based optimization for VLSI interconnectunder a higher-order AWE model. IEEE Trans. on CAD of Integrated Circuits and Systems 19(4): 446-458 (2000)
43EESachin S. Sapatnekar: A timing model incorporating the effect of crosstalk on delay andits application to optimal channel routing. IEEE Trans. on CAD of Integrated Circuits and Systems 19(5): 550-559 (2000)
42EEKishore Kasamsetty, Mahesh Ketkar, Sachin S. Sapatnekar: A new class of convex functions for delay modeling and itsapplication to the transistor sizing problem [CMOS gates]. IEEE Trans. on CAD of Integrated Circuits and Systems 19(7): 779-788 (2000)
1999
41EEJiang Hu, Sachin S. Sapatnekar: FAR-DS: Full-Plane AWE Routing with Driver Sizing. DAC 1999: 84-89
40EEYanbin Jiang, Sachin S. Sapatnekar: An integrated algorithm for combined placement and libraryless technology mapping. ICCAD 1999: 102-106
39EEMin Zhao, Sachin S. Sapatnekar: Timing-driven partitioning for two-phase domino and mixed static/domino implementations. ICCAD 1999: 107-110
38EEVijay Sundararajan, Sachin S. Sapatnekar, Keshab K. Parhi: Marsh: min-area retiming with setup and hold constraints. ICCAD 1999: 2-6
37EEMartin Kuhlmann, Sachin S. Sapatnekar, Keshab K. Parhi: Efficient Crosstalk Estimation. ICCD 1999: 266-
36EEJatuchai Pangjun, Sachin S. Sapatnekar: Clock distribution using multiple voltages. ISLPED 1999: 145-150
35EEJiang Hu, Sachin S. Sapatnekar: Simultaneous buffer insertion and non-Hanan optimization for VLSI interconnect under a higher order AWE model. ISPD 1999: 133-138
34EEHuibo Hou, Jiang Hu, Sachin S. Sapatnekar: Non-Hanan routing. IEEE Trans. on CAD of Integrated Circuits and Systems 18(4): 436-444 (1999)
33EENaresh Maheshwari, Sachin S. Sapatnekar: Optimizing large multiphase level-clocked circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 18(9): 1249-1264 (1999)
32EENaresh Maheshwari, Sachin S. Sapatnekar: Retiming control logic. Integration 28(1): 33-53 (1999)
1998
31EENaresh Maheshwari, Sachin S. Sapatnekar: Efficient Minarea Retiming of Large Level-Clocked Circuits. DATE 1998: 840-
30EEMin Zhao, Sachin S. Sapatnekar: Technology mapping for domino logic. ICCAD 1998: 248-251
29EEHuibo Hou, Sachin S. Sapatnekar: Routing tree topology construction to meet interconnect timing constraints. ISPD 1998: 205-210
28EENaresh Maheshwari, Sachin S. Sapatnekar: Efficient retiming of large circuits. IEEE Trans. VLSI Syst. 6(1): 74-83 (1998)
27EEYanbin Jiang, Sachin S. Sapatnekar, Cyrus Bamji, Juho Kim: Interleaving buffer insertion and transistor sizing into a single optimization. IEEE Trans. VLSI Syst. 6(4): 625-633 (1998)
26EEHarsha Sathyamurthy, Sachin S. Sapatnekar, John P. Fishburn: Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 17(2): 173-182 (1998)
1997
25EENaresh Maheshwari, Sachin S. Sapatnekar: An Improved Algorithm for Minimum-Area Retiming. DAC 1997: 2-7
24EENaresh Maheshwari, Sachin S. Sapatnekar: Minimum area retiming with equivalent initial states. ICCAD 1997: 216-219
23EEJuho Kim, Cyrus Bamji, Yanbin Jiang, Sachin S. Sapatnekar: Concurrent transistor sizing and buffer insertion by considering cost-delay tradeoffs. ISPD 1997: 130-135
22EEShankar Ramaswamy, Sachin S. Sapatnekar, Prithviraj Banerjee: A Framework for Exploiting Task and Data Parallelism on Distributed Memory Multicomputers. IEEE Trans. Parallel Distrib. Syst. 8(11): 1098-1116 (1997)
1996
21EEDaksh Lehther, Sachin S. Sapatnekar: Clock tree synthesis for multi-chip modules. ICCAD 1996: 50-53
20EENaresh Maheshwari, Sachin S. Sapatnekar: A Practical Algorithm for Retiming Level-Clocked Circuits. ICCD 1996: 440-
19EEJatan C. Shah, Sachin S. Sapatnekar: Wiresizing with Buffer Placement and Sizing for Power-Delay Tradeoffs. VLSI Design 1996: 346-351
18EESachin S. Sapatnekar, Rahul B. Deokar: Utilizing the retiming-skew equivalence in a practical algorithm for retiming large circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 15(10): 1237-1248 (1996)
17EESachin S. Sapatnekar: Wire sizing as a convex optimization problem: exploring the area-delay tradeoff. IEEE Trans. on CAD of Integrated Circuits and Systems 15(8): 1001-1011 (1996)
16EEPiyush K. Sancheti, Sachin S. Sapatnekar: Optimal design of macrocells for low power and high speed. IEEE Trans. on CAD of Integrated Circuits and Systems 15(9): 1160-1166 (1996)
1995
15EERahul B. Deokar, Sachin S. Sapatnekar: A Fresh Look at Retiming Via Clock Skew Optimization. DAC 1995: 310-315
14EESachin S. Sapatnekar, Weitong Chuang: Power vs. delay in gate sizing: conflicting objectives? ICCAD 1995: 463-466
13EEHarsha Sathyamurthy, Sachin S. Sapatnekar, John P. Fishburn: Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization. ICCAD 1995: 467-470
12 Piyush K. Sancheti, Sachin S. Sapatnekar: Layout Optimization Using Arbitrarily High Degree Posynomial Models. ISCAS 1995: 53-56
11EEWeitong Chuang, Sachin S. Sapatnekar, Ibrahim N. Hajj: Timing and area optimization for standard-cell VLSI circuit design. IEEE Trans. on CAD of Integrated Circuits and Systems 14(3): 308-320 (1995)
1994
10EESachin S. Sapatnekar: RC Interconnect Optimization Under the Elmore Delay Model. DAC 1994: 387-391
9 Shankar Ramaswamy, Sachin S. Sapatnekar, Prithviraj Banerjee: A Convex Programming Approach for Exploiting Data and Functional Parallelism on Distributed Memory Multicomputers. ICPP 1994: 116-125
8 Jaewon Kim, Sung-Mo Kang, Sachin S. Sapatnekar: High Performance CMOS Macromodule Layout Synthesis. ISCAS 1994: 179-182
7 Rahul B. Deokar, Sachin S. Sapatnekar: A Graph-Theoretic Approach to Clock Skew Optimization. ISCAS 1994: 407-410
6EESachin S. Sapatnekar, Pravin M. Vaidya, Sung-Mo Kang: Convexity-based algorithms for design centering. IEEE Trans. on CAD of Integrated Circuits and Systems 13(12): 1536-1549 (1994)
1993
5EESachin S. Sapatnekar, Pravin M. Vaidya, Steve M. Kang: Convexity-based algorithms for design centering. ICCAD 1993: 206-209
4EEWeitong Chuang, Sachin S. Sapatnekar, Ibrahim N. Hajj: A unified algorithm for gate sizing and clock skew optimization to minimize sequential circuit area. ICCAD 1993: 220-223
3 Sachin S. Sapatnekar, Pravin M. Vaidya, Sung-Mo Kang: Feasible Region Approximation Using Convex Polytopes. ISCAS 1993: 1786-1789
2EESachin S. Sapatnekar, Vasant B. Rao, Pravin M. Vaidya, Sung-Mo Kang: An exact solution to the transistor sizing problem for CMOS circuits using convex optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 12(11): 1621-1634 (1993)
1991
1 Sachin S. Sapatnekar, Vasant B. Rao, Pravin M. Vaidya: A Convex Optimization Approach to Transistor Sizing for CMOS Circuits. ICCAD 1991: 482-485

Coauthor Index

1Cristinel Ababei [121]
2Charles J. Alpert [48] [56] [59] [60] [66] [67] [82] [84] [104] [141] [166]
3Cyrus Bamji [23] [27] [57]
4Prithviraj Banerjee (Prith Banerjee) [9] [22]
5Kia Bazargan [121] [169] [191]
6David Blaauw (David T. Blaauw) [53] [70] [80] [86] [90]
7Keith A. Bowman [148]
8Dmitry Bufistov [168]
9Tiago Muller Gil Cardoso [147]
10Krishnendu Chakrabarty [159]
11Hongliang Chang [93] [98] [112] [135] [165]
12Yao-Wen Chang [189]
13Rajat Chaudhry [53]
14Guoqiang Chen [89]
15Ying Chen [134] [150]
16Weitong Chuang [4] [11] [14] [46]
17Jordi Cortadella [168]
18Rahul B. Deokar [7] [15] [18]
19Anirudh Devgan [190]
20Tim Edwards [53]
21Hanyong Eom [153] [182]
22Yan Feng [121] [155]
23John P. Fishburn [13] [26]
24Kaushik Gala [50] [80] [85] [86] [90]
25Gopal Gandham [56] [60]
26Brent Goplen [92] [121] [127] [136] [142] [158] [171]
27Jie Gu [170] [184]
28Ibrahim N. Hajj [4] [11]
29Eshel Haritan [190]
30Ramesh Harjani [125]
31Chen He [161]
32Huibo Hou [29] [34]
33Milos Hrkic [59]
34Haitian Hu [71] [78] [80] [86] [90]
35Jiang Hu [34] [35] [41] [44] [49] [54] [56] [59] [60] [61] [66] [68] [81] [82] [95] [104] [141]
36Yanbin Jiang [23] [27] [40] [57]
37Andrew B. Kahng [59]
38Steve M. Kang [5]
39Sung-Mo Kang [2] [3] [6] [8]
40Shrirang K. Karandikar [64] [87] [105] [107] [119] [129] [180]
41Kishore Kasamsetty [42] [51]
42Chandramouli V. Kashyap [188]
43John Keane [153] [182] [184]
44Mahesh Ketkar [42] [51] [79]
45Kurt Keutzer [190]
46Chris H. Kim [149] [152] [153] [156] [170] [173] [182] [183] [184] [194]
47Jaewon Kim [8]
48Juho Kim [23] [27]
49Tae-Hyoung Kim [153] [182]
50Desmond Kirkpatrick [190]
51Michael Kishinevsky [168]
52Joseph N. Kozhaya [106]
53Martin Kuhlmann [37] [55]
54Sanjay V. Kumar [149] [152] [156] [173] [183] [187] [188] [194]
55Marcello Lajolo [161]
56Daksh Lehther [21]
57Zhuo Li [166]
58David J. Lilja [134] [150] [151]
59John Lillis [59]
60Bao Liu [59]
61Qunzeng Liu [172]
62Zhi-Quan Luo [137] [179]
63Enrico Macii [161]
64Naresh Maheshwari [20] [24] [25] [28] [31] [32] [33]
65Felipe S. Marques [140] [147] [175]
66Grant Martin [146]
67Stephen Meier [190]
68Noel Menezes [58]
69Hushrav Mogal [121] [169] [191]
70Sani R. Nassif [77] [81] [83] [94] [95] [100] [106] [113] [116]
71José Luis Neves [56] [60]
72Vidyasagar Nookala [110] [130] [134] [137] [150] [151]
73Kevin J. Nowka [122]
74Michael Orshansky [148]
75Rajendran Panda [53] [70] [80] [86] [90]
76Jatuchai Pangjun [36] [72]
77Keshab K. Parhi [37] [38] [52] [69] [96]
78Duaine Pryor [190]
79Haifeng Qian [94] [98] [100] [106] [111] [113] [116] [132] [169] [176] [191]
80Stephen T. Quay [56] [59] [60] [166]
81Venkatesan Rajappan [91]
82Suresh Raman [48] [67]
83Shankar Ramaswamy [9] [22]
84Vasant B. Rao [1] [2]
85André Inácio Reis [131] [140] [147] [175]
86Renato P. Ribas [131] [140] [147] [175]
87Leomar S. da Rosa Jr. [147] [175]
88Jaijeet S. Roychowdhury [125]
89Piyush K. Sancheti [12] [16]
90Harsha Sathyamurthy [13] [26]
91Prashant Saxena [99] [114] [128] [136] [144]
92Felipe Ribeiro Schneider [131]
93Jatan C. Shah [19]
94Rupesh S. Shelar [62] [74] [76] [99] [114] [117] [128] [144]
95Weiping Shi [166]
96Jaskirat Singh [101] [115] [126] [137] [143] [154] [179] [181]
97Tom Spyrou [190]
98Karthikk Sridharan [195]
99Leon Stok [163]
100Haihua Su [50] [63] [77] [81] [83] [85] [88] [95]
101A. J. Sullivan [59]
102Anup Kumar Sultania [103] [109] [118]
103Vijay Sundararajan [38] [52] [69] [96]
104Dennis Sylvester [103] [109] [118]
105Cliff C. N. Sze (Chin Ngai Sze, Cliff N. Sze) [104] [141]
106Pravin M. Vaidya [1] [2] [3] [5] [6]
107Gustavo de Veciana [161]
108Paul G. Villarrubia (Paul Villarrubia) [59] [66] [82]
109Xinning Wang [99] [114] [128]
110Chia-Lin Yang [189]
111Ping-Hung Yuh [189]
112Yong Zhan [108] [133] [138] [155] [157] [158] [160] [167] [177] [187]
113Tianpei Zhang [75] [102] [121] [139] [157] [162] [167] [178]
114Min Zhao [30] [39] [45] [53] [65] [70] [73] [80] [86] [90]
115Pingqiang Zhou [195]
116Vladimir Zolotov [80] [86] [90]

Colors in the list of coauthors

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)