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Daniel G. Saab Vis

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*2009
56EEKhawla Alzoubi, Daniel G. Saab, Massood Tabib-Azar: Complementary nano-electromechanical switches for ultra-low power embedded processors. ACM Great Lakes Symposium on VLSI 2009: 309-314
2007
55EEJen-Chieh Ou, Daniel G. Saab, Qiang Qiang, Jacob A. Abraham: Reducing verification overhead with RTL slicing. ACM Great Lakes Symposium on VLSI 2007: 399-404
54EESwarup Bhunia, Massood Tabib-Azar, Daniel G. Saab: Ultralow-Power Reconfigurable Computing with Complementary Nano-Electromechanical Carbon Nanotube Switches. ASP-DAC 2007: 86-91
53 Jason Meyer, Fatih Kocan, Daniel G. Saab: Critical Path Delay Reduction in FPGAs with Unbalanced Lookup Times. ERSA 2007: 182-190
52EESankar Gurumurthy, Ramtilak Vemu, Jacob A. Abraham, Daniel G. Saab: Automatic Generation of Instructions to Robustly Test Delay Defects in Processors. European Test Symposium 2007: 173-178
51EEJacob A. Abraham, Daniel G. Saab: Tutorial T4A: Formal Verification Techniques and Tools for Complex Designs. VLSI Design 2007: 6
50EEFatih Kocan, Daniel G. Saab: Dynamic Fault Diagnosis of Combinational and Sequential Circuits on Reconfigurable Hardware. J. Electronic Testing 23(5): 405-420 (2007)
2006
49EEQiang Qiang, Daniel G. Saab, Jacob A. Abraham: Checking Nested Properties Using Bounded Model Checking and Sequential ATPG. VLSI Design 2006: 225-230
2005
48 Qiang Qiang, Daniel G. Saab, Jacob A. Abraham: An Emulation Model for Sequential ATPG-Based Bounded Model Checking. FPL 2005: 469-474
47EEQiang Qiang, Chia-Lun Chang, Daniel G. Saab, Jacob A. Abraham: Case Study of ATPG-based Bounded Model Checking: Verifying USB2.0 IP Core. ICCD 2005: 461-463
2003
46EEDaniel G. Saab, Jacob A. Abraham, Vivekananda M. Vedula: Formal Verification Using Bounded Model Checking: SAT versus Sequential ATPG Engines. VLSI Design 2003: 243-248
2002
45EEDaniel G. Saab, Fatih Kocan, Jacob A. Abraham: Massively Parallel/Reconfigurable Emulation Model for the D-algorithm. FPL 2002: 1172-1176
44EEJacob A. Abraham, Vivekananda M. Vedula, Daniel G. Saab: Verifying Properties Using Sequential ATPG. ITC 2002: 194-202
43EEFatih Kocan, Daniel G. Saab: Correction to "ATPG for combinational circuits on configurable hardware". IEEE Trans. VLSI Syst. 10(3): 374-374 (2002)
2001
42EEFatih Kocan, Daniel G. Saab: ATPG for combinational circuits on configurable hardware. IEEE Trans. VLSI Syst. 9(1): 117-129 (2001)
2000
41EERaghuram S. Tupuri, Jacob A. Abraham, Daniel G. Saab: Hierarchical Test Generation for Systems On a Chip. VLSI Design 2000: 198-
1999
40EEMiron Abramovici, José T. de Sousa, Daniel G. Saab: A Massively-Parallel Easily-Scalable Satisfiability Solver Using Reconfigurable Hardware. DAC 1999: 684-690
39EEFatih Kocan, Daniel G. Saab: Dynamic Fault Diagnosis on Reconfigurable Hardware. DAC 1999: 691-696
38EEFatih Kocan, Daniel G. Saab: Concurrent D-algorithm on reconfigurable hardware. ICCAD 1999: 152-156
37EEBen Mathew, Daniel G. Saab: Combining multiple DFT schemes with test generation. IEEE Trans. on CAD of Integrated Circuits and Systems 18(6): 685-696 (1999)
1998
36EEJalal A. Wehbeh, Daniel G. Saab: Initialization of Sequential Circuits and its Application to ATPG. J. Electronic Testing 13(3): 259-271 (1998)
1997
35 Miron Abramovici, Daniel G. Saab: Satisfiability on reconfigurable hardware. FPL 1997: 448-456
1996
34EEJalal A. Wehbeh, Daniel G. Saab: Initialization of sequential circuits and its application to ATPG. VTS 1996: 246-253
33EEDaniel G. Saab, Youssef Saab, Jacob A. Abraham: Automatic test vector cultivation for sequential VLSI circuits using genetic algorithms. IEEE Trans. on CAD of Integrated Circuits and Systems 15(10): 1278-1285 (1996)
32 Antoine N. Mourad, W. Kent Fuchs, Daniel G. Saab: Site Partitioning for Redundant Arrays of Distributed Disks. J. Parallel Distrib. Comput. 33(1): 1-11 (1996)
1995
31 Ben Mathew, Daniel G. Saab: DFT & ATPG: Together Again. ITC 1995: 262-271
1994
30 Elizabeth M. Rudnick, John G. Holm, Daniel G. Saab, Janak H. Patel: Application of Simple Genetic Algorithms to Sequential Circuit Test Generation. EDAC-ETC-EUROASIC 1994: 40-45
29EEDaniel G. Saab, Youssef Saab, Jacob A. Abraham: Iterative [simulation-based genetics + deterministic techniques]= complete ATPG0. ICCAD 1994: 40-43
28 Jalal A. Wehbeh, Daniel G. Saab: On the Initialization of Sequential Circuits. ITC 1994: 233-239
27EEChung-Hsing Chen, Tanay Karnik, Daniel G. Saab: Structural and behavioral synthesis for testability techniques. IEEE Trans. on CAD of Integrated Circuits and Systems 13(6): 777-785 (1994)
1993
26EEGwan S. Choi, Ravishankar K. Iyer, Daniel G. Saab: Fault behavior dictionary for simulation of device-level transients. ICCAD 1993: 6-9
25EEBen Mathew, Daniel G. Saab: Augmented partial reset. ICCAD 1993: 716-719
24 Antoine N. Mourad, W. Kent Fuchs, Daniel G. Saab: Performance of Redundant Disk Array Organizations in Transaction Processing Environments. ICPP 1993: 138-145
23 Antoine N. Mourad, W. Kent Fuchs, Daniel G. Saab: Assigning Sites fto Redundant Clusters in a Distributed Storage System. ICPP 1993: 64-71
22 Miron Abramovici, Prashant S. Parikh, Ben Mathew, Daniel G. Saab: On Selecting Flip-Flops for Partial Reset. ITC 1993: 1008-1012
21 Praveen Vishakantaiah, Jacob A. Abraham, Daniel G. Saab: CHEETA: Composition of Hierarchical Sequential Tests Using ATKET. ITC 1993: 606-615
20EERobert B. Mueller-Thuns, Daniel G. Saab, Robert F. Damiano, Jacob A. Abraham: Benchmarking Parallel Processing Platforms: An Applications Perspective. IEEE Trans. Parallel Distrib. Syst. 4(8): 947-954 (1993)
19EEDaniel G. Saab: Parallel-concurrent fault simulation. IEEE Trans. VLSI Syst. 1(3): 356-364 (1993)
18EEChung-Hsing Chen, Daniel G. Saab: A novel behavioral testability measure. IEEE Trans. on CAD of Integrated Circuits and Systems 12(12): 1960-1970 (1993)
17EERobert B. Mueller-Thuns, Daniel G. Saab, Robert F. Damiano, Jacob A. Abraham: VLSI logic and fault simulation on general-purpose parallel computers. IEEE Trans. on CAD of Integrated Circuits and Systems 12(3): 446-460 (1993)
16EEAndrew T. Yang, Yu-Hsu Chang, Daniel G. Saab, Ibrahim N. Hajj: Switch-level timing simulation of bipolar ECL circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 12(4): 516-530 (1993)
15 Antoine N. Mourad, W. Kent Fuchs, Daniel G. Saab: Recovery Issues in Databases Using Redundant Disk Arrays. J. Parallel Distrib. Comput. 17(1-2): 75-89 (1993)
1992
14EEDaniel G. Saab, Youssef Saab, Jacob A. Abraham: CRIS: a test cultivation program for sequential VLSI circuits. ICCAD 1992: 216-219
13EEChung-Hsing Chen, Daniel G. Saab: Behavioral synthesis for testability. ICCAD 1992: 612-615
12 Jalal A. Wehbeh, Daniel G. Saab: Hierarchical Simulation of MOS Circuits Using Extracted Functional Models. ICCD 1992: 512-515
11EEAntoine N. Mourad, W. Kent Fuchs, Daniel G. Saab: Database Recovery Using Redundant Disk Arrays. ICDE 1992: 176-183
10 Antoine N. Mourad, W. Kent Fuchs, Daniel G. Saab: Site Partitioning for Distributed Redundant Disk Arrays. RIDE-TQP 1992: 214
1991
9 Chung-Hsing Chen, Chienwen Wu, Daniel G. Saab: BETA: Behavioral Testability Analysis. ICCAD 1991: 202-205
8 Chung-Hsing Chen, Chienwen Wu, Daniel G. Saab: Accessibility Analysis on Data Flow Graph: An Approach to Design for Testability. ICCD 1991: 463-466
1990
7EEDavid T. Blaauw, Daniel G. Saab, Junsheng Long, Jacob A. Abraham: Derivation of signal flow for switch-level simulation. EURO-DAC 1990: 301-305
6 David Blaauw, Robert B. Mueller-Thuns, Daniel G. Saab, Prithviraj Banerjee, Jacob A. Abraham: SNEL: A Switch-Level Simulator Using Multiple Levels of Functional Abstraction. ICCAD 1990: 66-69
5EERobert B. Mueller-Thuns, Daniel G. Saab, Jacob A. Abraham: Design of a scalable parallel switch-level simulator for VLSI. SC 1990: 615-624
4EEDaniel G. Saab, Robert B. Mueller-Thuns, David Blaauw, Joseph T. Rahmeh, Jacob A. Abraham: Hierarchical multi-level fault simulation of large systems. J. Electronic Testing 1(2): 139-149 (1990)
1989
3EEDavid Blaauw, Daniel G. Saab, Robert B. Mueller-Thuns, Jacob A. Abraham, Joseph T. Rahmeh: Automatic Generation of Behavioral Models from Switch-Level Descriptions. DAC 1989: 179-184
1988
2EEDaniel G. Saab, Andrew T. Yang, Ibrahim N. Hajj: Delay Modeling and Time of Bipolar Digital Circuits. DAC 1988: 288-293
1987
1EEIbrahim N. Hajj, Daniel G. Saab: Switch-Level Logic Simulation of Digital Bipolar Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 6(2): 251-258 (1987)

Coauthor Index

1Jacob A. Abraham [3] [4] [5] [6] [7] [14] [17] [20] [21] [29] [33] [41] [44] [45] [46] [47] [48] [49] [51] [52] [55]
2Miron Abramovici [22] [35] [40]
3Khawla Alzoubi [56]
4Prithviraj Banerjee (Prith Banerjee) [6]
5Swarup Bhunia [54]
6David Blaauw (David T. Blaauw) [3] [4] [6] [7]
7Chia-Lun Chang [47]
8Yu-Hsu Chang [16]
9Chung-Hsing Chen [8] [9] [13] [18] [27]
10Gwan S. Choi (Gwan Choi) [26]
11Robert F. Damiano [17] [20]
12W. Kent Fuchs [10] [11] [15] [23] [24] [32]
13Sankar Gurumurthy [52]
14Ibrahim N. Hajj [1] [2] [16]
15John G. Holm [30]
16Ravishankar K. Iyer (Ravi K. Iyer) [26]
17Tanay Karnik [27]
18Fatih Kocan [38] [39] [42] [43] [45] [50] [53]
19Junsheng Long [7]
20Ben Mathew [22] [25] [31] [37]
21Jason Meyer [53]
22Antoine N. Mourad [10] [11] [15] [23] [24] [32]
23Robert B. Mueller-Thuns [3] [4] [5] [6] [17] [20]
24Jen-Chieh Ou [55]
25Prashant S. Parikh [22]
26Janak H. Patel [30]
27Qiang Qiang [47] [48] [49] [55]
28Joseph T. Rahmeh [3] [4]
29Elizabeth M. Rudnick [30]
30Youssef Saab [14] [29] [33]
31José T. de Sousa [40]
32Massood Tabib-Azar [54] [56]
33Raghuram S. Tupuri [41]
34Vivekananda M. Vedula [44] [46]
35Ramtilak Vemu [52]
36Praveen Vishakantaiah [21]
37Jalal A. Wehbeh [12] [28] [34] [36]
38Chienwen Wu [8] [9]
39Andrew T. Yang [2] [16]

Colors in the list of coauthors

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)