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Rob A. Rutenbar Vis

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*2009
103EEPatrick Groeneveld, Rob A. Rutenbar, Jed W. Pitera, Erik C. Carlson, Jinsong Chen: Oil fields, hedge funds, and drugs. DAC 2009: 416-417
102EEEdward C. Lin, Rob A. Rutenbar: A multi-fpga 10x-real-time high-speed search engine for a 5000-word vocabulary speech recognizer. FPGA 2009: 83-92
2008
101EEAndreas Kuehlmann, Anjan Bose, David E. Corman, Rob A. Rutenbar, Robert M. Manning, Anna Newman: Verifying really complex systems: on earth and beyond. DAC 2008: 552-553
100EEAmith Singhee, Sonia Singhal, Rob A. Rutenbar: Exploiting Correlation Kernels for Efficient Handling of Intra-Die Spatial Correlation, with Application to Statistical Timing. DATE 2008: 856-861
99EEAmith Singhee, Sonia Singhal, Rob A. Rutenbar: Practical, fast Monte Carlo statistical static timing analysis: why and how. ICCAD 2008: 190-195
98EEAmith Singhee, Jiajing Wang, Benton H. Calhoun, Rob A. Rutenbar: Recursive Statistical Blockade: An Enhanced Technique for Rare Event Simulation with Application to SRAM Circuit Design. VLSI Design 2008: 131-136
97EEAmith Singhee, Claire Fang Fang, James D. Ma, Rob A. Rutenbar: Probabilistic Interval-Valued Computation: Toward a Practical Surrogate for Statistics Inside CAD Tools. IEEE Trans. on CAD of Integrated Circuits and Systems 27(12): 2317-2330 (2008)
2007
96EERob A. Rutenbar: Next-Generation Design and EDA Challenges: Small Physics, Big Systems, and Tall Tool-Chains. ASP-DAC 2007
95EEAmith Singhee, Rob A. Rutenbar: Beyond Low-Order Statistical Response Surfaces: Latent Variable Regression for Efficient, Highly Nonlinear Fitting. DAC 2007: 256-261
94EEAmith Singhee, Rob A. Rutenbar: Statistical blockade: a novel method for very fast Monte Carlo simulation of rare circuit events, and its application. DATE 2007: 1379-1384
93EEEdward C. Lin, Kai Yu, Rob A. Rutenbar, Tsuhan Chen: A 1000-word vocabulary, speaker-independent, continuous live-mode speech recognizer implemented in a single FPGA. FPGA 2007: 60-68
92EEZhong Xiu, Rob A. Rutenbar: Mixed-size placement with fixed macrocells using grid-warping. ISPD 2007: 103-110
91EEAmith Singhee, Rob A. Rutenbar: From Finance to Flip Flops: A Study of Fast Quasi-Monte Carlo Methods from Computational Finance Applied to Statistical Circuit Analysis. ISQED 2007: 685-692
90EEYu-Tsun Chien, Dong Chen, Jea-Hong Lou, Gin-Kou Ma, Rob A. Rutenbar, Tamal Mukherjee: Designer-Driven Topology Optimization for Pipelined Analog to Digital Converters CoRR abs/0710.4722: (2007)
89EEJames D. Ma, Rob A. Rutenbar: Interval-Valued Reduced-Order Statistical Interconnect Modeling. IEEE Trans. on CAD of Integrated Circuits and Systems 26(9): 1602-1613 (2007)
2006
88EEAmith Singhee, Claire Fang Fang, James D. Ma, Rob A. Rutenbar: Probabilistic interval-valued computation: toward a practical surrogate for statistics inside CAD tools. DAC 2006: 167-172
87EESaurabh K. Tiwary, Pragati K. Tiwary, Rob A. Rutenbar: Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration. DAC 2006: 31-36
86EEGoran Frehse, Bruce H. Krogh, Rob A. Rutenbar: Verifying analog oscillator circuits using forward/backward abstraction refinement. DATE 2006: 257-262
85EERob A. Rutenbar: Design automation for analog: the next generation of tool challenges. ICCAD 2006: 458-460
84EESaurabh K. Tiwary, Rob A. Rutenbar: Faster, parametric trajectory-based macromodels via localized linear reductions. ICCAD 2006: 876-883
83EEGoran Frehse, Bruce H. Krogh, Rob A. Rutenbar, Oded Maler: Time Domain Verification of Oscillator Circuit Properties. Electr. Notes Theor. Comput. Sci. 153(3): 9-22 (2006)
82EEJames D. Ma, Rob A. Rutenbar: Fast Interval-Valued Statistical Modeling of Interconnect and Effective Capacitance. IEEE Trans. on CAD of Integrated Circuits and Systems 25(4): 710-724 (2006)
2005
81EESaurabh K. Tiwary, Rob A. Rutenbar: Scalable trajectory methods for on-demand analog macromodel extraction. DAC 2005: 403-408
80EEZhong Xiu, Rob A. Rutenbar: Timing-driven placement by grid-warping. DAC 2005: 585-591
79EEYu-Tsun Chien, Dong Chen, Jea-Hong Lou, Gin-Kou Ma, Rob A. Rutenbar, Tamal Mukherjee: Designer-Driven Topology Optimization for Pipelined Analog to Digital Converters. DATE 2005: 279-280
78 James D. Ma, Claire Fang Fang, Rob A. Rutenbar, Xiaolin Xie, Duane S. Boning: Interval-valued statistical modeling of oxide chemical-mechanical polishing. ICCAD 2005: 141-148
77EEJames D. Z. Ma, Rob A. Rutenbar: Fast interval-valued statistical interconnect modeling and reduction. ISPD 2005: 159-166
76EEZhong Xiu, David A. Papa, Philip Chong, Christoph Albrecht, Andreas Kuehlmann, Rob A. Rutenbar, Igor L. Markov: Early research experience with OpenAccess gear: an open source development environment for physical design. ISPD 2005: 94-100
2004
75EEGang Zhang, E. Aykut Dengi, Ronald A. Rohrer, Rob A. Rutenbar, L. Richard Carley: A synthesis flow toward fast parasitic closure for radio-frequency integrated circuits. DAC 2004: 155-158
74EEZhong Xiu, James D. Z. Ma, Suzanne M. Fowler, Rob A. Rutenbar: Large-scale placement by grid-warping. DAC 2004: 351-356
73EERob A. Rutenbar, Anthony R. Bonaccio, Teresa H. Y. Meng, Ernesto Perea, Robert Pitts, Charles Sodini, Jim Wieser: Will Moore's Law rule in the land of analog? DAC 2004: 633
72EESmriti Gupta, Bruce H. Krogh, Rob A. Rutenbar: Towards formal verification of analog designs. ICCAD 2004: 210-217
71EEJames D. Ma, Rob A. Rutenbar: Interval-valued reduced order statistical interconnect modeling. ICCAD 2004: 460-467
70EERob A. Rutenbar, Li-C. Wang, Kwang-Ting Cheng, Sandip Kundu: Static statistical timing analysis for latch-based pipeline designs. ICCAD 2004: 468-472
69EEGi-Joon Nam, Fadi A. Aloul, Karem A. Sakallah, Rob A. Rutenbar: A Comparative Study of Two Boolean Formulations of FPGA Detailed Routing Constraints. IEEE Trans. Computers 53(6): 688-696 (2004)
2003
68EERob A. Rutenbar, David L. Harame, Kurt Johnson, Paul Kempf, Teresa H. Y. Meng, Reza Rofougaran, James Spoto: Mixed signals on mixed-signal: the right next technology. DAC 2003: 278-279
67EEClaire Fang Fang, Rob A. Rutenbar, Markus Püschel, Tsuhan Chen: Toward efficient static analysis of finite-precision effects in DSP applications via affine arithmetic modeling. DAC 2003: 496-501
66EEClaire Fang Fang, Rob A. Rutenbar, Tsuhan Chen: Fast, Accurate Static Analysis for Fixed-Point Finite-Precision Effects in DSP Designs. ICCAD 2003: 275-282
65EEHui Xu, Rob A. Rutenbar, Karem A. Sakallah: sub-SAT: a formulation for relaxed Boolean satisfiability with applications in routing. IEEE Trans. on CAD of Integrated Circuits and Systems 22(6): 814-820 (2003)
2002
64EEHongzhou Liu, Amith Singhee, Rob A. Rutenbar, L. Richard Carley: Remembrance of circuits past: macromodeling by data mining in large analog design spaces. DAC 2002: 437-442
63EEGi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar: Hybrid Routing for FPGAs by Integrating Boolean Satisfiability with Geometric Search. FPL 2002: 360-369
62EEHui Xu, Rob A. Rutenbar, Karem A. Sakallah: sub-SAT: a formulation for relaxed boolean satisfiability with applications in routing. ISPD 2002: 182-187
61EEGi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar: A new FPGA detailed routing approach via search-based Booleansatisfiability. IEEE Trans. on CAD of Integrated Circuits and Systems 21(6): 674-684 (2002)
2001
60EERob A. Rutenbar, Max Baron, Thomas Daniel, Rajeev Jayaraman, Zvi Or-Bach, Jonathan Rose, Carl Sechen: Panel: (When) Will FPGAs Kill ASICs? DAC 2001: 321-322
59EEGi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar: A boolean satisfiability-based incremental rerouting approach with application to FPGAs. DATE 2001: 560-565
58EERob A. Rutenbar: Synthesis for Industrial-Scale Analog Intellectual Property. Evolvable Hardware 2001: 3-6
57EEMichael Krasnicki, Rodney Phelps, James R. Hellums, Mark McClung, Rob A. Rutenbar, L. Richard Carley: ASF: A Practical Simulation-Based Methodology for the Synthesis of Custom Analog Circuits. ICCAD 2001: 350-357
56EEPrakash Gopalakrishnan, Rob A. Rutenbar: Direct Transistor-Level Layout for Digital Blocks. ICCAD 2001: 577-
55EERob A. Rutenbar, Olivier Coudert, Patrick Groeneveld, Jürgen Koehl, Scott Peterson, Vivek Raghavan, Naresh Soni: Automatic Hierarchical Design: Fantasy or Reality? (Panel). ICCAD 2001: 656-
54EEDomine Leenaerts, Rob A. Rutenbar, Georges G. E. Gielen: Embedded Tutorial: CAD Solutions and Outstanding Challenges for Mixed-Signal and RF IC Design. ICCAD 2001
53EERob A. Rutenbar, L. Richard Carley, Roberto Zafalon, Nicola Dragone: Low-power technology mapping for mixed-swing logic. ISLPED 2001: 291-294
52EEGi-Joon Nam, Fadi A. Aloul, Karem A. Sakallah, Rob A. Rutenbar: A comparative study of two Boolean formulations of FPGA detailed routing constraints. ISPD 2001: 222-227
51EERony Kay, Rob A. Rutenbar: Wire packing - a strong formulation of crosstalk-aware chip-leveltrack/layer assignment with an efficient integer programming solution. IEEE Trans. on CAD of Integrated Circuits and Systems 20(5): 672-679 (2001)
2000
50EERodney Phelps, Michael Krasnicki, Rob A. Rutenbar, L. Richard Carley, James R. Hellums: A case study of synthesis for industrial-scale analog IP: redesign of the equalizer/filter frontend for an ADSL CODEC. DAC 2000: 1-6
49EEStephan Ohr, Rob A. Rutenbar, Henry Chang, Georges G. E. Gielen, Rudolf Koch, Roy McGuffin, K. C. Murphy: Survival strategies for mixed-signal systems-on-chip (panel session). DAC 2000: 579-580
48EEJohn M. Cohn, Rob A. Rutenbar, Steve Young, Chris Malachowsky, Luis Aldaz: Case studies: Chip design on the bleeding edge (panel session abstract). DAC 2000: 648
47EERob A. Rutenbar, Cheming Hu, Mark Horowitz, Stephen Y. Chow: Life at the end of CMOS scaling (and beyond) (panel session) (abstract only). DAC 2000: 85
46EERony Kay, Rob A. Rutenbar: Wire packing: a strong formulation of crosstalk-aware chip-level track/layer assignment with an efficient integer programming solution. ISPD 2000: 61-68
45EERob A. Rutenbar, John M. Cohn: Layout tools for analog ICs and mixed-signal SoCs: a survey. ISPD 2000: 76-83
44EEJ. Y. F. Tong, David Nagle, Rob A. Rutenbar: Reducing power by optimizing the necessary precision/range of floating-point arithmetic. IEEE Trans. VLSI Syst. 8(3): 273-286 (2000)
43EERodney Phelps, Michael Krasnicki, Rob A. Rutenbar, L. Richard Carley, James R. Hellums: Anaconda: simulation-based synthesis of analog circuits viastochastic pattern search. IEEE Trans. on CAD of Integrated Circuits and Systems 19(6): 703-717 (2000)
42EETamal Mukherjee, L. Richard Carley, Rob A. Rutenbar: Efficient handling of operating range and manufacturing linevariations in analog cell synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 19(8): 825-839 (2000)
1999
41EEMichael Krasnicki, Rodney Phelps, Rob A. Rutenbar, L. Richard Carley: MAELSTROM: Efficient Simulation-Based Synthesis for Custom Analog Cells. DAC 1999: 945-950
40EEGi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar: Satisfiability-Based Layout Revisited: Detailed Routing of Complex FPGAs vis Search-Based Boolean SAT. FPGA 1999: 167-175
39EEPascal C. H. Meier, Rob A. Rutenbar, L. Richard Carley: Inverse polarity techniques for high-speed/low-power multipliers. ISLPED 1999: 264-266
38EEGi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar: Satisfiability-Based Detailed FPGA Routing. VLSI Design 1999: 574-577
37EEMehmet Aktuna, Rob A. Rutenbar, L. Richard Carley: Device-level early floorplanning algorithms for RF circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 18(4): 375-388 (1999)
1998
36EEMehmet Aktuna, Rob A. Rutenbar, L. Richard Carley: Device-level early floorplanning algorithms for RF circuits. ISPD 1998: 57-64
35EER. Glenn Wood, Rob A. Rutenbar: FPGA routing and routability estimation via Boolean satisfiability. IEEE Trans. VLSI Syst. 6(2): 222-231 (1998)
34EESudip Nag, Rob A. Rutenbar: Performance-driven simultaneous placement and routing for FPGA's. IEEE Trans. on CAD of Integrated Circuits and Systems 17(6): 499-518 (1998)
1997
33EER. Glenn Wood, Rob A. Rutenbar: FPGA Routing and Routability Estimation via Boolean Satisfiability. FPGA 1997: 119-125
32EEGary Ellis, Lawrence T. Pileggi, Rob A. Rutenbar: A hierarchical decomposition methodology for multistage clock circuits. ICCAD 1997: 266-273
1996
31EEBulent Basaran, Rob A. Rutenbar: An O(n) Algorithm for Transistor Stacking with Performance Constraints. DAC 1996: 221-226
30EEL. Richard Carley, Georges G. E. Gielen, Rob A. Rutenbar, Willy M. C. Sansen: Synthesis Tools for Mixed-Signal ICs: Progress on Frontend and Backend Strategies. DAC 1996: 298-303
29EEEmil S. Ochotta, Rob A. Rutenbar, L. Richard Carley: Synthesis of high-performance analog circuits in ASTRX/OBLX. IEEE Trans. on CAD of Integrated Circuits and Systems 15(3): 273-294 (1996)
1995
28EESudip K. Nag, Rob A. Rutenbar: Performance-driven simultaneous place and route for island-style FPGAs. ICCAD 1995: 332-338
27EEJitendra Khare, Sujoy Mitra, Pranab K. Nag, U. Maly, Rob A. Rutenbar: Testability-oriented channel routing. VLSI Design 1995: 208-213
26EEPrabir C. Maulik, L. Richard Carley, Rob A. Rutenbar: Integer programming based topology selection of cell-level analog circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 14(4): 401-412 (1995)
1994
25EEEmil S. Ochotta, Rob A. Rutenbar, L. Richard Carley: ASTRX/OBLX: Tools for Rapid Synthesis of High-Performance Analog Circuits. DAC 1994: 24-30
24EESudip Nag, Rob A. Rutenbar: Performance-Driven Simultaneous Place and Route for Row-Based FPGAs. DAC 1994: 301-307
23EETamal Mukherjee, L. Richard Carley, Rob A. Rutenbar: Synthesis of manufacturable analog circuits. ICCAD 1994: 586-593
1993
22EEBulent Basaran, Rob A. Rutenbar, L. Richard Carley: Latchup-aware placement and parasitic-bounded routing of custom analog cells. ICCAD 1993: 415-421
1992
21EEPrabir C. Maulik, L. Richard Carley, Rob A. Rutenbar: A Mixed-Integer Nonlinear Programming Approach to Analog Circuit Synthesis. DAC 1992: 698-703
20EESujoy Mitra, Sudip Nag, Rob A. Rutenbar, L. Richard Carley: System-level routing of mixed-signal ASICs in WREN. ICCAD 1992: 394-399
19EEDorothy E. Setliff, Rob A. Rutenbar: Knowledge Representation and Reasoning in a Software Synthesis Architecture. IEEE Trans. Software Eng. 18(6): 523-533 (1992)
1991
18 Rajeev Jayaraman, Rob A. Rutenbar: A Parallel Steiner Heuristic for Wirelength Estimation of Large Net Populations. ICCAD 1991: 344-347
17 John M. Cohn, David J. Garrod, Rob A. Rutenbar, L. Richard Carley: Techniques for Simultaneous Placement and Routing of Custom Analog Cells in KOAN/ANAGRAM II. ICCAD 1991: 394-397
16EEDorothy E. Setliff, Rob A. Rutenbar: On the feasibility of synthesizing CAD software from specifications: generating maze router tools in ELF. IEEE Trans. on CAD of Integrated Circuits and Systems 10(6): 783-801 (1991)
15EESaul A. Kravitz, Randal E. Bryant, Rob A. Rutenbar: Massively parallel switch-level simulation: a feasibility study. IEEE Trans. on CAD of Integrated Circuits and Systems 10(7): 871-894 (1991)
1990
14EEErik C. Carlson, Rob A. Rutenbar: Design and Performance Evaluation of New Massively Parallel VLSI Mask Verification Algorithms in JIGSAW. DAC 1990: 253-259
1989
13EEDorothy E. Setliff, Rob A. Rutenbar: ELF: A Tool for Automatic Synthesis of Custom Physical CAD Software. DAC 1989: 543-548
12EESaul A. Kravitz, Randal E. Bryant, Rob A. Rutenbar: Massively Parallel Switch-Level Simulation: A Feasibility Study. DAC 1989: 91-97
11 Rob A. Rutenbar: Zen and the Art of Analog Design Automation. IFIP Congress 1989: 911
10EESaul A. Kravitz, Randal E. Bryant, Rob A. Rutenbar: Logic Simulation on Massively Parallel Architectures. ISCA 1989: 336-343
9EERamesh Harjani, Rob A. Rutenbar, L. Richard Carley: OASYS: a framework for analog circuit synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 8(12): 1247-1266 (1989)
1988
8EEErik C. Carlson, Rob A. Rutenbar: Mask Verification on the Connection Machine. DAC 1988: 134-140
7EERob A. Rutenbar, Daniel E. Atkins: Systolic routing hardware: performance evaluation and optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 7(3): 397-410 (1988)
1987
6EERamesh Harjani, Rob A. Rutenbar, L. Richard Carley: A Prototype Framework for Knowledge-Based Analog Circuit Synthesis. DAC 1987: 42-49
5EESaul A. Kravitz, Rob A. Rutenbar: Placement by Simulated Annealing on a Multiprocessor. IEEE Trans. on CAD of Integrated Circuits and Systems 6(4): 534-549 (1987)
4EEErik C. Carlson, Rob A. Rutenbar: A Scanline Data Structure Processor for VLSI Geometry Checking. IEEE Trans. on CAD of Integrated Circuits and Systems 6(5): 780-794 (1987)
1986
3EESaul A. Kravitz, Rob A. Rutenbar: Multiprocessor-based placement by simulated annealing. DAC 1986: 567-573
1985
2EERob A. Rutenbar: Future directions for DA machine research (panel session). DAC 1985: 496-497
1984
1EERob A. Rutenbar, Trevor N. Mudge, Daniel E. Atkins: A Class of Cellular Architectures to Support Physical Design Automation. IEEE Trans. on CAD of Integrated Circuits and Systems 3(4): 264-278 (1984)

Coauthor Index

1Mehmet Aktuna [36] [37]
2Christoph Albrecht [76]
3Luis Aldaz [48]
4Fadi A. Aloul [52] [69]
5Daniel E. Atkins [1] [7]
6Max Baron [60]
7Bulent Basaran [22] [31]
8Anthony R. Bonaccio [73]
9Duane S. Boning [78]
10Anjan Bose [101]
11Randal E. Bryant [10] [12] [15]
12Benton H. Calhoun [98]
13L. Richard Carley [6] [9] [17] [20] [21] [22] [23] [25] [26] [29] [30] [36] [37] [39] [41] [42] [43] [50] [53] [57] [64] [75]
14Erik C. Carlson [4] [8] [14] [103]
15Henry Chang [49]
16Dong Chen [79] [90]
17Jinsong Chen [103]
18Tsuhan Chen [66] [67] [93]
19Kwang-Ting Cheng (Kwang-Ting (Tim) Cheng) [70]
20Yu-Tsun Chien [79] [90]
21Philip Chong [76]
22Stephen Y. Chow [47]
23John M. Cohn [17] [45] [48]
24David E. Corman [101]
25Olivier Coudert [55]
26Thomas Daniel [60]
27E. Aykut Dengi [75]
28Nicola Dragone [53]
29Gary Ellis [32]
30Claire Fang Fang [66] [67] [78] [88] [97]
31Suzanne M. Fowler [74]
32Goran Frehse [83] [86]
33David J. Garrod [17]
34Georges G. E. Gielen [30] [49] [54]
35Prakash Gopalakrishnan [56]
36Patrick Groeneveld [55] [103]
37Smriti Gupta [72]
38David L. Harame [68]
39Ramesh Harjani [6] [9]
40James R. Hellums [43] [50] [57]
41Mark Horowitz [47]
42Cheming Hu [47]
43Rajeev Jayaraman [18] [60]
44Kurt Johnson [68]
45Rony Kay [46] [51]
46Paul Kempf [68]
47Jitendra Khare [27]
48Rudolf Koch [49]
49Jürgen Koehl [55]
50Michael Krasnicki [41] [43] [50] [57]
51Saul A. Kravitz [3] [5] [10] [12] [15]
52Bruce H. Krogh [72] [83] [86]
53Andreas Kuehlmann [76] [101]
54Sandip Kundu [70]
55Domine Leenaerts [54]
56Edward C. Lin [93] [102]
57Hongzhou Liu [64]
58Jea-Hong Lou [79] [90]
59Gin-Kou Ma [79] [90]
60James D. Ma [71] [78] [82] [88] [89] [97]
61James D. Z. Ma [74] [77]
62Chris Malachowsky [48]
63Oded Maler [83]
64U. Maly [27]
65Robert M. Manning [101]
66Igor L. Markov [76]
67Prabir C. Maulik [21] [26]
68Mark McClung [57]
69Roy McGuffin [49]
70Pascal C. H. Meier [39]
71Teresa H. Y. Meng [68] [73]
72Sujoy Mitra [20] [27]
73Trevor N. Mudge [1]
74Tamal Mukherjee [23] [42] [79] [90]
75K. C. Murphy [49]
76Pranab K. Nag [27]
77Sudip Nag [20] [24] [34]
78Sudip K. Nag [28]
79David Nagle [44]
80Gi-Joon Nam [38] [40] [52] [59] [61] [63] [69]
81Anna Newman [101]
82Emil S. Ochotta [25] [29]
83Stephan Ohr [49]
84Zvi Or-Bach [60]
85David A. Papa [76]
86Ernesto Perea [73]
87Scott Peterson [55]
88Rodney Phelps [41] [43] [50] [57]
89Lawrence T. Pileggi (Larry T. Pileggi, Lawrence T. Pillage) [32]
90Jed W. Pitera [103]
91Robert Pitts [73]
92Markus Püschel [67]
93Vivek Raghavan [55]
94Reza Rofougaran [68]
95Ronald A. Rohrer [75]
96Jonathan Rose [60]
97Karem A. Sakallah [38] [40] [52] [59] [61] [62] [63] [65] [69]
98Willy M. C. Sansen [30]
99Carl Sechen [60]
100Dorothy E. Setliff [13] [16] [19]
101Sonia Singhal [99] [100]
102Amith Singhee [64] [88] [91] [94] [95] [97] [98] [99] [100]
103Charles Sodini [73]
104Naresh Soni [55]
105James Spoto [68]
106Pragati K. Tiwary [87]
107Saurabh K. Tiwary [81] [84] [87]
108J. Y. F. Tong [44]
109Jiajing Wang [98]
110Li-C. Wang [70]
111Jim Wieser [73]
112R. Glenn Wood [33] [35]
113Xiaolin Xie [78]
114Zhong Xiu [74] [76] [80] [92]
115Hui Xu [62] [65]
116Steve Young [48]
117Kai Yu [93]
118Roberto Zafalon [53]
119Gang Zhang [75]

Colors in the list of coauthors

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)