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Kaushik Roy Vis

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*2009
360EEMesut Meterelliyoz, Kaushik Roy: Design for burn-in test: a technique for burn-in thermal stability under die-to-die parameter variations. ASP-DAC 2009: 787-792
359EEJing Li, Patrick Ndai, Ashish Goel, Haixin Liu, Kaushik Roy: An alternate design paradigm for robust spin-torque transfer magnetic RAM (STT MRAM) from circuit/architecture perspective. ASP-DAC 2009: 841-846
358EECharles Augustine, Behtash Behin-Aein, Xuanyao Fong, Kaushik Roy: A design methodology and device/circuit/architecture compatible simulation framework for low-power magnetic quantum cellular automata systems. ASP-DAC 2009: 847-852
357EEIk Joon Chang, Debabrata Mohapatra, Kaushik Roy: A voltage-scalable & process variation resilient hybrid SRAM architecture for MPEG-4 video processors. DAC 2009: 670-675
356EEKaushik Roy, Jaydeep P. Kulkarni, Sumeet Kumar Gupta: Device/circuit interactions at 22nm technology node. DAC 2009: 97-102
355EEUmapada Pal, Rami Kumar Roy, Kaushik Roy, Fumitaka Kimura: Indian Multi-Script Full Pin-code String Recognition for Postal Automation. ICDAR 2009: 456-460
354EEKaushik Roy, Prabir Bhattacharya: Level Set Approaches and Adaptive Asymmetrical SVMs Applied for Nonideal Iris Recognition. ICIAR 2009: 418-428
353EEKaushik Roy, Prabir Bhattacharya: Nonideal Iris Recognition Using Level Set Approach and Coalitional Game Theory. ICVS 2009: 394-402
352EEKaushik Roy, Prabir Bhattacharya: Iris Recognition in Nonideal Situations. ISC 2009: 143-150
351EEBhanu Kapoor, Shankar Hemmady, Shireesh Verma, Kaushik Roy, Manuel A. d'Abreu: Impact of SoC power management techniques on verification and testing. ISQED 2009: 692-695
350EECharles Augustine, Arijit Raychowdhury, Yunfei Gao, Mark S. Lundstrom, Kaushik Roy: PETE: A device/circuit analysis framework for evaluation and comparison of charge based emerging devices. ISQED 2009: 80-85
349EENilanjan Banerjee, Saumya Chandra, Swaroop Ghosh, Sujit Dey, Anand Raghunathan, Kaushik Roy: Coping with Variations through System-Level Design. VLSI Design 2009: 581-586
348EEJing Li, Kunhyuk Kang, Kaushik Roy: Variation Estimation and Compensation Technique in Scaled LTPS TFT Circuits for Low-Power Low-Cost Applications. IEEE Trans. on CAD of Integrated Circuits and Systems 28(1): 46-59 (2009)
347EEJung Hwan Choi, Nilanjan Banerjee, Kaushik Roy: Variation-Aware Low-Power Synthesis Methodology for Fixed-Point FIR Filters. IEEE Trans. on CAD of Integrated Circuits and Systems 28(1): 87-97 (2009)
346EEUmapada Pal, Kaushik Roy, Fumitaka Kimura: A Lexicon-Driven Handwritten City-Name Recognition Scheme for Indian Postal Automation. IEICE Transactions 92-D(5): 1146-1158 (2009)
2008
345EEKaushik Roy, Prabir Bhattacharya: Improving Features Subset Selection Using Genetic Algorithms for Iris Recognition. ANNPR 2008: 292-304
344EESwaroop Ghosh, Kaushik Roy: Exploring high-speed low-power hybrid arithmetic units at scaled supply and adaptive clock-stretching. ASP-DAC 2008: 635-640
343EEKunhyuk Kang, Saakshi Gangwal, Sang Phill Park, Kaushik Roy: NBTI induced performance degradation in logic and memory circuits: how effectively can we approach a reliability solution? ASP-DAC 2008: 726-731
342EEJaydeep P. Kulkarni, Keejong Kim, Sang Phill Park, Kaushik Roy: Process variation tolerant SRAM array for ultra low voltage applications. DAC 2008: 108-113
341EEJing Li, Charles Augustine, Sayeef S. Salahuddin, Kaushik Roy: Modeling of failure probability and statistical design of spin-torque transfer magnetic random access memory (STT MRAM) array for yield enhancement. DAC 2008: 278-283
340EESwaroop Ghosh, Patrick Ndai, Kaushik Roy: A Novel Low Overhead Fault Tolerant Kogge-Stone Adder Using Adaptive Clocking. DATE 2008: 366-371
339EEDimitris Gizopoulos, Kaushik Roy, Patrick Girard, Nicola Nicolici, Xiaoqing Wen: Power-Aware Testing and Test Strategies for Low Power Devices. DATE 2008
338EEDimitris Gizopoulos, Kaushik Roy, Subhasish Mitra, Pia Sanda: Soft Errors: System Effects, Protection Techniques and Case Studies. DATE 2008
337EENilanjan Banerjee, Charles Augustine, Kaushik Roy: Fault-Tolerance with Graceful Degradation in Quality: A Design Methodology and Its Application to Digital Signal Processing Systems. DFT 2008: 323-331
336EEKaushik Roy, Prabir Bhattacharya: Optimal Features Subset Selection Using Genetic Algorithms for Iris Recognition. ICIAR 2008: 894-904
335EEKaushik Roy, Prabir Bhattacharya: Adaptive asymmetrical SVM and genetic algorithms based iris recognition. ICPR 2008: 1-4
334EEKaushik Roy, Kinshuk Majumder: Trilingual Script Separation of Handwritten Postal Document. ICVGIP 2008: 693-700
333EEMesut Meterelliyoz, Jaydeep P. Kulkarni, Kaushik Roy: Thermal analysis of 8-T SRAM for nano-scaled technologies. ISLPED 2008: 123-128
332EESwarup Bhunia, Kaushik Roy: Low power design under parameter variations. ISLPED 2008: 137-138
331EESwaroop Ghosh, Jung Hwan Choi, Patrick Ndai, Kaushik Roy: O2C: occasional two-cycle operations for dynamic thermal management in high performance in-order microprocessors. ISLPED 2008: 189-192
330EESwarup Bhunia, Kaushik Roy: Low power design under parameter variations. SoCC 2008: 389-390
329EEAditya Bansal, Jae-Joon Kim, Keunwoo Kim, Saibal Mukhopadhyay, Ching-Te Chuang, Kaushik Roy: Optimal Dual-VT Design in Sub-100 Nanometer PDSOI and Double-Gate Technologies. VLSI Design 2008: 125-130
328EENiladri Narayan Mojumder, Saibal Mukhopadhyay, Jae-Joon Kim, Ching-Te Chuang, Kaushik Roy: Design and Analysis of a Self-Repairing SRAM with On-Chip Monitor and Compensation Circuitry. VTS 2008: 101-106
327EEPatrick Ndai, Swarup Bhunia, Amit Agarwal, Kaushik Roy: Within-Die Variation-Aware Scheduling in Superscalar Processors for Improved Throughput. IEEE Trans. Computers 57(7): 940-951 (2008)
326EEAnimesh Datta, Swarup Bhunia, Jung Hwan Choi, Saibal Mukhopadhyay, Kaushik Roy: Profit Aware Circuit Design Under Process Variations Considering Speed Binning. IEEE Trans. VLSI Syst. 16(7): 806-815 (2008)
325EESaibal Mukhopadhyay, Hamid Mahmoodi, Kaushik Roy: Reduction of Parametric Failures in Sub-100-nm SRAM Array Using Body Bias. IEEE Trans. on CAD of Integrated Circuits and Systems 27(1): 174-183 (2008)
324EESwarup Bhunia, Hamid Mahmoodi, Arijit Raychowdhury, Kaushik Roy: Arbitrary Two-Pattern Delay Testing Using a Low-Overhead Supply Gating Technique. J. Electronic Testing 24(6): 577-590 (2008)
323EEJing Li, Aditya Bansal, Swaroop Ghosh, Kaushik Roy: An alternate design paradigm for low-power, low-cost, testable hybrid systems using scaled LTPS TFTs. JETC 4(3): (2008)
322EEJongsun Park, Kaushik Roy: A Low Complexity Reconfigurable DCT Architecture to Trade off Image Quality for Power Consumption. Signal Processing Systems 53(3): 399-410 (2008)
2007
321EEJing Li, Kunhyuk Kang, Aditya Bansal, Kaushik Roy: High Performance and Low Power Electronics on Flexible Substrate. DAC 2007: 274-275
320EEKunhyuk Kang, Kee-Jong Kim, Ahmad E. Islam, Muhammad Ashraful Alam, Kaushik Roy: Characterization and Estimation of Circuit Reliability Degradation under NBTI using On-Line IDDQ Measurement. DAC 2007: 358-363
319EEKunhyuk Kang, Kee-Jong Kim, Kaushik Roy: Variation Resilient Low-Power Circuit Design Methodology using On-Chip Phase Locked Loop. DAC 2007: 934-939
318EESwaroop Ghosh, Swarup Bhunia, Kaushik Roy: Low-overhead circuit synthesis for temperature adaptation using dynamic voltage scheduling. DATE 2007: 1532-1537
317EEMyeong-Eun Hwang, Tamer Cakici, Kaushik Roy: Interactive presentation: Process tolerant beta-ratio modulation for ultra-dynamic voltage scaling. DATE 2007: 1550-1555
316EENilanjan Banerjee, Georgios Karakonstantis, Kaushik Roy: Process variation tolerant low power DCT architecture. DATE 2007: 630-635
315 Saibal Mukhopadhyay, Qikai Chen, Kaushik Roy: Memories in Scaled Technologies: A Review of Process Induced Failures, Test Methodologies, and Fault Tolerance. DDECS 2007: 69-74
314EEKaushik Roy, Claire Tomlin: A New Hybrid State Estimator for Systems with Limited Mode Changes. HSCC 2007: 487-500
313EEGeorgios Karakonstantis, Nilanjan Banerjee, Kaushik Roy, Chaitali Chakrabarti: Design methodology to trade off power, output quality and error resiliency: application to color interpolation filtering. ICCAD 2007: 199-204
312EEKunhyuk Kang, Sang Phill Park, Kaushik Roy, Muhammad Ashraful Alam: Estimation of statistical variation in temporal NBTI degradation and its impact on lifetime circuit performance. ICCAD 2007: 730-734
311EEJung Hwan Choi, Jayathi Murthy, Kaushik Roy: The effect of process variation on device temperature in FinFET circuits. ICCAD 2007: 747-751
310EEKaushik Roy, Prabir Bhattacharya: Collarette Area Localization and Asymmetrical Support Vector Machines for Efficient Iris Recognition. ICIAP 2007: 3-8
309EEKaushik Roy, Prabir Bhattacharya: Iris Recognition Based on Zigzag Collarette Region and Asymmetrical Support Vector Machines. ICIAR 2007: 854-865
308EESwaroop Ghosh, Patrick Ndai, Swarup Bhunia, Kaushik Roy: Tolerance to Small Delay Defects by Adaptive Clock Stretching. IOLTS 2007: 244-252
307EENilanjan Banerjee, Jung Hwan Choi, Kaushik Roy: A process variation aware low power synthesis methodology for fixed-point FIR filters. ISLPED 2007: 147-152
306EEJaydeep P. Kulkarni, Keejong Kim, Kaushik Roy: A 160 mV, fully differential, robust schmitt trigger based sub-threshold SRAM. ISLPED 2007: 171-176
305EEKeejong Kim, Hamid Mahmoodi, Kaushik Roy: A low-power SRAM using bit-line charge-recycling technique. ISLPED 2007: 177-182
304EEMyeong-Eun Hwang, Seong-Ook Jung, Kaushik Roy: Slope interconnect effort: gate-interconnect interdependentdelay model for CMOS logic gates. ISLPED 2007: 387-390
303EEDebabrata Mohapatra, Georgios Karakonstantis, Kaushik Roy: Low-power process-variation tolerant arithmetic units using input-based elastic clocking. ISLPED 2007: 74-79
302EETamer Cakici, Kee-Jong Kim, Kaushik Roy: FinFET Based SRAM Design for Low Standby Power Applications. ISQED 2007: 127-132
301EEPatrick Ndai, Shih-Lien Lu, Dinesh Somasekhar, Kaushik Roy: Fine-Grained Redundancy in Adders. ISQED 2007: 317-321
300EEJaydeep P. Kulkarni, Kaushik Roy: A High Performance, Scalable Multiplexed Keeper Technique. ISQED 2007: 545-549
299EEKaushik Roy, Prabir Bhattacharya: Application of Multi-objective Genetic Algorithm and asymmetrical Support Vector Machine to improve the reliability of an iris recognition system. SMC 2007: 1952-1957
298EEQikai Chen, Arjun Guha, Kaushik Roy: An Accurate Analytical SNM Modeling Technique for SRAMs Based on Butterworth Filter Function. VLSI Design 2007: 615-620
297EESwarup Bhunia, Saibal Mukhopadhyay, Kaushik Roy: Process Variations and Process-Tolerant Design. VLSI Design 2007: 699-704
296EESwaroop Ghosh, Swarup Bhunia, Kaushik Roy: Low-Power and testable circuit synthesis using Shannon decomposition. ACM Trans. Design Autom. Electr. Syst. 12(4): (2007)
295EEAnimesh Datta, Swarup Bhunia, Saibal Mukhopadhyay, Nilanjan Banerjee, Kaushik Roy: Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies CoRR abs/0710.4663: (2007)
294EESaibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy: Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits CoRR abs/0710.4729: (2007)
293EEAmit Agarwal, Kunhyuk Kang, Swarup Bhunia, James D. Gallagher, Kaushik Roy: Device-Aware Yield-Centric Dual-Vt Design Under Parameter Variations in Nanoscale Technologies. IEEE Trans. VLSI Syst. 15(6): 660-671 (2007)
292EEKunhyuk Kang, Haldun Kufluoglu, Kaushik Roy, Muhammad Ashraful Alam: Impact of Negative-Bias Temperature Instability in Nanoscale SRAM Array: Modeling and Analysis. IEEE Trans. on CAD of Integrated Circuits and Systems 26(10): 1770-1781 (2007)
291EESwaroop Ghosh, Swarup Bhunia, Kaushik Roy: CRISTA: A New Paradigm for Low-Power, Variation-Tolerant, and Adaptive Circuit Synthesis Using Critical Path Isolation. IEEE Trans. on CAD of Integrated Circuits and Systems 26(11): 1947-1956 (2007)
290EEAnimesh Datta, Ashish Goel, R. T. Cakici, Hamid Mahmoodi, D. Lekshmanan, Kaushik Roy: Modeling and Circuit Synthesis for Independently Controlled Double Gate FinFET Devices. IEEE Trans. on CAD of Integrated Circuits and Systems 26(11): 1957-1966 (2007)
289EEJung Hwan Choi, Aditya Bansal, Mesut Meterelliyoz, Jayathi Murthy, Kaushik Roy: Self-Consistent Approach to Leakage Power and Temperature Estimation to Predict Thermal Runaway in FinFET Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 26(11): 2059-2068 (2007)
288EEBipul Chandra Paul, Kunhyuk Kang, Haldun Kufluoglu, Muhammad Ashraful Alam, Kaushik Roy: Negative Bias Temperature Instability: Estimation and Design for Improved Reliability of Nanoscale Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 26(4): 743-751 (2007)
287EEYongtao Wang, Khurram Muhammad, Kaushik Roy: Design of Sigma-Delta Modulators With Arbitrary Transfer Functions. IEEE Transactions on Signal Processing 55(2): 677-683 (2007)
286EEHiroaki Suzuki, Woopyo Jeong, Kaushik Roy: Adaptive Supply Voltage for Low-Power Ripple-Carry and Carry-Select Adders. IEICE Transactions 90-C(4): 865-876 (2007)
285EESaibal Mukhopadhyay, Keunwoo Kim, Jae-Joon Kim, Shih-Hsien Lo, Rajiv V. Joshi, Ching-Te Chuang, Kaushik Roy: Estimation of gate-to-channel tunneling current in ultra-thin oxide sub-50nm double gate devices. Microelectronics Journal 38(8-9): 931-941 (2007)
2006
284EEHai Li, Yiran Chen, Kaushik Roy, Cheng-Kok Koh: SAVS: a self-adaptive variable supply-voltage technique for process- tolerant and power-efficient multi-issue superscalar processor design. ASP-DAC 2006: 158-163
283EEAditya Bansal, Mesut Meterelliyoz, Siddharth Singh, Jung Hwan Choi, Jayathi Murthy, Kaushik Roy: Compact thermal models for estimation of temperature-dependent power/performance in FinFET technology. ASP-DAC 2006: 237-242
282EEAshish Goel, Swarup Bhunia, Hamid Mahmoodi-Meimand, Kaushik Roy: Low-overhead design of soft-error-tolerant scan flip-flops with enhanced-scan capability. ASP-DAC 2006: 665-670
281EEAnimesh Datta, Swarup Bhunia, Jung Hwan Choi, Saibal Mukhopadhyay, Kaushik Roy: Speed binning aware design methodology to improve profit under parameter variations. ASP-DAC 2006: 712-717
280EEHari Ananthan, Kaushik Roy: A fully physical model for leakage distribution under process variations in Nanoscale double-gate CMOS. DAC 2006: 413-418
279EEMark M. Budnik, Arijit Raychowdhury, Aditya Bansal, Kaushik Roy: A high density, carbon nanotube capacitor for decoupling applications. DAC 2006: 935-938
278EESwaroop Ghosh, Saibal Mukhopadhyay, Kee-Jong Kim, Kaushik Roy: Self-calibration technique for reduction of hold failures in low-power nano-scaled SRAM. DAC 2006: 971-976
277EEMark M. Budnik, Kaushik Roy: Minimizing ohmic loss and supply voltage variation using a novel distributed power supply network. DATE 2006: 1116-1121
276EEJongsun Park, Jung Hwan Choi, Kaushik Roy: Dynamic bit-width adaptation in DCT: image quality versus computation energy trade-off. DATE 2006: 520-521
275EEBipul Chandra Paul, Kunhyuk Kang, Haldun Kufluoglu, Muhammad Ashraful Alam, Kaushik Roy: Temporal performance degradation under NBTI: estimation and design for improved reliability of nanoscale circuits. DATE 2006: 780-785
274EEArijit Raychowdhury, Bipul Chandra Paul, Swarup Bhunia, Kaushik Roy: Ultralow power computing with sub-threshold leakage: a comparative study of bulk and SOI technologies. DATE 2006: 856-861
273EENilanjan Banerjee, Kaushik Roy, Hamid Mahmoodi-Meimand, Swarup Bhunia: Low power synthesis of dynamic logic circuits using fine-grained clock gating. DATE 2006: 862-867
272EEQikai Chen, Saibal Mukhopadhyay, Aditya Bansal, Kaushik Roy: Circuit-aware device design methodology for nanometer technologies: a case study for low power SRAM design. DATE 2006: 983-988
271EEKaushik Roy, Prabir Bhattacharya: Iris Recognition with Support Vector Machines. ICB 2006: 486-492
270EEJung Hwan Choi, Aditya Bansal, Mesut Meterelliyoz, Jayathi Murthy, Kaushik Roy: Leakage power dependent temperature estimation to predict thermal runaway in FinFET circuits. ICCAD 2006: 583-586
269EESwaroop Ghosh, Swarup Bhunia, Kaushik Roy: A new paradigm for low-power, variation-tolerant circuit synthesis using critical path isolation. ICCAD 2006: 619-624
268EEKunhyuk Kang, Haldun Kufluoglu, Muhammad Ashraful Alam, Kaushik Roy: Efficient Transistor-Level Sizing Technique under Temporal Performance Degradation due to NBTI. ICCD 2006
267EESwaroop Ghosh, Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy: Delay Fault Localization in Test-Per-Scan BIST Using Built-In Delay Sensor. IOLTS 2006: 31-36
266EEIk Joon Chang, Jae-Joon Kim, Kaushik Roy: Robust level converter design for sub-threshold logic. ISLPED 2006: 14-19
265EEArijit Raychowdhury, Xuanyao Fong, Qikai Chen, Kaushik Roy: Analysis of super cut-off transistors for ultralow power digital logic circuits. ISLPED 2006: 2-7
264EEQikai Chen, Mesut Meterelliyoz, Kaushik Roy: A CMOS Thermal Sensor and Its Applications in Temperature Adaptive Design. ISQED 2006: 243-248
263EEMark M. Budnik, Kaushik Roy: Minimizing Ohmic Loss in Future Processor IR Events. ISQED 2006: 650-658
262EEKaushik Roy, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Hari Ananthan, Aditya Bansal, Tamer Cakici: Double-Gate SOI Devices for Low-Power and High-Performance Applications. VLSI Design 2006: 445-452
261EEKunhyuk Kang, Bipul C. Paul, Kaushik Roy: Statistical timing analysis using levelized covariance propagation considering systematic and random variations of process parameters. ACM Trans. Design Autom. Electr. Syst. 11(4): 848-879 (2006)
260EEKaushik Roy, T. M. Mak, Kwang-Ting (Tim) Cheng: Test Consideration for Nanometer-Scale CMOS Circuits. IEEE Design & Test of Computers 23(2): 128-136 (2006)
259EEAmit Agarwal, Saibal Mukhopadhyay, Arijit Raychowdhury, Kaushik Roy, Chris H. Kim: Leakage Power Analysis and Reduction for Nanoscale Circuits. IEEE Micro 26(2): 68-80 (2006)
258EEMark M. Budnik, Kaushik Roy: A Power Delivery and Decoupling Network Minimizing Ohmic Loss and Supply Voltage Variation in Silicon Nanoscale Technologies. IEEE Trans. VLSI Syst. 14(12): 1336-1346 (2006)
257EESaibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Kaushik Roy: A novel high-performance and robust sense amplifier using independent gate control in sub-50-nm double-gate MOSFET. IEEE Trans. VLSI Syst. 14(2): 183-192 (2006)
256EEDongku Kang, Hunsoo Choo, Khurram Muhammad, Kaushik Roy: Layout-driven architecture synthesis for high-speed digital filters. IEEE Trans. VLSI Syst. 14(2): 203-207 (2006)
255EEChris H. Kim, Kaushik Roy, Steven Hsu, Ram Krishnamurthy, Shekhar Borkar: A process variation compensating technique with an on-die leakage current sensor for nanometer scale dynamic circuits. IEEE Trans. VLSI Syst. 14(6): 646-649 (2006)
254EENilanjan Banerjee, Arijit Raychowdhury, Kaushik Roy, Swarup Bhunia, Hamid Mahmoodi: Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis. IEEE Trans. VLSI Syst. 14(9): 1034-1039 (2006)
253EEArijit Raychowdhury, Kaushik Roy: Modeling of metallic carbon-nanotube interconnects for circuit simulations and a comparison with Cu interconnects for scaled technologies. IEEE Trans. on CAD of Integrated Circuits and Systems 25(1): 58-65 (2006)
252EESaibal Mukhopadhyay, Keunwoo Kim, Ching-Te Chuang, Kaushik Roy: Modeling and Analysis of Leakage Currents in Double-Gate Technologies. IEEE Trans. on CAD of Integrated Circuits and Systems 25(10): 2052-2061 (2006)
251EEAnimesh Datta, Swarup Bhunia, Saibal Mukhopadhyay, Kaushik Roy: Delay Modeling and Statistical Design of Pipelined Circuit Under Process Variation. IEEE Trans. on CAD of Integrated Circuits and Systems 25(11): 2427-2436 (2006)
250EEAditya Bansal, Bipul Chandra Paul, Kaushik Roy: An Analytical Fringe Capacitance Model for Interconnects Using Conformal Mapping. IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 2765-2774 (2006)
249EESwaroop Ghosh, Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy: A Novel Delay Fault Testing Methodology Using Low-Overhead Built-In Delay Sensor. IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 2934-2943 (2006)
248EEJongsun Park, Khurram Muhammad, Kaushik Roy: Efficient modeling of 1/falpha/ noise using multirate process. IEEE Trans. on CAD of Integrated Circuits and Systems 25(7): 1247-1256 (2006)
247EESaibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy: Modeling and analysis of loading effect on leakage of nanoscaled bulk-CMOS logic circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 25(8): 1486-1495 (2006)
246EEKaushik Roy: Guest Editorial. Integration 39(2): 63 (2006)
245EEBipul Chandra Paul, Amit Agarwal, Kaushik Roy: Low-power design techniques for scaled technologies. Integration 39(2): 64-89 (2006)
244EEBipul C. Paul, Kaushik Roy: Impact of Body Bias on Delay Fault Testing of Sub-100 nm CMOS Circuits. J. Electronic Testing 22(2): 115-124 (2006)
2005
243 Kaushik Roy, Vivek Tiwari: Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005, San Diego, California, USA, August 8-10, 2005 ACM 2005
242EEMatthew Cooke, Hamid Mahmoodi-Meimand, Qikai Chen, Kaushik Roy: Energy recovery clocked dynamic logic. ACM Great Lakes Symposium on VLSI 2005: 468-471
241EEAnimesh Datta, Swarup Bhunia, Saibal Mukhopadhyay, Kaushik Roy: A Statistical Approach to Area-Constrained Yield Enhancement for Pipelined Circuits under Parameter Variations. Asian Test Symposium 2005: 170-175
240EESaibal Mukhopadhyay, Arijit Raychowdhury, Hamid Mahmoodi-Meimand, Kaushik Roy: Leakage Current Based Stabilization Scheme for Robust Sense-Amplifier Design for Yield Enhancement in Nano-scale SRAM. Asian Test Symposium 2005: 176-181
239EESwaroop Ghosh, Swarup Bhunia, Kaushik Roy: Shannon Expansion Based Supply-Gated Logic for Improved Power and Testability. Asian Test Symposium 2005: 404-409
238EESwarup Bhunia, Nilanjan Banerjee, Qikai Chen, Hamid Mahmoodi-Meimand, Kaushik Roy: A novel synthesis approach for active leakage power reduction using dynamic supply gating. DAC 2005: 479-484
237EESwarup Bhunia, Hamid Mahmoodi-Meimand, Arijit Raychowdhury, Kaushik Roy: A Novel Low-overhead Delay Testing Technique for Arbitrary Two-Pattern Test Application. DATE 2005: 1136-1141
236EESaibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy: Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits. DATE 2005: 224-229
235EEKunhyuk Kang, Bipul Chandra Paul, Kaushik Roy: Statistical Timing Analysis using Levelized Covariance Propagation. DATE 2005: 764-769
234EEAnimesh Datta, Swarup Bhunia, Saibal Mukhopadhyay, Nilanjan Banerjee, Kaushik Roy: Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies. DATE 2005: 926-931
233 Kaushik Roy, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Hari Ananthan, Aditya Bansal, Tamer Cakici: Double-gate SOI devices for low-power and high-performance applications. ICCAD 2005: 217-224
232 Amit Agarwal, Kunhyuk Kang, Kaushik Roy: Accurate estimation and modeling of total chip leakage considering inter- & intra-die process variations. ICCAD 2005: 736-741
231EEPatrick Ndai, Amit Agarwal, Qikai Chen, Kaushik Roy: A Soft Error Monitor Using Switching Current Detection. ICCD 2005: 185-192
230EENilanjan Banerjee, Arijit Raychowdhury, Swarup Bhunia, Hamid Mahmoodi-Meimand, Kaushik Roy: Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis. ICCD 2005: 206-214
229EEArijit Raychowdhury, Saibal Mukhopadhyay, Kaushik Roy: A Feasibility Study of Subthreshold SRAM Across Technology Generations. ICCD 2005: 417-424
228EEChris H. Kim, Steven Hsu, Ram Krishnamurthy, Shekhar Borkar, Kaushik Roy: Self Calibrating Circuit Design for Variation Tolerant VLSI Systems. IOLTS 2005: 100-105
227EEQikai Chen, Saibal Mukhopadhyay, Hamid Mahmoodi, Kaushik Roy: Process Variation Tolerant Online Current Monitor for Robust Systems. IOLTS 2005: 171-176
226EEAnimesh Datta, Saibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy: Yield Prediction of High Performance Pipelined Circuit with Respect to Delay Failures in Sub-100nm Technology. IOLTS 2005: 275-280
225EEArijit Raychowdhury, Swaroop Ghosh, Kaushik Roy: A Novel On-Chip Delay Measurement Hardware for Efficient Speed-Binning. IOLTS 2005: 287-292
224EEAditya Bansal, Kaushik Roy: Asymmetric halo CMOSFET to reduce static power dissipation with improved performance. ISCAS (1) 2005: 1-4
223EEYongtao Wang, Kaushik Roy: A novel low-complexity method for parallel multiplierless implementation of digital FIR filters. ISCAS (3) 2005: 2020-2023
222EEYongtao Wang, Kaushik Roy: A new reduced-complexity sphere decoder with true lattice-boundary-awareness for multi-antenna systems. ISCAS (5) 2005: 4963-4966
221EESteven Hsu, Amit Agarwal, Kaushik Roy, Ram Krishnamurthy, Shekhar Y. Borkar: An 8.3GHz dual supply/threshold optimized 32b integer ALU-register file loop in 90nm CMOS. ISLPED 2005: 103-106
220EEYiran Chen, Hai Li, Kaushik Roy, Cheng-Kok Koh: Cascaded carry-select adder (C2SA): a new structure for low-power CSA design. ISLPED 2005: 115-118
219EEAmit Agarwal, Kunhyuk Kang, Swarup Bhunia, James D. Gallagher, Kaushik Roy: Effectiveness of low power dual-Vt designs in nano-scale technologies under process parameter variations. ISLPED 2005: 14-19
218EESaibal Mukhopadhyay, Keunwoo Kim, Ching-Te Chuang, Kaushik Roy: Modeling and analysis of total leakage currents in nanoscale double gate devices and circuits. ISLPED 2005: 8-13
217EEAnimesh Datta, Swarup Bhunia, Nilanjan Banerjee, Kaushik Roy: A Power-Aware GALS Architecture for Real-Time Algorithm-Specific Tasks. ISQED 2005: 358-363
216EESaibal Mukhopadhyay, Keunwoo Kim, Jae-Joon Kim, Shih-Hsien Lo, Rajiv V. Joshi, Ching-Te Chuang, Kaushik Roy: Modeling and Analysis of Gate Leakage in Ultra-thin Oxide Sub-50nm Double Gate Devices and Circuits. ISQED 2005: 410-415
215EESwarup Bhunia, Hamid Mahmoodi-Meimand, Debjyoti Ghosh, Kaushik Roy: Power Reduction in Test-Per-Scan BIST with Supply Gating and Efficient Scan Partitioning. ISQED 2005: 453-458
214EEDongku Kang, Yiran Chen, Kaushik Roy: Power Supply Noise-Aware Scheduling and Allocation for DSP Synthesis. ISQED 2005: 48-53
213EESaibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Kaushik Roy: Design of High Performance Sense Amplifier Using Independent Gate Control in sub-50nm Double-Gate MOSFET. ISQED 2005: 490-495
212EEKee-Jong Kim, Chris H. Kim, Kaushik Roy: TFT-LCD Application Specific Low Power SRAM Using Charge-Recycling Technique. ISQED 2005: 59-64
211EEQikai Chen, Hamid Mahmoodi-Meimand, Swarup Bhunia, Kaushik Roy: Modeling and Testing of SRAM for New Failure Mechanisms Due to Process Variations in Nanoscale CMOS. VTS 2005: 292-297
210EEAiqun Cao, Naran Sirisantana, Cheng-Kok Koh, Kaushik Roy: Synthesis of skewed logic circuits. ACM Trans. Design Autom. Electr. Syst. 10(2): 205-228 (2005)
209EELih-Yih Chiou, Swarup Bhunia, Kaushik Roy: Synthesis of application-specific highly efficient multi-mode cores for embedded systems. ACM Trans. Embedded Comput. Syst. 4(1): 168-188 (2005)
208EESwarup Bhunia, Animesh Datta, Nilanjan Banerjee, Kaushik Roy: GAARP: A Power-Aware GALS Architecture for Real-Time Algorithm-Specific Tasks. IEEE Trans. Computers 54(6): 752-766 (2005)
207EEAmit Agarwal, Bipul Chandra Paul, Hamid Mahmoodi-Meimand, Animesh Datta, Kaushik Roy: A process-tolerant cache architecture for improved yield in nanoscale technologies. IEEE Trans. VLSI Syst. 13(1): 27-38 (2005)
206EEYiran Chen, Kaushik Roy, Cheng-Kok Koh: Current demand balancing: a technique for minimization of current surge in high performance clock-gated microprocessors. IEEE Trans. VLSI Syst. 13(1): 75-85 (2005)
205EEArijit Raychowdhury, Bipul Chandra Paul, Swarup Bhunia, Kaushik Roy: Computing with subthreshold leakage: device/circuit/architecture co-design for ultralow-power subthreshold operation. IEEE Trans. VLSI Syst. 13(11): 1213-1224 (2005)
204EEQikai Chen, Hamid Mahmoodi-Meimand, Swarup Bhunia, Kaushik Roy: Efficient testing of SRAM with optimized march sequences and a novel DFT technique for emerging failures due to process variations. IEEE Trans. VLSI Syst. 13(11): 1286-1295 (2005)
203EEChris H. Kim, Jae-Joon Kim, Saibal Mukhopadhyay, Kaushik Roy: A forward body-biased low-leakage SRAM cache: device, circuit and architecture considerations. IEEE Trans. VLSI Syst. 13(3): 349-357 (2005)
202EESwarup Bhunia, Hamid Mahmoodi-Meimand, Debjyoti Ghosh, Saibal Mukhopadhyay, Kaushik Roy: Low-power scan design using first-level supply gating. IEEE Trans. VLSI Syst. 13(3): 384-395 (2005)
201EESwarup Bhunia, Kaushik Roy: A novel wavelet transform-based transient current analysis for fault detection and localization. IEEE Trans. VLSI Syst. 13(4): 503-507 (2005)
200EEHai Li, Chen-Yong Cher, Kaushik Roy, T. N. Vijaykumar: Combined circuit and architectural level variable supply-voltage scaling for low power. IEEE Trans. VLSI Syst. 13(5): 564-576 (2005)
199EESaibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Kaushik Roy: Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS. IEEE Trans. on CAD of Integrated Circuits and Systems 24(12): 1859-1880 (2005)
198EESaibal Mukhopadhyay, Arijit Raychowdhury, Kaushik Roy: Accurate estimation of total leakage in nanometer-scale bulk CMOS circuits based on device geometry and doping profile. IEEE Trans. on CAD of Integrated Circuits and Systems 24(3): 363-381 (2005)
197EESwarup Bhunia, Arijit Raychowdhury, Kaushik Roy: Defect Oriented Testing of Analog Circuits Using Wavelet Analysis of Dynamic Supply Current. J. Electronic Testing 21(2): 147-159 (2005)
196EESwarup Bhunia, Arijit Raychowdhury, Kaushik Roy: Frequency Specification Testing of Analog Filters Using Wavelet Transform of Dynamic Supply Current. J. Electronic Testing 21(3): 243-255 (2005)
2004
195 Rajiv V. Joshi, Kiyoung Choi, Vivek Tiwari, Kaushik Roy: Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004, Newport Beach, California, USA, August 9-11, 2004 ACM 2004
194EEWoopyo Jeong, Bipul Chandra Paul, Kaushik Roy: Adaptive supply voltage technique for low swing interconnects. ASP-DAC 2004: 284-287
193EEYiran Chen, Kaushik Roy, Cheng-Kok Koh: Priority assignment optimization for minimization of current surge in high performance power efficient clock-gated microprocessor. ASP-DAC 2004: 893-898
192 Cheng-Yi Chen, Soonkeon Kwon, Kaushik Roy: Efficient Communication Channel Utilization for Mapping FFT onto Mesh Array. Communications in Computing 2004: 167-176
191EESeung Hoon Choi, Bipul Chandra Paul, Kaushik Roy: Novel sizing algorithm for yield improvement under process variation in nanometer technology. DAC 2004: 454-459
190EEAmit Agarwal, Chris H. Kim, Saibal Mukhopadhyay, Kaushik Roy: Leakage in nano-scale technologies: mechanisms, impact and design considerations. DAC 2004: 6-11
189EESwarup Bhunia, Arijit Raychowdhury, Kaushik Roy: Trim Bit Setting of Analog Filters Using Wavelet-Based Supply Current Analysis. DATE 2004: 704-705
188EESwarup Bhunia, Hamid Mahmoodi-Meimand, Arijit Raychowdhury, Kaushik Roy: First Level Hold: A Novel Low-Overhead Delay Fault Testing Technique. DFT 2004: 314-315
187EESaibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Kaushik Roy: Statistical design and optimization of SRAM cell for yield enhancement. ICCAD 2004: 10-13
186EEArijit Raychowdhury, Kaushik Roy: A circuit model for carbon nanotube interconnects: comparative study with Cu interconnects for scaled technologies. ICCAD 2004: 237-240
185EEDongku Kang, Hunsoo Choo, Kaushik Roy: Floorplan-Aware Low-Complexity Digital Filter Synthesis for Low-Power & High-Speed. ICCD 2004: 354-357
184EESwarup Bhunia, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Debjyoti Ghosh, Kaushik Roy: A Novel Low-Power Scan Design Technique Using Supply Gating. ICCD 2004: 60-65
183EEXiaowei Ding, Kaushik Roy: A Novel Bitstream Level Joint Channel Error Concealment Scheme for Realtime Video over Wireless Networks. INFOCOM 2004
182EEAmit Agarwal, Bipul Chandra Paul, Kaushik Roy: A Novel Fault Tolerant Cache to Improve Yield in Nanometer Technologies. IOLTS 2004: 149-154
181EEDebjyoti Ghosh, Swarup Bhunia, Kaushik Roy: A Technique to Reduce Power and Test Application Time in BIST. IOLTS 2004: 182-183
180 Hamid Mahmoodi-Meimand, Kaushik Roy: Dual-edge triggered level converting flip-flops. ISCAS (2) 2004: 661-664
179 Hamid Mahmoodi-Meimand, Kaushik Roy: Data-retention flip-flops for power-down applications. ISCAS (2) 2004: 677-680
178EEMyeong-Eun Hwang, Arijit Raychowdhury, Kaushik Roy: Effectiveness of energy recovery techniques in reducing on-chip power density in molecular nano-technologies. ISCAS (3) 2004: 709-712
177EEHiroaki Suzuki, Woopyo Jeong, Kaushik Roy: Low-power carry-select adder using adaptive supply voltage based on input vector patterns. ISLPED 2004: 313-318
176EEHari Ananthan, Chris H. Kim, Kaushik Roy: Larger-than-vdd forward body bias in sub-0.5V nanoscale CMOS. ISLPED 2004: 8-13
175EEBipul Chandra Paul, Arijit Raychowdhury, Kaushik Roy: Device optimization for ultra-low power digital sub-threshold operation. ISLPED 2004: 96-101
174EEArijit Raychowdhury, Kaushik Roy: A Novel Multiple-Valued Logic Design Using Ballistic Carbon Nanotube FETs. ISMVL 2004: 14-19
173EESwarup Bhunia, Arijit Raychowdhury, Kaushik Roy: Frequency Specification Testing of Analog Filters Using Wavelet Transform of Dynamic Supply Current. ISQED 2004: 389-394
172EEHari Ananthan, Aditya Bansal, Kaushik Roy: FinFET SRAM - Device and Circuit Design Considerations. ISQED 2004: 511-516
171EEKaushik Roy: Low-Power Design. ISQED 2004: 8
170EEDongku Kang, Mark C. Johnson, Kaushik Roy: Simultaneous Multiple-Vdd Scheduling and Allocation for Partitioned Floorplan. ISQED 2004: 98-103
169EEBipul Chandra Paul, Cassondra Neau, Kaushik Roy: Impact of Body Bias on Delay Fault Testing of Nanoscale CMOS Circuits. ITC 2004: 1269-1275
168EEArijit Raychowdhury, Saibal Mukhopadhyay, Kaushik Roy: Modeling and Estimation of Leakage in Sub-90nm Devices. VLSI Design 2004: 65-
167EENaran Sirisantana, Kaushik Roy: Low-Power Design Using Multiple Channel Lengths and Oxide Thicknesses. IEEE Design & Test of Computers 21(1): 56-63 (2004)
166EENaran Sirisantana, Bipul Chandra Paul, Kaushik Roy: Enhancing Yield at the End of the Technology Roadmap. IEEE Design & Test of Computers 21(6): 563-571 (2004)
165 Hai Li, Swarup Bhunia, Yiran Chen, Kaushik Roy, T. N. Vijaykumar: DCG: deterministic clock-gating for low-power microprocessor design. IEEE Trans. VLSI Syst. 12(3): 245-254 (2004)
164EEArijit Raychowdhury, Saibal Mukhopadhyay, Kaushik Roy: A circuit-compatible model of ballistic carbon nanotube field-effect transistors. IEEE Trans. on CAD of Integrated Circuits and Systems 23(10): 1411-1420 (2004)
2003
163EESaibal Mukhopadhyay, Arijit Raychowdhury, Kaushik Roy: Accurate estimation of total leakage current in scaled CMOS logic circuits based on compact current modeling. DAC 2003: 169-174
162EEGuoan Zhong, Cheng-Kok Koh, Venkataramanan Balakrishnan, Kaushik Roy: An adaptive window-based susceptance extraction and its efficient implementation. DAC 2003: 728-731
161EELih-Yih Chiou, Swarup Bhunia, Kaushik Roy: Synthesis of Application-Specific Highly-Efficient Multi-Mode Systems for Low-Power Applications. DATE 2003: 10096-10103
160EEHunsoo Choo, Khurram Muhammad, Kaushik Roy: MRPF: An Architectural Transformation for Synthesis of High-Performance and Low-Power Digital Filters. DATE 2003: 10700-10705
159EEAmit Agarwal, Kaushik Roy, T. N. Vijaykumar: Exploring High Bandwidth Pipelined Cache Architecture for Scaled Technology. DATE 2003: 10778-10783
158EESeung Hoon Choi, Kaushik Roy: A New Crosstalk Noise Model for DOMINO Logic Circuits. DATE 2003: 11112-11113
157EENaran Sirisantana, Kaushik Roy: Selectively Clocked CMOS Logic Style for Low-Power Noise-Immune Operations in Scaled Technologies. DATE 2003: 11160-11161
156EEDebjyoti Ghosh, Swarup Bhunia, Kaushik Roy: Multiple Scan Chain Design Technique for Power Reduction during Test Application in BIST. DFT 2003: 191-198
155EEHai Li, Swarup Bhunia, Yiran Chen, T. N. Vijaykumar, Kaushik Roy: Deterministic Clock Gating for Microprocessor Power Reduction. HPCA 2003: 113-
154EEArijit Raychowdhury, Saibal Mukhopadhyay, Kaushik Roy: Modeling of Ballistic Carbon Nanotube Field Effect Transistors for Efficient Circuit Simulation. ICCAD 2003: 487-490
153EEHiroaki Suzuki, Woopyo Jeong, Kaushik Roy: Low Power Adder with Adaptive Supply Voltage. ICCD 2003: 103-106
152EEDongku Kang, Mark C. Johnson, Kaushik Roy: Multiple-Vdd Scheduling/Allocation for Partitioned Floorplan. ICCD 2003: 412-418
151EEYonghee Im, Kaushik Roy: A logic-aware layout methodology to enhance the noise immunity of domino circuits. ISCAS (5) 2003: 637-640
150EECassondra Neau, Kaushik Roy: Optimal body bias selection for leakage improvement and process compensation over different technology generations. ISLPED 2003: 116-121
149EESaibal Mukhopadhyay, Kaushik Roy: Modeling and estimation of total leakage current in nano-scaled CMOS devices considering the effect of parameter variation. ISLPED 2003: 172-175
148EEAmit Agarwal, Kaushik Roy: A noise tolerant cache design to reduce gate and sub-threshold leakage in the nanometer regime. ISLPED 2003: 18-21
147EEYiran Chen, Kaushik Roy, Cheng-Kok Koh: Integrated architectural/physical planning approach for minimization of current surge in high performance clock-gated microprocessors. ISLPED 2003: 229-234
146EEMatthew Cooke, Hamid Mahmoodi-Meimand, Kaushik Roy: Energy recovery clocking scheme and flip-flops for ultra low-energy applications. ISLPED 2003: 54-59
145EEChris H. Kim, Jae-Joon Kim, Saibal Mukhopadhyay, Kaushik Roy: A forward body-biased low-leakage SRAM cache: device and architecture considerations. ISLPED 2003: 6-9
144EEYonghee Im, Kaushik Roy: LALM: A Logic-Aware Layout Methodology to Enhance the Noise Immunity of Domino Circuits. ISVLSI 2003: 45-54
143EEHai Li, Chen-Yong Cher, T. N. Vijaykumar, Kaushik Roy: VSV: L2-Miss-Driven Variable Supply-Voltage Scaling for Low Power. MICRO 2003: 19-28
142EERajiv V. Joshi, Kaushik Roy: Design of Deep Sub-Micron CMOS Circuits. VLSI Design 2003: 15-16
141EEKaushik Roy, T. M. Mak, Kwang-Ting Cheng: Embedded Tutorial: Test Consideration for Nanometer Scale CMOS Circuits. VTS 2003: 313-318
140EEJongsun Park, Khurram Muhammad, Kaushik Roy: High-performance FIR filter design based on sharing multiplication. IEEE Trans. VLSI Syst. 11(2): 244-253 (2003)
139EESaibal Mukhopadhyay, Cassondra Neau, R. T. Cakici, Amit Agarwal, Chris H. Kim, Kaushik Roy: Gate leakage reduction for scaled devices using transistor stacking. IEEE Trans. VLSI Syst. 11(4): 716-730 (2003)
138EEAli Keshavarzi, Kaushik Roy, Charles F. Hawkins, Vivek De: Multiple-parameter CMOS IC testing with increased sensitivity for IDDQ. IEEE Trans. VLSI Syst. 11(5): 863-870 (2003)
137EEC. H.-I. Kim, Hendrawan Soeleman, Kaushik Roy: Ultra-low-power DLMS adaptive filter for hearing aid applications. IEEE Trans. VLSI Syst. 11(6): 1058-1067 (2003)
136EEGuoan Zhong, Cheng-Kok Koh, Kaushik Roy: On-chip interconnect modeling by wire duplication. IEEE Trans. on CAD of Integrated Circuits and Systems 22(11): 1521-1532 (2003)
2002
135EESwarup Bhunia, Hai Li, Kaushik Roy: A High Performance IDDQ Testable Cache for Scaled CMOS Technologies. Asian Test Symposium 2002: 157-
134EESwarup Bhunia, Kaushik Roy, Jaume Segura: A novel wavelet transform based transient current analysis for fault detection and localization. DAC 2002: 361-366
133EEAmit Agarwal, Hai Li, Kaushik Roy: DRG-cache: a data retention gated-ground cache for low power. DAC 2002: 473-478
132EESeung Hoon Choi, Kaushik Roy, Florentin Dartu: Timed pattern generation for noise-on-delay calculation. DAC 2002: 870-873
131EESwarup Bhunia, Kaushik Roy: Fault Detection and Diagnosis Using Wavelet Based Transient Current Analysis. DATE 2002: 1118
130EEChris H. Kim, Kaushik Roy: Dynamic VTH Scaling Scheme for Active Leakage Power Reduction. DATE 2002: 163-167
129EEYiran Chen, Venkataramanan Balakrishnan, Cheng-Kok Koh, Kaushik Roy: Model Reduction in the Time-Domain Using Laguerre Polynomials and Krylov Methods. DATE 2002: 931-937
128EESeung Hoon Choi, Kaushik Roy: Noise Analysis under Capacitive and Inductive Coupling for High Speed Circuits. DELTA 2002: 365-369
127EEGuoan Zhong, Cheng-Kok Koh, Kaushik Roy: On-chip interconnect modeling by wire duplication. ICCAD 2002: 341-346
126EEChris H. Kim, Kaushik Roy: Dynamic Vt SRAM: a leakage tolerant cache memory for low voltage microprocessors. ISLPED 2002: 251-254
125EEJongsun Park, Woopyo Jeong, Hunsoo Choo, Hamid Mahmoodi-Meimand, Yongtao Wang, Kaushik Roy: High performance and low power FIR filter design based on sharing multiplication. ISLPED 2002: 295-300
124EEAiqun Cao, Naran Sirisantana, Cheng-Kok Koh, Kaushik Roy: Synthesis of Selectively Clocked Skewed Logic Circuits. ISQED 2002: 229-234
123EEBipul Chandra Paul, Kaushik Roy: Testing CrossTalk Induced Delay Faults in Static CMOS Circuits Through Dynamic Timing Analysis. ITC 2002: 384-390
122EEShiyou Zhao, Kaushik Roy, Cheng-Kok Koh: Power Supply Noise Aware Floorplanning and Decoupling Capacitance Placement. VLSI Design 2002: 489-
121EESeung Hoon Choi, Bipul Chandra Paul, Kaushik Roy: Dynamic Noise Analysis with Capacitive and Inductive Coupling. VLSI Design 2002: 65-70
120EESwarup Bhunia, Kaushik Roy: Dynamic Supply Current Testing of Analog Circuits Using Wavelet Transform. VTS 2002: 302-310
119EEZhanping Chen, Liqiong Wei, Ali Keshavarzi, Kaushik Roy: IDDQ Testing for Deep-Submicron ICs: Challenges and Solutions. IEEE Design & Test of Computers 19(2): 24-33 (2002)
118EEAli Keshavarzi, James Tschanz, Siva Narendra, Vivek De, W. Robert Daasch, Kaushik Roy, Manoj Sachdev, Charles F. Hawkins: Leakage and Process Variation Effects in Current Testing on Future CMOS Circuits. IEEE Design & Test of Computers 19(5): 36-43 (2002)
117EEMark C. Johnson, Dinesh Somasekhar, Lih-Yih Chiou, Kaushik Roy: Leakage control with efficient use of transistor stacks in single threshold CMOS. IEEE Trans. VLSI Syst. 10(1): 1-5 (2002)
116EEYonghee Im, Kaushik Roy: O2ABA: a novel high-performance predictable circuit architecture for the deep submicron era. IEEE Trans. VLSI Syst. 10(3): 221-229 (2002)
115EEKhurram Muhammad, Kaushik Roy: Reduced computational redundancy implementation of DSP algorithms using computation sharing vector scaling. IEEE Trans. VLSI Syst. 10(3): 292-300 (2002)
114EELiqiong Wei, Rongtian Zhang, Kaushik Roy, Zhanping Chen, David B. Janes: Vertically integrated SOI circuits for low-power and high-performance applications. IEEE Trans. VLSI Syst. 10(3): 351-362 (2002)
113EEAlexandre Solomatnikov, Dinesh Somasekhar, Naran Sirisantana, Kaushik Roy: Skewed CMOS: noise-tolerant high-performance low-power static circuit family. IEEE Trans. VLSI Syst. 10(4): 469-476 (2002)
112EEShiyou Zhao, Kaushik Roy, Cheng-Kok Koh: Decoupling capacitance allocation and its application topower-supply noise-aware floorplanning. IEEE Trans. on CAD of Integrated Circuits and Systems 21(1): 81-92 (2002)
111EEKhurram Muhammad, Kaushik Roy: A graph theoretic approach for synthesizing very low-complexityhigh-speed digital filters. IEEE Trans. on CAD of Integrated Circuits and Systems 21(2): 204-216 (2002)
110EEKaushik Roy, Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand: Leakage Current in Deep-Submicron CMOS Circuits. Journal of Circuits, Systems, and Computers 11(6): 575-600 (2002)
2001
109 Kaushik Roy, Sung-Mo Kang, Cheng-Kok Koh: Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, West Lafayette, Indiana, USA, 2001 ACM 2001
108EEBipul Chandra Paul, Seung Hoon Choi, Yonghee Im, Kaushik Roy: Design Verification and Robust Design Technique for Cross-Talk Faults. Asian Test Symposium 2001: 449-
107EERongtian Zhang, Kaushik Roy, Cheng-Kok Koh, David B. Janes: Exploring SOI Device Structures and Interconnect Architectures for 3-Dimensional Integration. DAC 2001: 846-851
106EECassondra Neau, Khurram Muhammad, Kaushik Roy: Low complexity FIR filters using factorization of perturbed coefficients. DATE 2001: 268-272
105EESe-Hyun Yang, Michael D. Powell, Babak Falsafi, Kaushik Roy, T. N. Vijaykumar: An Integrated Circuit/Architecture Approach to Reducing Leakage in Deep-Submicron High-Performance I-Caches. HPCA 2001: 147-158
104EEYonghee Im, Kaushik Roy: CASh: A Novel "Clock as Shield" Design Methodology for Noise Immune Precharge-Evaluate Logic. ICCAD 2001: 337-
103EEXiaodong Zhang, Kaushik Roy: Power Constrained Test Scheduling with Low Power Weighted Random Testing. IOLTW 2001: 136
102EERongtian Zhang, Kaushik Roy, Cheng-Kok Koh, David B. Janes: Power trends and performance characterization of 3-dimensional integration. ISCAS (4) 2001: 414-417
101EERui Wang, Kaushik Roy, Cheng-Kok Koh: Short-circuit power analysis of an inverter driving an RLC load. ISCAS (4) 2001: 886-889
100EERongtian Zhang, Kaushik Roy, David B. Janes: Double-gate fully-depleted SOI transistors for low-power high-performance nano-scale circuit design. ISLPED 2001: 213-218
99EENaran Sirisantana, Aiqun Cao, Shawn Davidson, Cheng-Kok Koh, Kaushik Roy: Selectively clocked skewed logic (SCSL): low-power logic style for high-performance applications. ISLPED 2001: 267-270
98EEHyung-il Kim, Kaushik Roy: Ultra-low power DLMS adaptive filter for hearing aid applications. ISLPED 2001: 352-357
97EEShiyou Zhao, Kaushik Roy, Cheng-Kok Koh: Decoupling capacitance allocation for power supply noise suppression. ISPD 2001: 66-71
96EERongtian Zhang, Kaushik Roy, Cheng-Kok Koh, David B. Janes: Power Trends and Performance Characterization of 3-Dimensional Integration for Future Technology Generations. ISQED 2001: 217-222
95EEKaushik Roy, Ali Keshavarzi: Design and Test of Low Voltage CMOS Circuits. ISQED 2001: 7
94EEMichael D. Powell, Amit Agarwal, T. N. Vijaykumar, Babak Falsafi, Kaushik Roy: Reducing set-associative cache energy via way-prediction and selective direct-mapping. MICRO 2001: 54-65
93EEHendrawan Soeleman, Kaushik Roy, Bipul Chandra Paul: Sub-Domino Logic: Ultra-Low Power Dynamic Sub-Threshold Digital Logic. VLSI Design 2001: 211-214
92EEKhurram Muhammad, Kaushik Roy: Fault Detection and Location Using IDD Waveform Analysis. IEEE Design & Test of Computers 18(1): 42-49 (2001)
91EEMichael D. Powell, Se-Hyun Yang, Babak Falsafi, Kaushik Roy, T. N. Vijaykumar: Reducing leakage in a high-performance deep-submicron instruction cache. IEEE Trans. VLSI Syst. 9(1): 77-89 (2001)
90EEHendrawan Soeleman, Kaushik Roy, Bipul Chandra Paul: Robust subthreshold logic for ultra-low power operation. IEEE Trans. VLSI Syst. 9(1): 90-99 (2001)
89EEZhanping Chen, Liqiong Wei, Kaushik Roy: On effective IDDQ testing of low-voltage CMOS circuits using leakage control techniques. IEEE Trans. VLSI Syst. 9(5): 718-725 (2001)
2000
88 Majid Sarrafzadeh, Prithviraj Banerjee, Kaushik Roy: Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, Chicago, Illinois, USA, March 2-4, 2000 ACM 2000
87EEHendrawan Soeleman, Kaushik Roy: Digital CMOS logic operation in the sub-threshold region. ACM Great Lakes Symposium on VLSI 2000: 107-112
86EEKwang-Ting Cheng, Sujit Dey, Mike Rodgers, Kaushik Roy: Test challenges for deep sub-micron technologies. DAC 2000: 142-149
85EEDinesh Somasekhar, Seung Hoon Choi, Kaushik Roy, Yibin Ye, Vivek De: Dynamic noise analysis in precharge-evaluate circuits. DAC 2000: 243
84 Rongtian Zhang, Kaushik Roy, Cheng-Kok Koh, David B. Janes: Stochastic Wire-Length and Delay Distribution of 3-Dimensional Circuits. ICCAD 2000: 208-213
83 Guoan Zhong, Cheng-Kok Koh, Kaushik Roy: A Twisted Bundle Layout Structure for Minimizing Inductive Coupling Noise. ICCAD 2000: 406-411
82 Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh: Frequency Domain Analysis of Switching Noise on Power Supply Network. ICCAD 2000: 487-492
81EENaran Sirisantana, Liqiong Wei, Kaushik Roy: High-Performance Low-Power CMOS Circuits Using Multiple Channel Length and Multiple Oxide Thickness. ICCD 2000: 227-
80EEAlexandre Solomatnikov, Kaushik Roy, Cheng-Kok Koh, Dinesh Somasekhar: Skewed CMOS: Noise-Immune High-Performance Low-Power Static Circuit Family. ICCD 2000: 241-246
79EEShiyou Zhao, Kaushik Roy, Cheng-Kok Koh: Estimation of Inductive and Resistive Switching Noise on Power Supply Network in Deep Sub-Micron CMOS Circuits. ICCD 2000: 65-72
78EEXiaodong Zhang, Kaushik Roy: Power Reduction in Test-Per-Scan BIST. IOLTW 2000: 133-
77EEHendrawan Soeleman, Kaushik Roy, Bipul Chandra Paul: Robust ultra-low power sub-threshold DTMOS logic. ISLPED 2000: 25-30
76EEZhanping Chen, Liqiong Wei, Kaushik Roy: On Effective IDDQ Testing of Low Voltage CMOS Circuits Using Leakage Control Techniques. ISQED 2000: 181-188
75EEXiaodong Zhang, Kaushik Roy: Peak Power Reduction in Low Power BIST. ISQED 2000: 425-432
74 Ali Keshavarzi, Kaushik Roy, Charles F. Hawkins, Manoj Sachdev, K. Soumyanath, Vivek De: Multiple-parameter CMOS IC testing with increased sensitivity for I_DDQ. ITC 2000: 1051-1059
73 Kaushik Roy, Khurram Muhammad: Low Power VLSI Signal Processing. VLSI Design 2000: 12
72EEShiyou Zhao, Kaushik Roy: Estimation of Switching Noise on Power Supply Lines in Deep Sub-micron CMOS Circuits. VLSI Design 2000: 168-
71EELiqiong Wei, Kaushik Roy, Vivek De: Low Voltage Low Power CMOS Design Techniques for Deep Submicron ICs. VLSI Design 2000: 24-29
70EEHendrawan Soeleman, Kaushik Roy, Tan-Li Chou: Estimating Circuit Activity in Combinational CMOS Digital Circuits. IEEE Design & Test of Computers 17(2): 112-119 (2000)
69EEAli Keshavarzi, Kaushik Roy, Charles F. Hawkins: Intrinsic leakage in deep submicron CMOS ICs-measurement-based test solutions. IEEE Trans. VLSI Syst. 8(6): 717-723 (2000)
68EEZhanping Chen, Kaushik Roy, Edwin K. P. Chong: Estimation of power dissipation using a novel power macromodelingtechnique. IEEE Trans. on CAD of Integrated Circuits and Systems 19(11): 1363-1369 (2000)
67EEXiaodong Zhang, Wenlei Shan, Kaushik Roy: Low-power weighted random pattern testing. IEEE Trans. on CAD of Integrated Circuits and Systems 19(11): 1389-1398 (2000)
1999
66EEYibin Ye, Kaushik Roy, Rolf Drechsler: Power Consumption in XOR-Based Circuits. ASP-DAC 1999: 299-302
65EELiqiong Wei, Zhanping Chen, Kaushik Roy, Yibin Ye, Vivek De: Mixed-Vth (MVT) CMOS Circuit Design Methodology for Low Power Applications. DAC 1999: 430-435
64EEMark C. Johnson, Dinesh Somasekhar, Kaushik Roy: Leakage Control with Efficient Use of Transistor Stacks in Single Threshold CMOS. DAC 1999: 442-445
63EEXiaodong Zhang, Kaushik Roy: Design and Synthesis of Low Power Weighted Random Pattern Generator Considering Peak Power Reduction. DFT 1999: 148-
62EEKhurram Muhammad, Kaushik Roy: A novel design methodology for high performance and low power digital filters. ICCAD 1999: 80-83
61EEKhurram Muhammad, Dinesh Somasekhar, Kaushik Roy: Switching Characteristics of Generalized Array Multiplier Architectures and their Applications to Low Power Design. ICCD 1999: 230-235
60EEKaushik Roy, Liqiong Wei, Zhanping Chen: Multiple-Vdd multiple-Vth CMOS (MVCMOS) for low power applications. ISCAS (1) 1999: 366-370
59EEAli Keshavarzi, Siva Narendra, Shekhar Borkar, Charles F. Hawkins, Kaushik Roy, Vivek De: Technology scaling behavior of optimum reverse body bias for standby leakage power reduction in CMOS IC's. ISLPED 1999: 252-254
58EEHendrawan Soeleman, Kaushik Roy: Ultra-low power digital subthreshold logic circuits. ISLPED 1999: 94-96
57EEKhurram Muhammad, Kaushik Roy: A Graph Theoretic Approach for Design and Synthesis of Multiplierless FIR Filters. ISSS 1999: 94-99
56 Xiaodong Zhang, Kaushik Roy, Sudipta Bhawmik: POWERTEST: A Tool for Energy Conscious Weighted Random Pattern Testing. VLSI Design 1999: 416-422
55 Kaushik Roy, Anand Raghunathan, Sujit Dey: Low Power Design Methodologies for Systems-on-Chips. VLSI Design 1999: 609
54 Sudip Nag, H. K. Verma, Kaushik Roy: VLSI Signal Processing in FPGAs. VLSI Design 1999: 609
53EELiqiong Wei, Zhanping Chen, Kaushik Roy, Mark C. Johnson, Yibin Ye, Vivek De: Design and optimization of dual-threshold circuits for low-voltage low-power applications. IEEE Trans. VLSI Syst. 7(1): 16-24 (1999)
52EEMark C. Johnson, Dinesh Somasekhar, Kaushik Roy: Models and algorithms for bounds on leakage in CMOS circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 18(6): 714-725 (1999)
1998
51EELiqiong Wei, Zhanping Chen, Mark Johnson, Kaushik Roy, Vivek De: Design and Optimization of Low Voltage High Performance Dual Threshold CMOS Circuits. DAC 1998: 489-494
50EEZhanping Chen, Kaushik Roy: A Power Macromodeling Technique Based on Power Sensitivity. DAC 1998: 678-683
49EEJames R. Anderson, Siddharth Sheth, Kaushik Roy: A Coarse-Grained FPGA Architecture for High-Performance FIR Filtering. FPGA 1998: 234-244
48EEHendrawan Soeleman, Dinesh Somasekhar, Kaushik Roy: IDD Waveforms Analysis for Testing of Domino and Low Voltage Static CMOS Circuits. Great Lakes Symposium on VLSI 1998: 243-248
47EEZhanping Chen, Kaushik Roy, Edwin K. P. Chong: Estimation of power sensitivity in sequential circuits with power macromodeling application. ICCAD 1998: 468-472
46EEZhanping Chen, Mark Johnson, Liqiong Wei, Kaushik Roy: Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks. ISLPED 1998: 239-244
45EEChuan-Yu Wang, Kaushik Roy: Maximum power estimation for CMOS circuits using deterministic and statistical approaches. IEEE Trans. VLSI Syst. 6(1): 134-140 (1998)
44EEZhanping Chen, Kaushik Roy, Tan-Li Chou: Efficient statistical approach to estimate power considering uncertain properties of primary inputs. IEEE Trans. VLSI Syst. 6(3): 484-492 (1998)
43EEDinesh Somasekhar, Kaushik Roy: LVDCSL: a high fan-in, high-performance, low-voltage differential current switch logic family. IEEE Trans. VLSI Syst. 6(4): 573-577 (1998)
1997
42EEYibin Ye, Kaushik Roy: A Graph-Based Synthesis Algorithm for AND/XOR Networks. DAC 1997: 107-112
41EENaushik Sankarayya, Kaushik Roy, Debashis Bhattacharya: Optimizing computations in a transposed direct form realization of floating-point LTI-FIR systems. ICCAD 1997: 120-125
40EEZhanping Chen, Kaushik Roy, Tan-Li Chou: Power sensitivity - a new method to estimate power dissipation considering uncertain specifications of primary inputs. ICCAD 1997: 40-44
39EEChuan-Yu Wang, Kaushik Roy: COSMOS: a continuous optimization approach for maximum power estimation of CMOS circuits. ICCAD 1997: 52-55
38 Khurram Muhammad, Kaushik Roy: On Complexity Reduction of FIR Digital Filters Using Constrained Least Squares Solution. ICCD 1997: 196-201
37 Chuan-Yu Wang, Kaushik Roy: Estimation of Maximum Power for Sequential Circuits Considering Spurious Transitions. ICCD 1997: 746-751
36EEDinesh Somasekhar, Kaushik Roy: LVDCSL: low voltage differential current switch logic, a robust low power DCSL family. ISLPED 1997: 18-23
35EEYibin Ye, Kaushik Roy, Georgios I. Stamoulis: Quasi-static energy recovery logic and supply-clock generation circuits. ISLPED 1997: 96-99
34 Ali Keshavarzi, Kaushik Roy, Charles F. Hawkins: Intrinsic Leakage in Low-Power Deep Submicron CMOS ICs. ITC 1997: 146-155
33EENaushik Sankarayya, Kaushik Roy, Debashis Bhattacharya: Algorithms for Low Power FIR Filter Realization Using Differential Coefficients. VLSI Design 1997: 174-178
32EEP. Patil, Tan-Li Chou, Kaushik Roy, R. Roy: Low-Power Driven Logic Synthesis Using Accurate Power Estimation Technique. VLSI Design 1997: 179-184
31EEMark C. Johnson, Kaushik Roy: Datapath scheduling with multiple supply voltages and level converters. ACM Trans. Design Autom. Electr. Syst. 2(3): 227-248 (1997)
1996
30EEMark C. Johnson, Kaushik Roy: Optimal Selection of Supply Voltages and Level Conversions During Data Path Scheduling Under Resource Constraints. ICCD 1996: 72-77
29EEKaushik Roy, R. K. Roy: Low Power Design. VLSI Design 1996: 2
28EEChuan-Yu Wang, Kaushik Roy: Maximum power estimation for CMOS circuits using deterministic and statistic approaches. VLSI Design 1996: 364-369
27EES. C. Prasad, Kaushik Roy: Transistor reordering for power minimization under delay constraint. ACM Trans. Design Autom. Electr. Syst. 1(2): 280-300 (1996)
26EETan-Li Chou, Kaushik Roy: Accurate power estimation of CMOS sequential circuits. IEEE Trans. VLSI Syst. 4(3): 369-380 (1996)
25EETan-Li Chou, Kaushik Roy: Estimation of activity for static and domino CMOS circuits considering signal correlations and simultaneous switching. IEEE Trans. on CAD of Integrated Circuits and Systems 15(10): 1257-1265 (1996)
1995
24EETan-Li Chou, Kaushik Roy: Statistical estimation of sequential circuit activity. ICCAD 1995: 34-37
23EEChuan-Yu Wang, Kaushik Roy: Control unit synthesis targeting low-power processors. ICCD 1995: 454-
22EETan-Li Chou, Kaushik Roy: Estimation of sequential circuit activity considering spatial and temporal correlations. ICCD 1995: 577-
21 Kevin T. Kornegay, Kaushik Roy: Integrated Test Solutions and Test Economics for MCMs. ITC 1995: 193-201
20EES. C. Prasad, Kaushik Roy: Circuit optimization for minimisation of power consumption under delay constraint. VLSI Design 1995: 305-309
19 Kaushik Roy, Sudip Nag: On Routability for FPGAs under Faulty Conditions. IEEE Trans. Computers 44(11): 1296-1305 (1995)
1994
18EEKaushik Roy, Sharat Prasad: Logic synthesis for reliability—an early start to controlling electromigration and hot carrier effects. EURO-DAC 1994: 136-141
17 Kaushik Roy, Sudip Nag: On Channel Architecture and Routability for FPGAs Under Faulty Conditions. FPL 1994: 361-372
16 Kaushik Roy, Sharat Prasad: Power Dissipation Driven FPGA Place and Route Under Delay Constraints. FPL 1994: 57-65
15EETan-Li Chou, Kaushik Roy, Sharat Prasad: Estimation of circuit activity considering signal correlations and simultaneous switching. ICCAD 1994: 300-303
14 Santanu Dutta, Sudip Nag, Kaushik Roy: ASAP: A Transistor Sizing Tool for Speed Area and Power Optimization of Static CMOS Circuits. ISCAS 1994: 61-64
13 Kaushik Roy, Abhijit Chatterjee: Guest Editors' Introduction: Low-Power VLSI Design. IEEE Design & Test of Computers 11(4): 6-7 (1994)
12EEMarc E. Levitt, Kaushik Roy, Jacob A. Abraham: BiCMOS logic testing. IEEE Trans. VLSI Syst. 2(2): 241-248 (1994)
11EEKaushik Roy, Sudip Nag: Automatic synthesis of FPGA channel architecture for routability and performance. IEEE Trans. VLSI Syst. 2(4): 508-511 (1994)
1993
10EESudip Nag, Kaushik Roy: Iterative Wirability and Performance Improvement for FPGAs. DAC 1993: 321-325
9 Kaushik Roy, Sudip Nag, Santanu Dutta: Channel Architecture Optimization for Performance and Routability of Row-Based FPGAs. ICCD 1993: 220-223
8 Kaushik Roy: On Fault Modeling and Fault Tolerance of Antifuse Based FPGAs. ISCAS 1993: 1623-1626
7 Mahesh Mehendale, Kaushik Roy: Estimating Area Efficiency of Antifuse Based Channelled FPGA Architectures. VLSI Design 1993: 100-103
6EEKaushik Roy, S. C. Prasad: Circuit activity based logic synthesis for low power reliable operations. IEEE Trans. VLSI Syst. 1(4): 503-513 (1993)
5EEKaushik Roy: A bounded search algorithm for segmented channel routing for FPGA's and associated channel architecture issues. IEEE Trans. on CAD of Integrated Circuits and Systems 12(11): 1695-1705 (1993)
1992
4 Kaushik Roy, Sharat Prasad: SYCLOP: Synthesis of CMOS Logic for Low Power Applications. ICCD 1992: 464-467
1990
3EEKaushik Roy, Jacob A. Abraham: High level test generation using data flow descriptions. EURO-DAC 1990: 480-484
2 Prithviraj Banerjee, Joseph T. Rahmeh, Craig B. Stunkel, V. S. S. Nair, Kaushik Roy, Vijay Balasubramanian, Jacob A. Abraham: Algorithm-Based Fault Tolerance on a Hypercube Multiprocessor. IEEE Trans. Computers 39(9): 1132-1145 (1990)
1989
1EEKaushik Roy, Jacob A. Abraham: A Novel Approach to Accurate Timing Verification Using RTL Descriptions. DAC 1989: 638-641

Coauthor Index

1Jacob A. Abraham [1] [2] [3] [12]
2Amit Agarwal [94] [133] [139] [148] [159] [182] [190] [207] [219] [221] [231] [232] [245] [259] [293] [327]
3Muhammad Ashraful Alam [268] [275] [288] [292] [312] [320]
4Hari Ananthan [172] [176] [233] [262] [280]
5James R. Anderson [49]
6Charles Augustine [337] [341] [350] [358]
7Venkataramanan Balakrishnan [129] [162]
8Vijay Balasubramanian [2]
9Nilanjan Banerjee [208] [217] [230] [234] [238] [254] [273] [295] [307] [313] [316] [337] [347] [349]
10Prithviraj Banerjee (Prith Banerjee) [2] [88]
11Aditya Bansal [172] [224] [233] [250] [262] [270] [272] [279] [283] [289] [321] [323] [329]
12Behtash Behin-Aein [358]
13Debashis Bhattacharya [33] [41]
14Prabir Bhattacharya [271] [299] [309] [310] [335] [336] [345] [352] [353] [354]
15Sudipta Bhawmik [56]
16Swarup Bhunia [120] [131] [134] [135] [155] [156] [161] [165] [173] [181] [184] [188] [189] [196] [197] [201] [202] [204] [205] [208] [209] [211] [215] [217] [219] [226] [230] [234] [236] [237] [238] [239] [241] [247] [249] [251] [254] [267] [269] [273] [274] [281] [282] [291] [293] [294] [295] [296] [297] [308] [318] [324] [326] [327] [330] [332]
17Shekhar Y. Borkar (Shekhar Borkar) [59] [221] [228] [255]
18Mark M. Budnik [258] [263] [277] [279]
19R. T. Cakici [139] [290]
20Tamer Cakici [233] [262] [302] [317]
21Aiqun Cao [99] [124] [210]
22Chaitali Chakrabarti [313]
23Saumya Chandra [349]
24Ik Joon Chang [266] [357]
25Abhijit Chatterjee [13]
26Cheng-Yi Chen [192]
27Qikai Chen [204] [211] [227] [231] [238] [242] [264] [265] [272] [298] [315]
28Yiran Chen [129] [147] [155] [165] [193] [206] [214] [220] [284]
29Zhanping Chen [40] [44] [46] [47] [50] [51] [53] [60] [65] [68] [76] [89] [114] [119]
30Kwang-Ting Cheng (Kwang-Ting (Tim) Cheng) [86] [141] [260]
31Chen-Yong Cher [143] [200]
32Lih-Yih Chiou [117] [161] [209]
33Jung Hwan Choi [270] [276] [281] [283] [289] [307] [311] [326] [331] [347]
34Kiyoung Choi [195]
35Seung Hoon Choi [85] [108] [121] [128] [132] [158] [191]
36Edwin K. P. Chong [47] [68]
37Hunsoo Choo [125] [160] [185] [256]
38Tan-Li Chou [15] [22] [24] [25] [26] [32] [40] [44] [70]
39Ching-Te Chuang [216] [218] [252] [285] [328] [329]
40Matthew Cooke [146] [242]
41W. Robert Daasch [118]
42Florentin Dartu [132]
43Animesh Datta [207] [208] [217] [226] [234] [241] [251] [281] [290] [295] [326]
44Shawn Davidson [99]
45Vivek De [51] [53] [59] [65] [71] [74] [85] [118] [138]
46Sujit Dey [55] [86] [349]
47Xiaowei Ding [183]
48Rolf Drechsler [66]
49Santanu Dutta [9] [14]
50Babak Falsafi [91] [94] [105]
51Xuanyao Fong [265] [358]
52James D. Gallagher [219] [293]
53Saakshi Gangwal [343]
54Yunfei Gao [350]
55Debjyoti Ghosh [156] [181] [184] [202] [215]
56Swaroop Ghosh [225] [239] [249] [267] [269] [278] [291] [296] [308] [318] [323] [331] [340] [344] [349]
57Patrick Girard [339]
58Dimitris Gizopoulos [338] [339]
59Ashish Goel [282] [290] [359]
60Arjun Guha [298]
61Sumeet Kumar Gupta [356]
62Charles F. Hawkins [34] [59] [69] [74] [118] [138]
63Shankar Hemmady [351]
64Steven Hsu [221] [228] [255]
65Myeong-Eun Hwang [178] [304] [317]
66Yonghee Im [104] [108] [116] [144] [151]
67Ahmad E. Islam [320]
68David B. Janes [84] [96] [100] [102] [107] [114]
69Woopyo Jeong [125] [153] [177] [194] [286]
70Mark Johnson [46] [51]
71Mark C. Johnson [30] [31] [52] [53] [64] [117] [152] [170]
72Rajiv V. Joshi [142] [195] [216] [285]
73Seong-Ook Jung [304]
74Dongku Kang [152] [170] [185] [214] [256]
75Kunhyuk Kang [219] [232] [235] [261] [268] [275] [288] [292] [293] [312] [319] [320] [321] [343] [348]
76Sung-Mo Kang [109]
77Bhanu Kapoor [351]
78Georgios Karakonstantis [303] [313] [316]
79Ali Keshavarzi [34] [59] [69] [74] [95] [118] [119] [138]
80C. H.-I. Kim [137]
81Chris H. Kim [126] [130] [139] [145] [176] [190] [203] [212] [228] [255] [259]
82Hyung-il Kim [98]
83Jae-Joon Kim [145] [203] [216] [266] [285] [328] [329]
84Kee-Jong Kim [212] [278] [302] [319] [320]
85Keejong Kim [305] [306] [342]
86Keunwoo Kim [216] [218] [252] [285] [329]
87Fumitaka Kimura [346] [355]
88Cheng-Kok Koh [79] [80] [82] [83] [84] [96] [97] [99] [101] [102] [107] [109] [112] [122] [124] [127] [129] [136] [147] [162] [193] [206] [210] [220] [284]
89Kevin T. Kornegay [21]
90Ram Krishnamurthy [221] [228] [255]
91Haldun Kufluoglu [268] [275] [288] [292]
92Jaydeep P. Kulkarni [300] [306] [333] [342] [356]
93Soonkeon Kwon [192]
94D. Lekshmanan [290]
95Marc E. Levitt [12]
96Hai Li [133] [135] [143] [155] [165] [200] [220] [284]
97Jing Li [321] [323] [341] [348] [359]
98Haixin Liu [359]
99Shih-Hsien Lo [216] [285]
100Shih-Lien Lu [301]
101Mark S. Lundstrom [350]
102Hamid Mahmoodi (Hamid Mahmoodi-Meimand) [110] [125] [146] [179] [180] [184] [187] [188] [199] [202] [204] [207] [211] [213] [215] [227] [230] [233] [237] [238] [240] [242] [254] [257] [262] [273] [282] [290] [305] [324] [325]
103Kinshuk Majumder [334]
104T. M. Mak [141] [260]
105Mahesh Mehendale [7]
106Mesut Meterelliyoz [264] [270] [283] [289] [333] [360]
107Subhasish Mitra [338]
108Debabrata Mohapatra [303] [357]
109Niladri Narayan Mojumder [328]
110Khurram Muhammad [38] [57] [61] [62] [73] [92] [106] [111] [115] [140] [160] [248] [256] [287]
111Saibal Mukhopadhyay [110] [139] [145] [149] [154] [163] [164] [168] [184] [187] [190] [198] [199] [202] [203] [213] [216] [218] [226] [227] [229] [233] [234] [236] [240] [241] [247] [251] [252] [257] [259] [262] [272] [278] [281] [285] [294] [295] [297] [315] [325] [326] [328] [329]
112Jayathi Murthy [270] [283] [289] [311]
113Sudip Nag [9] [10] [11] [14] [17] [19] [54]
114Suku Nair (V. S. S. Nair) [2]
115Siva Narendra [59] [118]
116Patrick Ndai [231] [301] [308] [327] [331] [340] [359]
117Cassondra Neau [106] [139] [150] [169]
118Nicola Nicolici [339]
119Umapada Pal (U. Pal) [346] [355]
120Jongsun Park [125] [140] [248] [276] [322]
121Sang Phill Park [312] [342] [343]
122P. Patil [32]
123Bipul Chandra Paul (Bipul C. Paul) [77] [90] [93] [108] [121] [123] [166] [169] [175] [182] [191] [194] [205] [207] [235] [244] [245] [250] [261] [274] [275] [288]
124Michael D. Powell [91] [94] [105]
125S. C. Prasad [6] [20] [27]
126Sharat Prasad [4] [15] [16] [18]
127Anand Raghunathan [55] [349]
128Joseph T. Rahmeh [2]
129Arijit Raychowdhury [154] [163] [164] [168] [173] [174] [175] [178] [186] [188] [189] [196] [197] [198] [205] [225] [229] [230] [237] [240] [249] [253] [254] [259] [265] [267] [274] [279] [324] [350]
130Mike Rodgers [86]
131R. Roy [32]
132R. K. Roy [29]
133Rami Kumar Roy [355]
134Manoj Sachdev [74] [118]
135Sayeef S. Salahuddin [341]
136Pia Sanda [338]
137Naushik Sankarayya [33] [41]
138Majid Sarrafzadeh [88]
139Jaume Segura [134]
140Wenlei Shan [67]
141Siddharth Sheth [49]
142Siddharth Singh [283]
143Naran Sirisantana [81] [99] [113] [124] [157] [166] [167] [210]
144Hendrawan Soeleman [48] [58] [70] [77] [87] [90] [93] [137]
145Alexandre Solomatnikov [80] [113]
146Dinesh Somasekhar [36] [43] [48] [52] [61] [64] [80] [85] [113] [117] [301]
147K. Soumyanath [74]
148Georgios I. Stamoulis [35]
149Craig B. Stunkel [2]
150Hiroaki Suzuki [153] [177] [286]
151Vivek Tiwari [195] [243]
152Claire Tomlin [314]
153James Tschanz [118]
154H. K. Verma [54]
155Shireesh Verma [351]
156T. N. Vijaykumar [91] [94] [105] [143] [155] [159] [165] [200]
157Chuan-Yu Wang [23] [28] [37] [39] [45]
158Rui Wang [101]
159Yongtao Wang [125] [222] [223] [287]
160Liqiong Wei [46] [51] [53] [60] [65] [71] [76] [81] [89] [114] [119]
161Xiaoqing Wen [339]
162Se-Hyun Yang [91] [105]
163Yibin Ye [35] [42] [53] [65] [66] [85]
164Rongtian Zhang [84] [96] [100] [102] [107] [114]
165Xiaodong Zhang [56] [63] [67] [75] [78] [103]
166Shiyou Zhao [72] [79] [82] [97] [112] [122]
167Guoan Zhong [83] [127] [136] [162]
168Manuel A. d'Abreu [351]

Colors in the list of coauthors

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)