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Michel Renovell Vis

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*2009
106EEFlorence Azaïs, Yves Bertrand, Michel Renovell: An analysis of the timing behavior of CMOS digital blocks under Simultaneous Switching Noise conditions. DDECS 2009: 158-163
105EEPiet Engelke, Bernd Becker, Michel Renovell, Jürgen Schlöffel, Bettina Braitling, Ilia Polian: SUPERB: Simulator utilizing parallel evaluation of resistive bridges. ACM Trans. Design Autom. Electr. Syst. 14(4): (2009)
2008
104 Marcelo Lubaszewski, Michel Renovell, Rajesh K. Gupta: Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2008, Gramado, Brazil, September 1-4, 2008 ACM 2008
103 Bernd Straube, Milos Drutarovský, Michel Renovell, Peter Gramata, Mária Fischerová: Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), Bratislava, Slovakia, April 16-18, 2008 IEEE Computer Society 2008
102EEPiet Engelke, Ilia Polian, Michel Renovell, Sandip Kundu, Bharath Seshadri, Bernd Becker: On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing. IEEE Trans. on CAD of Integrated Circuits and Systems 27(2): 327-338 (2008)
2007
101EEPhilippe Cauvet, Serge Bernard, Michel Renovell: System-in-Package, a Combination of Challenges and Solutions. European Test Symposium 2007: 193-199
100EEVincent Kerzerho, Philippe Cauvet, Serge Bernard, Florence Azaïs, Mariane Comte, Michel Renovell: "Analogue Network of Converters": A DFT Technique to Test a Complete Set of ADCs and DACs Embedded in a Complex SiP or SOC. European Test Symposium 2007: 211-216
99EETiago R. Balen, Fernanda Lima Kastensmidt, Marcelo Lubaszewski, Michel Renovell: Single Event Upset in SRAM-based Field Programmable Analog Arrays: Effects and Mitigation. ISVLSI 2007: 192-197
98EETiago R. Balen, José Vicente Calvano, Marcelo Lubaszewski, Michel Renovell: Built-In Self-Test of Field Programmable Analog Arrays based on Transient Response Analysis. J. Electronic Testing 23(6): 497-512 (2007)
2006
97EEMariane Comte, Satoshi Ohtake, Hideo Fujiwara, Michel Renovell: Electrical Behavior of GOS Fault affected Domino Logic Cell. DELTA 2006: 183-189
96EEVincent Kerzerho, Philippe Cauvet, Serge Bernard, Florence Azaïs, Mariane Comte, Michel Renovell: "Analogue Network of Converters": A DFT Technique to Test a Complete Set of ADCs and DACs Embedded in a Complex SiP or SOC. European Test Symposium 2006: 159-164
95EETiago R. Balen, José Vicente Calvano, Marcelo Lubaszewski, Michel Renovell: Functional Test of Field Programmable Analog Arrays. VTS 2006: 326-333
94EEVincent Kerzerho, Philippe Cauvet, Serge Bernard, Florence Azaïs, Mariane Comte, Michel Renovell: A Novel DFT Technique for Testing Complete Sets of ADCs and DACs in Complex SiPs. IEEE Design & Test of Computers 23(3): 234-243 (2006)
93EEPiet Engelke, Ilia Polian, Michel Renovell, Bernd Becker: Simulating Resistive-Bridging and Stuck-At Faults. IEEE Trans. on CAD of Integrated Circuits and Systems 25(10): 2181-2192 (2006)
92EEPiet Engelke, Ilia Polian, Michel Renovell, Bernd Becker: Automatic Test Pattern Generation for Resistive Bridging Faults. J. Electronic Testing 22(1): 61-69 (2006)
91EEPatrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell: An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs. J. Electronic Testing 22(2): 161-172 (2006)
2005
90EEIlia Polian, Sandip Kundu, Jean Marc Gallière, Piet Engelke, Michel Renovell, Bernd Becker: Resistive Bridge Fault Model Evolution from Conventional to Ultra Deep Submicron Technologies. VTS 2005: 343-348
89EEGustavo Pereira, Antonio Andrade Jr., Tiago R. Balen, Marcelo Lubaszewski, Florence Azaïs, Michel Renovell: Testing the Interconnect Networks and I/O Resources of Field Programmable Analog Arrays. VTS 2005: 389-394
88EEJean Marc Gallière, Michel Renovell, Florence Azaïs, Yves Bertrand: Delay Testing Viability of Gate Oxide Short Defects. J. Comput. Sci. Technol. 20(2): 195-200 (2005)
87EEPatrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell: Delay Fault Testing of Look-Up Tables in SRAM-Based FPGAs. J. Electronic Testing 21(1): 43-55 (2005)
86EEIlia Polian, Piet Engelke, Michel Renovell, Bernd Becker: Modeling Feedback Bridging Faults with Non-Zero Resistance. J. Electronic Testing 21(1): 57-69 (2005)
85EEFlorence Azaïs, Marcelo Lubaszewski, Pascal Nouet, Michel Renovell: A Strategy for Optimal Test Point Insertion in Analog Cascaded Filters. J. Electronic Testing 21(1): 9-16 (2005)
84EETiago R. Balen, Antonio Q. Andrade, Florence Azaïs, Marcelo Lubaszewski, Michel Renovell: Applying the Oscillation Test Strategy to FPAA's Configurable Analog Blocks. J. Electronic Testing 21(2): 135-146 (2005)
83EEAdoración Rueda, Michel Renovell, José Luis Huertas: Guest Editorial. J. Electronic Testing 21(3): 203 (2005)
82EEFlorence Azaïs, Serge Bernard, Yves Bertrand, Mariane Comte, Michel Renovell: Efficiency of Optimized Dynamic Test Flows for ADCs: Sensitivity to Specifications. J. Electronic Testing 21(3): 291-298 (2005)
81EEAntonio Andrade Jr., Gustavo Vieira, Tiago R. Balen, Marcelo Lubaszewski, Florence Azaïs, Michel Renovell: Built-in self-test of global interconnects of field programmable analog arrays. Microelectronics Journal 36(12): 1112-1123 (2005)
2004
80EEAntonio Zenteno, Víctor H. Champac, Michel Renovell, Florence Azaïs: Analysis and Attenuation Proposal in Ground Bounce. Asian Test Symposium 2004: 460-463
79EEPatrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell: High Quality TPG for Delay Faults in Look-Up Tables of FPGAs. DELTA 2004: 83-88
78EEPatrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell: BIST of Delay Faults in the Logic Architecture of Symmetrical FPGAs. IOLTS 2004: 187-192
77EEDavid Hély, Marie-Lise Flottes, Frédéric Bancel, Bruno Rouzeyre, Nicolas Bérard, Michel Renovell: Scan Design and Secure Chip. IOLTS 2004: 219-226
76EETiago R. Balen, Antonio Andrade Jr., Florence Azaïs, Michel Renovell, Marcelo Lubaszewski: Testing the Configurable Analog Blocks of Field Programmable Analog Arrays. ITC 2004: 893-902
75EEMehdi Baradaran Tahoori, Edward J. McCluskey, Michel Renovell, Philippe Faure: A Multi-Configuration Strategy for an Application Dependent Testing of FPGAs. VTS 2004: 154-170
74EEPiet Engelke, Ilia Polian, Michel Renovell, Bharath Seshadri, Bernd Becker: The Pros and Cons of Very-Low-Voltage Testing: An Analysis based on Resistive Bridging Faults. VTS 2004: 171-178
73EETiago R. Balen, Antonio Andrade Jr., Florence Azaïs, Marcelo Lubaszewski, Michel Renovell: An Approach to the Built-In Self-Test of Field Programmable Analog Arrays. VTS 2004: 383-388
72EESerge Bernard, Mariane Comte, Florence Azaïs, Yves Bertrand, Michel Renovell: Efficiency of Spectral-Based ADC Test Flows to Detect Static Errors. J. Electronic Testing 20(3): 257-267 (2004)
71EEFlorence Azaïs, Serge Bernard, Yves Bertrand, Mariane Comte, Michel Renovell: Correlation Between Static and Dynamic Parameters of A-to-D Converters: In the View of a Unique Test Procedure. J. Electronic Testing 20(4): 375-387 (2004)
70EEAlex Gonsales, Marcelo Lubaszewski, Luigi Carro, Michel Renovell: A New FPGA for DSP Applications Integrating BIST Capabilities. J. Electronic Testing 20(4): 423-431 (2004)
2003
69EEMichel Renovell, Jean Marc Gallière, Florence Azaïs, Yves Bertrand: Delay Testing of MOS Transistor with Gate Oxide Short. Asian Test Symposium 2003: 168-173
68EEPatrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell: Defect Analysis for Delay-Fault BIST in FPGAs. IOLTS 2003: 124-128
67EEPiet Engelke, Ilia Polian, Michel Renovell, Bernd Becker: Simulating Resistive Bridging and Stuck-At Faults. ITC 2003: 1051-1059
66EESerge Bernard, Mariane Comte, Florence Azaïs, Yves Bertrand, Michel Renovell: A New Methodology For ADC Test Flow Optimization. ITC 2003: 201-209
65EEFlorence Azaïs, Yves Bertrand, Michel Renovell, André Ivanov, Sassan Tabatabaei: An All-Digital DFT Scheme for Testing Catastrophic Faults in PLLs. IEEE Design & Test of Computers 20(1): 60-67 (2003)
64EEUros Kac, Franc Novak, Florence Azaïs, Pascal Nouet, Michel Renovell: Extending IEEE Std. 1149.4 Analog Boundary Modules to Enhance Mixed-Signal Test. IEEE Design & Test of Computers 20(2): 32-39 (2003)
63EEMichel Renovell, Jean Marc Gallière, Florence Azaïs, Yves Bertrand: Modeling the Random Parameters Effects in a Non-Split Model of Gate Oxide Short. J. Electronic Testing 19(4): 377-386 (2003)
62EESerge Bernard, Florence Azaïs, Yves Bertrand, Michel Renovell: On-Chip Generation of Ramp and Triangle-Wave Stimuli for ADC BIST. J. Electronic Testing 19(4): 469-479 (2003)
61EEMichel Renovell: Some Aspects of the Test Generation Problem for an Application-Oriented Test of SRAM-Based FPGAs. Journal of Circuits, Systems, and Computers 12(2): 143-158 (2003)
60EEFlorence Azaïs, Serge Bernard, Yves Bertrand, Mariane Comte, Michel Renovell: A-to-D converters static error detection from dynamic parameter measurement. Microelectronics Journal 34(10): 945-953 (2003)
2002
59 Manfred Glesner, Peter Zipf, Michel Renovell: Field-Programmable Logic and Applications, Reconfigurable Computing Is Going Mainstream, 12th International Conference, FPL 2002, Montpellier, France, September 2-4, 2002, Proceedings Springer 2002
58EEMichel Renovell, Penelope Faure, Paolo Prinetto, Yervant Zorian: Testing the Unidimensional Interconnect Architecture of Symmetrical SRAM-Based FPGA. DELTA 2002: 297-301
57EEMichel Renovell, Florence Azaïs, Yves Bertrand: Improving Defect Detection in Static-Voltage Testing. IEEE Design & Test of Computers 19(6): 83-89 (2002)
2001
56EEFlorence Azaïs, Serge Bernard, Yves Bertrand, Michel Renovell: Implementation of a linear histogram BIST for ADCs. DATE 2001: 590-595
55EESerge Bernard, Florence Azaïs, Yves Bertrand, Michel Renovell: Analog BIST Generator for ADC Testing. DFT 2001: 338-346
54EEMichel Renovell: Revisiting the Classical Fault Models through a Detailed Analysis of Realistic Defects. ISQED 2001: 359-364
53 Michel Renovell, Jean Marc Gallière, Florence Azaïs, Serge Bernard, Yves Bertrand: Boolean and current detection of MOS transistor with gate oxide short. ITC 2001: 1039-1048
52 Michel Renovell, Penelope Faure, Jean Michel Portal, Joan Figueras, Yervant Zorian: IS-FPGA : a new symmetric FPGA architecture with implicit scan. ITC 2001: 924-931
51 Florence Azaïs, Serge Bernard, Yves Bertrand, Michel Renovell: On-chip Generator of a Saw-Tooth Test Stimulus for ADC BIST. VLSI-SOC 2001: 425-436
50EEFlorence Azaïs, Serge Bernard, Yves Bertrand, Xavier Michel, Michel Renovell: A Low-Cost Adaptive Ramp Generator for Analog BIST Applications. VTS 2001: 266-271
49EEAndré Ivanov, Sumbal Rafiq, Michel Renovell, Florence Azaïs, Yves Bertrand: On the detectability of CMOS floating gate transistor faults. IEEE Trans. on CAD of Integrated Circuits and Systems 20(1): 116-128 (2001)
48EEFlorence Azaïs, Serge Bernard, Yves Bertrand, Michel Renovell: A Low-Cost BIST Architecture for Linear Histogram Testing of ADCs. J. Electronic Testing 17(2): 139-147 (2001)
47EEFlorence Azaïs, Serge Bernard, Yves Bertrand, Michel Renovell: Optimizing Sinusoidal Histogram Test for Low Cost ADC BIST. J. Electronic Testing 17(3-4): 255-266 (2001)
46EEMichel Renovell, Jean Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian: A Discussion on Test Pattern Generation for FPGA - Implemented Circuits. J. Electronic Testing 17(3-4): 283-290 (2001)
45EEMichel Renovell: Guest Editorial. J. Electronic Testing 17(5): 371 (2001)
2000
44EEMichel Renovell, Jean Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian: TOF: a tool for test pattern generation optimization of an FPGA application oriented test. Asian Test Symposium 2000: 323-328
43EELuigi Carro, Érika F. Cota, Marcelo Lubaszewski, Yves Bertrand, Florence Azaïs, Michel Renovell: TI-BIST: a temperature independent analog BIST for switched-capacitor filters. Asian Test Symposium 2000: 78-83
42EEÉrika F. Cota, Michel Renovell, Florence Azaïs, Yves Bertrand, Luigi Carro, Marcelo Lubaszewski: Reuse of Existing Resources for Analog BIST of a Switch Capacitor Filte. DATE 2000: 226-
41EEMichel Renovell: A Specific Test Methodology for Symmetric SRAM-Based FPGAs. FPL 2000: 300-311
40 Michel Renovell, Yervant Zorian: Different experiments in test generation for XILINX FPGAs. ITC 2000: 854-862
39EEMichel Renovell, Florence Azaïs, Serge Bernard, Yves Bertrand: Hardware Resource Minimization for Histogram-Based ADC BIST. VTS 2000: 247-254
38EEMichel Renovell, Florence Azaïs, J-C. Bodin, Yves Bertrand: Combining Functional and Structural Approaches for Switched-Current Circuit Testing. J. Electronic Testing 16(3): 259-267 (2000)
37EEMichel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian: An Approach to Minimize the Test Configuration for the Logic Cells of the Xilinx XC4000 FPGAs Family. J. Electronic Testing 16(3): 289-299 (2000)
36EEMichel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian: Testing the Local Interconnect Resources of SRAM-Based FPGA's. J. Electronic Testing 16(5): 513-520 (2000)
1999
35EEMichel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian: Minimizing the Number of Test Configurations for Different FPGA Families. Asian Test Symposium 1999: 363-368
34EEMichel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian: Testing the Configurable Interconnect/Logic Interface of SRAM-Based FPGA's. DATE 1999: 618-622
33 Michel Renovell, André Ivanov, Yves Bertrand, Florence Azaïs, Sumbal Rafiq: Optimal conditions for Boolean and current detection of floating gate faults. ITC 1999: 477-486
32EEMichel Renovell, Florence Azaïs, Yves Bertrand: Detection of Defects Using Fault Model Oriented Test Sequences. J. Electronic Testing 14(1-2): 13-22 (1999)
31EEMichel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian: SRAM-Based FPGAs: Testing the Embedded RAM Modules. J. Electronic Testing 14(1-2): 159-167 (1999)
1998
30EESumbal Rafiq, André Ivanov, Sassan Tabatabaei, Michel Renovell: Testing for Floating Gates Defects in CMOS Circuits. Asian Test Symposium 1998: 228-236
29EEMichel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian: SRAM-Based FPGA's: Testing the Interconnect/Logic Interface. Asian Test Symposium 1998: 266-271
28EEMichel Renovell, Florence Azaïs, J-C. Bodin, Yves Bertrand: BISTing Switched-Current Circuits. Asian Test Symposium 1998: 372-377
27EEFlorence Azaïs, André Ivanov, Michel Renovell, Yves Bertrand: A Methodology and Design for Effective Testing of Voltage-Controlled Oscillators (VCOs. Asian Test Symposium 1998: 383-387
26EEMichel Renovell: Microsystems Testing: A Challenge. Asian Test Symposium 1998: 512
25EEMichel Renovell, Florence Azaïs, Yves Bertrand: Optimized Implementations of the Multi-Configuration DFT Technique for Analog Circuits. DATE 1998: 815-821
24EEMichel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian: RAM-Based FPGA's: A Test Approach for the Configurable Logic. DATE 1998: 82-88
23EECecilia Metra, Michel Renovell, G. Mojoli, Jean Michel Portal, Sandro Pastore, Joan Figueras, Yervant Zorian, Davide Salvi, Giacomo R. Sechi: Novel Technique for Testing FPGAs. DATE 1998: 89-
22EEMichel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian: SRAM-Based FPGAs: A Fault Model for the Configurable Logig Modules. FPL 1998: 139-148
21 Karl-Erwin Großpietsch, Jacob A. Abraham, Johannes Maier, Hans-Dieter Kochs, Michel Renovell: From Dependable Computing Systems to Computing for Integrated Dependable Systems? (Panel). FTCS 1998: 296-301
20EEMichel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian: SRAM-based FPGA's: testing the LUT/RAM modules. ITC 1998: 1102-1111
19EEFlorence Azaïs, Michel Renovell, Yves Bertrand, J-C. Bodin: Design-For-Testability for Switched-Current Circuits. VTS 1998: 370-375
18EEMichel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian: Testing the Interconnect of RAM-Based FPGAs. IEEE Design & Test of Computers 15(1): 45-50 (1998)
1997
17EEMichel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian: Test Pattern and Test Configuration Generation Methodology for the Logic of RAM-Based FPGA. Asian Test Symposium 1997: 254-
16EEMichel Renovell, Florence Azaïs, Yves Bertrand: On-chip analog output response compaction. ED&TC 1997: 568-572
15 Michel Renovell, Yves Bertrand: Test Strategy Sensitivity to Defect Parameters. ITC 1997: 607-616
14EEMichel Renovell, Joan Figueras, Yervant Zorian: Test of RAM-based FPGA: methodology and application to the interconnect. VTS 1997: 230-237
1996
13EEMichel Renovell, P. Huc, Yves Bertrand: The Logic Threshold Based Voting: A Model for Local Feedback Bridging Fault. EDCC 1996: 205-213
12EEMichel Renovell, P. Huc, Yves Bertrand: Bridging fault coverage improvement by power supply control. VTS 1996: 338-343
11EEMichel Renovell, Florence Azaïs, Yves Bertrand: The multi-configuration: A DFT technique for analog circuits. VTS 1996: 54-59
1995
10EEMichel Renovell, P. Huc, Yves Bertrand: Serial transistor network modeling for bridging fault simulation. Asian Test Symposium 1995: 100-106
9EEMichel Renovell, Florence Azaïs, Yves Bertrand: A design-for-test technique for multistage analog circuits. Asian Test Symposium 1995: 113-119
8EES. Lavabre, Yves Bertrand, Michel Renovell, Christian Landrault: Test configurations to enhance the testability of sequential circuits. Asian Test Symposium 1995: 160-168
7EEMichel Renovell, P. Huc, Yves Bertrand: The concept of resistance interval: a new parametric model for realistic resistive bridging fault. VTS 1995: 184-189
6EEJoan Figueras, Michel Renovell: Current testing in dynamic CMOS circuits. J. Electronic Testing 6(1): 127-131 (1995)
1994
5EEMichel Renovell, P. Huc, Yves Bertrand: The Configuration Ratio: A Model for Simulating CMOS Intra-Gate Bridge with Variable Logic Thresholds. EDCC 1994: 165-177
1993
4 Michel Renovell, Joan Figueras: Current Testing Viability in Dynamic CMOS Circuits. DFT 1993: 207-214
3 Yves Bertrand, Frédéric Bancel, Michel Renovell: Multiconfiguration Technique to Reduce Test Duration for Sequential Circuits. ITC 1993: 989-997
2 Yves Bertrand, Frédéric Bancel, Michel Renovell: A DFT Technique to Improve ATPG Efficiency for Sequential Circuits. VLSI Design 1993: 51-54
1992
1EEMichel Renovell, Gaston Cambon: Electrical analysis and modeling of floating-gate fault. IEEE Trans. on CAD of Integrated Circuits and Systems 11(11): 1450-1458 (1992)

Coauthor Index

1Jacob A. Abraham [21]
2Antonio Q. Andrade [84]
3Antonio Andrade Jr. [73] [76] [81] [89]
4Florence Azaïs [9] [11] [16] [19] [25] [27] [28] [32] [33] [38] [39] [42] [43] [47] [48] [49] [50] [51] [53] [55] [56] [57] [60] [62] [63] [64] [65] [66] [69] [71] [72] [73] [76] [80] [81] [82] [84] [85] [88] [89] [94] [96] [100] [106]
5Tiago R. Balen [73] [76] [81] [84] [89] [95] [98] [99]
6Frédéric Bancel [2] [3] [77]
7Bernd Becker [67] [74] [86] [90] [92] [93] [102] [105]
8Nicolas Bérard [77]
9Serge Bernard [39] [47] [48] [50] [51] [53] [55] [56] [60] [62] [66] [71] [72] [82] [94] [96] [100] [101]
10Yves Bertrand [2] [3] [5] [7] [8] [9] [10] [11] [12] [13] [15] [16] [19] [25] [27] [28] [32] [33] [38] [39] [42] [43] [47] [48] [49] [50] [51] [53] [55] [56] [57] [60] [62] [63] [65] [66] [69] [71] [72] [82] [88] [106]
11J-C. Bodin [19] [28] [38]
12Bettina Braitling [105]
13José Vicente Calvano [95] [98]
14Gaston Cambon [1]
15Luigi Carro [42] [43] [70]
16Philippe Cauvet [94] [96] [100] [101]
17Víctor H. Champac (Víctor H. Champac Vilela) [80]
18Mariane Comte [60] [66] [71] [72] [82] [94] [96] [97] [100]
19Érika F. Cota [42] [43]
20Milos Drutarovský [103]
21Piet Engelke [67] [74] [86] [90] [92] [93] [102] [105]
22Penelope Faure [44] [46] [52] [58]
23Philippe Faure [75]
24Joan Figueras [4] [6] [14] [17] [18] [20] [22] [23] [24] [29] [31] [34] [35] [36] [37] [44] [46] [52]
25Mária Fischerová [103]
26Marie-Lise Flottes [77]
27Hideo Fujiwara [97]
28Jean Marc Gallière [53] [63] [69] [88] [90]
29Patrick Girard [68] [78] [79] [87] [91]
30Manfred Glesner [59]
31Alex Gonsales [70]
32Peter Gramata [103]
33Karl-Erwin Großpietsch [21]
34Rajesh K. Gupta (Rajesh Gupta) [104]
35David Hély [77]
36Olivier Héron [68] [78] [79] [87] [91]
37P. Huc [5] [7] [10] [12] [13]
38José Luis Huertas (José L. Huertas) [83]
39André Ivanov [27] [30] [33] [49] [65]
40Uros Kac [64]
41Fernanda Gusmão de Lima Kastensmidt (Fernanda Gusmão de Lima, Fernanda Lima Kastensmidt) [99]
42Vincent Kerzerho [94] [96] [100]
43Hans-Dieter Kochs [21]
44Sandip Kundu [90] [102]
45Christian Landrault [8]
46S. Lavabre [8]
47Marcelo Lubaszewski [42] [43] [70] [73] [76] [81] [84] [85] [89] [95] [98] [99] [104]
48Johannes Maier [21]
49Edward J. McCluskey [75]
50Cecilia Metra [23]
51Xavier Michel [50]
52G. Mojoli [23]
53Pascal Nouet [64] [85]
54Franc Novak [64]
55Satoshi Ohtake [97]
56Sandro Pastore [23]
57Gustavo Pereira [89]
58Ilia Polian [67] [74] [86] [90] [92] [93] [102] [105]
59Jean Michel Portal [17] [18] [20] [22] [23] [24] [29] [31] [34] [35] [36] [37] [44] [46] [52]
60Serge Pravossoudovitch [68] [78] [79] [87] [91]
61Paolo Prinetto [58]
62Sumbal Rafiq [30] [33] [49]
63Bruno Rouzeyre [77]
64Adoración Rueda [83]
65Davide Salvi [23]
66Jürgen Schlöffel [105]
67Giacomo R. Sechi [23]
68Bharath Seshadri [74] [102]
69Bernd Straube [103]
70Sassan Tabatabaei [30] [65]
71Mehdi Baradaran Tahoori [75]
72Gustavo Vieira [81]
73Antonio Zenteno [80]
74Peter Zipf [59]
75Yervant Zorian [14] [17] [18] [20] [22] [23] [24] [29] [31] [34] [35] [36] [37] [40] [44] [46] [52] [58]

Colors in the list of coauthors

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)