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Michel Renovell

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2008
86EEPiet Engelke, Ilia Polian, Michel Renovell, Sandip Kundu, Bharath Seshadri, Bernd Becker: On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing. IEEE Trans. on CAD of Integrated Circuits and Systems 27(2): 327-338 (2008)
2007
85EEPhilippe Cauvet, Serge Bernard, Michel Renovell: System-in-Package, a Combination of Challenges and Solutions. European Test Symposium 2007: 193-199
84EEVincent Kerzerho, Philippe Cauvet, Serge Bernard, Florence Azaïs, Mariane Comte, Michel Renovell: "Analogue Network of Converters": A DFT Technique to Test a Complete Set of ADCs and DACs Embedded in a Complex SiP or SOC. European Test Symposium 2007: 211-216
83EETiago R. Balen, Fernanda Lima Kastensmidt, Marcelo Lubaszewski, Michel Renovell: Single Event Upset in SRAM-based Field Programmable Analog Arrays: Effects and Mitigation. ISVLSI 2007: 192-197
82EETiago R. Balen, José Vicente Calvano, Marcelo Lubaszewski, Michel Renovell: Built-In Self-Test of Field Programmable Analog Arrays based on Transient Response Analysis. J. Electronic Testing 23(6): 497-512 (2007)
2006
81EEMariane Comte, Satoshi Ohtake, Hideo Fujiwara, Michel Renovell: Electrical Behavior of GOS Fault affected Domino Logic Cell. DELTA 2006: 183-189
80EEVincent Kerzerho, Philippe Cauvet, Serge Bernard, Florence Azaïs, Mariane Comte, Michel Renovell: "Analogue Network of Converters": A DFT Technique to Test a Complete Set of ADCs and DACs Embedded in a Complex SiP or SOC. European Test Symposium 2006: 159-164
79EETiago R. Balen, José Vicente Calvano, Marcelo Lubaszewski, Michel Renovell: Functional Test of Field Programmable Analog Arrays. VTS 2006: 326-333
78EEVincent Kerzerho, Philippe Cauvet, Serge Bernard, Florence Azaïs, Mariane Comte, Michel Renovell: A Novel DFT Technique for Testing Complete Sets of ADCs and DACs in Complex SiPs. IEEE Design & Test of Computers 23(3): 234-243 (2006)
77EEPiet Engelke, Ilia Polian, Michel Renovell, Bernd Becker: Simulating Resistive-Bridging and Stuck-At Faults. IEEE Trans. on CAD of Integrated Circuits and Systems 25(10): 2181-2192 (2006)
76EEPiet Engelke, Ilia Polian, Michel Renovell, Bernd Becker: Automatic Test Pattern Generation for Resistive Bridging Faults. J. Electronic Testing 22(1): 61-69 (2006)
75EEPatrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell: An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs. J. Electronic Testing 22(2): 161-172 (2006)
2005
74EEIlia Polian, Sandip Kundu, Jean Marc Galliere, Piet Engelke, Michel Renovell, Bernd Becker: Resistive Bridge Fault Model Evolution from Conventional to Ultra Deep Submicron Technologies. VTS 2005: 343-348
73EEGustavo Pereira, Antonio Andrade Jr., Tiago R. Balen, Marcelo Lubaszewski, Florence Azaïs, Michel Renovell: Testing the Interconnect Networks and I/O Resources of Field Programmable Analog Arrays. VTS 2005: 389-394
72EEJean Marc Galliere, Michel Renovell, Florence Azaïs, Yves Bertrand: Delay Testing Viability of Gate Oxide Short Defects. J. Comput. Sci. Technol. 20(2): 195-200 (2005)
71EEPatrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell: Delay Fault Testing of Look-Up Tables in SRAM-Based FPGAs. J. Electronic Testing 21(1): 43-55 (2005)
70EEIlia Polian, Piet Engelke, Michel Renovell, Bernd Becker: Modeling Feedback Bridging Faults with Non-Zero Resistance. J. Electronic Testing 21(1): 57-69 (2005)
69EEFlorence Azaïs, Marcelo Lubaszewski, Pascal Nouet, Michel Renovell: A Strategy for Optimal Test Point Insertion in Analog Cascaded Filters. J. Electronic Testing 21(1): 9-16 (2005)
68EETiago R. Balen, Antonio Q. Andrade, Florence Azaïs, Marcelo Lubaszewski, Michel Renovell: Applying the Oscillation Test Strategy to FPAA's Configurable Analog Blocks. J. Electronic Testing 21(2): 135-146 (2005)
67EEAdoración Rueda, Michel Renovell, José Luis Huertas: Guest Editorial. J. Electronic Testing 21(3): 203 (2005)
66EEFlorence Azaïs, Serge Bernard, Yves Bertrand, Mariane Comte, Michel Renovell: Efficiency of Optimized Dynamic Test Flows for ADCs: Sensitivity to Specifications. J. Electronic Testing 21(3): 291-298 (2005)
65EEAntonio Andrade Jr., Gustavo Vieira, Tiago R. Balen, Marcelo Lubaszewski, Florence Azaïs, Michel Renovell: Built-in self-test of global interconnects of field programmable analog arrays. Microelectronics Journal 36(12): 1112-1123 (2005)
2004
64EEAntonio Zenteno, Víctor H. Champac, Michel Renovell, Florence Azaïs: Analysis and Attenuation Proposal in Ground Bounce. Asian Test Symposium 2004: 460-463
63EEPatrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell: High Quality TPG for Delay Faults in Look-Up Tables of FPGAs. DELTA 2004: 83-88
62EEPatrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell: BIST of Delay Faults in the Logic Architecture of Symmetrical FPGAs. IOLTS 2004: 187-192
61EEDavid Hély, Marie-Lise Flottes, Frédéric Bancel, Bruno Rouzeyre, Nicolas Bérard, Michel Renovell: Scan Design and Secure Chip. IOLTS 2004: 219-226
60EETiago R. Balen, Antonio Andrade Jr., Florence Azaïs, Michel Renovell, Marcelo Lubaszewski: Testing the Configurable Analog Blocks of Field Programmable Analog Arrays. ITC 2004: 893-902
59EEMehdi Baradaran Tahoori, Edward J. McCluskey, Michel Renovell, Philippe Faure: A Multi-Configuration Strategy for an Application Dependent Testing of FPGAs. VTS 2004: 154-170
58EEPiet Engelke, Ilia Polian, Michel Renovell, Bharath Seshadri, Bernd Becker: The Pros and Cons of Very-Low-Voltage Testing: An Analysis based on Resistive Bridging Faults. VTS 2004: 171-178
57EETiago R. Balen, Antonio Andrade Jr., Florence Azaïs, Marcelo Lubaszewski, Michel Renovell: An Approach to the Built-In Self-Test of Field Programmable Analog Arrays. VTS 2004: 383-388
2003
56EEMichel Renovell, Jean Marc Galliere, Florence Azaïs, Yves Bertrand: Delay Testing of MOS Transistor with Gate Oxide Short. Asian Test Symposium 2003: 168-173
55EEPatrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell: Defect Analysis for Delay-Fault BIST in FPGAs. IOLTS 2003: 124-128
54EEPiet Engelke, Ilia Polian, Michel Renovell, Bernd Becker: Simulating Resistive Bridging and Stuck-At Faults. ITC 2003: 1051-1059
53EESerge Bernard, Mariane Comte, Florence Azaïs, Yves Bertrand, Michel Renovell: A New Methodology For ADC Test Flow Optimization. ITC 2003: 201-209
52EEFlorence Azaïs, Yves Bertrand, Michel Renovell, André Ivanov, Sassan Tabatabaei: An All-Digital DFT Scheme for Testing Catastrophic Faults in PLLs. IEEE Design & Test of Computers 20(1): 60-67 (2003)
51EEUros Kac, Franc Novak, Florence Azaïs, Pascal Nouet, Michel Renovell: Extending IEEE Std. 1149.4 Analog Boundary Modules to Enhance Mixed-Signal Test. IEEE Design & Test of Computers 20(2): 32-39 (2003)
50EEMichel Renovell: Some Aspects of the Test Generation Problem for an Application-Oriented Test of SRAM-Based FPGAs. Journal of Circuits, Systems, and Computers 12(2): 143-158 (2003)
49EEFlorence Azaïs, Serge Bernard, Yves Bertrand, Mariane Comte, Michel Renovell: A-to-D converters static error detection from dynamic parameter measurement. Microelectronics Journal 34(10): 945-953 (2003)
2002
48 Manfred Glesner, Peter Zipf, Michel Renovell: Field-Programmable Logic and Applications, Reconfigurable Computing Is Going Mainstream, 12th International Conference, FPL 2002, Montpellier, France, September 2-4, 2002, Proceedings Springer 2002
47EEMichel Renovell, Penelope Faure, Paolo Prinetto, Yervant Zorian: Testing the Unidimensional Interconnect Architecture of Symmetrical SRAM-Based FPGA. DELTA 2002: 297-301
46EEMichel Renovell, Florence Azaïs, Yves Bertrand: Improving Defect Detection in Static-Voltage Testing. IEEE Design & Test of Computers 19(6): 83-89 (2002)
2001
45EEFlorence Azaïs, Serge Bernard, Yves Bertrand, Michel Renovell: Implementation of a linear histogram BIST for ADCs. DATE 2001: 590-595
44EESerge Bernard, Florence Azaïs, Yves Bertrand, Michel Renovell: Analog BIST Generator for ADC Testing. DFT 2001: 338-346
43EEMichel Renovell: Revisiting the Classical Fault Models through a Detailed Analysis of Realistic Defects. ISQED 2001: 359-364
42 Michel Renovell, Jean Marc Galliere, Florence Azaïs, Serge Bernard, Yves Bertrand: Boolean and current detection of MOS transistor with gate oxide short. ITC 2001: 1039-1048
41 Michel Renovell, Penelope Faure, Jean Michel Portal, Joan Figueras, Yervant Zorian: IS-FPGA : a new symmetric FPGA architecture with implicit scan. ITC 2001: 924-931
40 Florence Azaïs, Serge Bernard, Yves Bertrand, Michel Renovell: On-chip Generator of a Saw-Tooth Test Stimulus for ADC BIST. VLSI-SOC 2001: 425-436
39EEFlorence Azaïs, Serge Bernard, Yves Bertrand, Xavier Michel, Michel Renovell: A Low-Cost Adaptive Ramp Generator for Analog BIST Applications. VTS 2001: 266-271
38EEAndré Ivanov, Sumbal Rafiq, Michel Renovell, Florence Azaïs, Yves Bertrand: On the detectability of CMOS floating gate transistor faults. IEEE Trans. on CAD of Integrated Circuits and Systems 20(1): 116-128 (2001)
2000
37EEMichel Renovell, Jean Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian: TOF: a tool for test pattern generation optimization of an FPGA application oriented test. Asian Test Symposium 2000: 323-328
36EELuigi Carro, Érika F. Cota, Marcelo Lubaszewski, Yves Bertrand, Florence Azaïs, Michel Renovell: TI-BIST: a temperature independent analog BIST for switched-capacitor filters. Asian Test Symposium 2000: 78-83
35EEÉrika F. Cota, Michel Renovell, Florence Azaïs, Yves Bertrand, Luigi Carro, Marcelo Lubaszewski: Reuse of Existing Resources for Analog BIST of a Switch Capacitor Filte. DATE 2000: 226-
34EEMichel Renovell: A Specific Test Methodology for Symmetric SRAM-Based FPGAs. FPL 2000: 300-311
33 Michel Renovell, Yervant Zorian: Different experiments in test generation for XILINX FPGAs. ITC 2000: 854-862
32EEMichel Renovell, Florence Azaïs, Serge Bernard, Yves Bertrand: Hardware Resource Minimization for Histogram-Based ADC BIST. VTS 2000: 247-254
1999
31EEMichel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian: Minimizing the Number of Test Configurations for Different FPGA Families. Asian Test Symposium 1999: 363-368
30EEMichel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian: Testing the Configurable Interconnect/Logic Interface of SRAM-Based FPGA's. DATE 1999: 618-622
29 Michel Renovell, André Ivanov, Yves Bertrand, Florence Azaïs, Sumbal Rafiq: Optimal conditions for Boolean and current detection of floating gate faults. ITC 1999: 477-486
1998
28EESumbal Rafiq, André Ivanov, Sassan Tabatabaei, Michel Renovell: Testing for Floating Gates Defects in CMOS Circuits. Asian Test Symposium 1998: 228-236
27EEMichel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian: SRAM-Based FPGA's: Testing the Interconnect/Logic Interface. Asian Test Symposium 1998: 266-271
26EEMichel Renovell, Florence Azaïs, J-C. Bodin, Yves Bertrand: BISTing Switched-Current Circuits. Asian Test Symposium 1998: 372-377
25EEFlorence Azaïs, André Ivanov, Michel Renovell, Yves Bertrand: A Methodology and Design for Effective Testing of Voltage-Controlled Oscillators (VCOs. Asian Test Symposium 1998: 383-387
24EEMichel Renovell: Microsystems Testing: A Challenge. Asian Test Symposium 1998: 512
23EEMichel Renovell, Florence Azaïs, Yves Bertrand: Optimized Implementations of the Multi-Configuration DFT Technique for Analog Circuits. DATE 1998: 815-821
22EEMichel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian: RAM-Based FPGA's: A Test Approach for the Configurable Logic. DATE 1998: 82-88
21EECecilia Metra, Michel Renovell, G. Mojoli, Jean Michel Portal, S. Pastore, Joan Figueras, Yervant Zorian, Davide Salvi, Giacomo R. Sechi: Novel Technique for Testing FPGAs. DATE 1998: 89-
20EEMichel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian: SRAM-Based FPGAs: A Fault Model for the Configurable Logig Modules. FPL 1998: 139-148
19 Karl-Erwin Großpietsch, Jacob A. Abraham, Johannes Maier, Hans-Dieter Kochs, Michel Renovell: From Dependable Computing Systems to Computing for Integrated Dependable Systems? (Panel). FTCS 1998: 296-301
18EEMichel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian: SRAM-based FPGA's: testing the LUT/RAM modules. ITC 1998: 1102-1111
17EEFlorence Azaïs, Michel Renovell, Yves Bertrand, J-C. Bodin: Design-For-Testability for Switched-Current Circuits. VTS 1998: 370-375
16EEMichel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian: Testing the Interconnect of RAM-Based FPGAs. IEEE Design & Test of Computers 15(1): 45-50 (1998)
1997
15EEMichel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian: Test Pattern and Test Configuration Generation Methodology for the Logic of RAM-Based FPGA. Asian Test Symposium 1997: 254-
14 Michel Renovell, Yves Bertrand: Test Strategy Sensitivity to Defect Parameters. ITC 1997: 607-616
13EEMichel Renovell, Joan Figueras, Yervant Zorian: Test of RAM-based FPGA: methodology and application to the interconnect. VTS 1997: 230-237
1996
12 Michel Renovell, P. Huc, Yves Bertrand: The Logic Threshold Based Voting: A Model for Local Feedback Bridging Fault. EDCC 1996: 205-213
11EEMichel Renovell, P. Huc, Yves Bertrand: Bridging fault coverage improvement by power supply control. VTS 1996: 338-343
10EEMichel Renovell, Florence Azaïs, Yves Bertrand: The multi-configuration: A DFT technique for analog circuits. VTS 1996: 54-59
1995
9EEMichel Renovell, P. Huc, Yves Bertrand: Serial transistor network modeling for bridging fault simulation. Asian Test Symposium 1995: 100-106
8EEMichel Renovell, Florence Azaïs, Yves Bertrand: A design-for-test technique for multistage analog circuits. Asian Test Symposium 1995: 113-119
7EES. Lavabre, Yves Bertrand, Michel Renovell, Christian Landrault: Test configurations to enhance the testability of sequential circuits. Asian Test Symposium 1995: 160-168
6EEMichel Renovell, P. Huc, Yves Bertrand: The concept of resistance interval: a new parametric model for realistic resistive bridging fault. VTS 1995: 184-189
1994
5 Michel Renovell, P. Huc, Yves Bertrand: The Configuration Ratio: A Model for Simulating CMOS Intra-Gate Bridge with Variable Logic Thresholds. EDCC 1994: 165-177
1993
4 Michel Renovell, Joan Figueras: Current Testing Viability in Dynamic CMOS Circuits. DFT 1993: 207-214
3 Yves Bertrand, Frédéric Bancel, Michel Renovell: Multiconfiguration Technique to Reduce Test Duration for Sequential Circuits. ITC 1993: 989-997
2 Yves Bertrand, Frédéric Bancel, Michel Renovell: A DFT Technique to Improve ATPG Efficiency for Sequential Circuits. VLSI Design 1993: 51-54
1992
1EEMichel Renovell, Gaston Cambon: Electrical analysis and modeling of floating-gate fault. IEEE Trans. on CAD of Integrated Circuits and Systems 11(11): 1450-1458 (1992)

Coauthor Index

1Jacob A. Abraham [19]
2Antonio Q. Andrade [68]
3Antonio Andrade Jr. [57] [60] [65] [73]
4Florence Azaïs [8] [10] [17] [23] [25] [26] [29] [32] [35] [36] [38] [39] [40] [42] [44] [45] [46] [49] [51] [52] [53] [56] [57] [60] [64] [65] [66] [68] [69] [72] [73] [78] [80] [84]
5Tiago R. Balen [57] [60] [65] [68] [73] [79] [82] [83]
6Frédéric Bancel [2] [3] [61]
7Bernd Becker [54] [58] [70] [74] [76] [77] [86]
8Nicolas Bérard [61]
9Serge Bernard [32] [39] [40] [42] [44] [45] [49] [53] [66] [78] [80] [84] [85]
10Yves Bertrand [2] [3] [5] [6] [7] [8] [9] [10] [11] [12] [14] [17] [23] [25] [26] [29] [32] [35] [36] [38] [39] [40] [42] [44] [45] [46] [49] [52] [53] [56] [66] [72]
11J-C. Bodin [17] [26]
12José Vicente Calvano [79] [82]
13Gaston Cambon [1]
14Luigi Carro [35] [36]
15Philippe Cauvet [78] [80] [84] [85]
16Víctor H. Champac (Víctor H. Champac Vilela) [64]
17Mariane Comte [49] [53] [66] [78] [80] [81] [84]
18Érika F. Cota [35] [36]
19Piet Engelke [54] [58] [70] [74] [76] [77] [86]
20Penelope Faure [37] [41] [47]
21Philippe Faure [59]
22Joan Figueras [4] [13] [15] [16] [18] [20] [21] [22] [27] [30] [31] [37] [41]
23Marie-Lise Flottes [61]
24Hideo Fujiwara [81]
25Jean Marc Galliere [42] [56] [72] [74]
26Patrick Girard [55] [62] [63] [71] [75]
27Manfred Glesner [48]
28Karl-Erwin Großpietsch [19]
29David Hély [61]
30Olivier Héron [55] [62] [63] [71] [75]
31P. Huc [5] [6] [9] [11] [12]
32José Luis Huertas (José L. Huertas) [67]
33André Ivanov [25] [28] [29] [38] [52]
34Uros Kac [51]
35Fernanda Gusmão de Lima Kastensmidt (Fernanda Gusmão de Lima, Fernanda Lima Kastensmidt) [83]
36Vincent Kerzerho [78] [80] [84]
37Hans-Dieter Kochs [19]
38Sandip Kundu [74] [86]
39Christian Landrault [7]
40S. Lavabre [7]
41Marcelo Lubaszewski [35] [36] [57] [60] [65] [68] [69] [73] [79] [82] [83]
42Johannes Maier [19]
43Edward J. McCluskey [59]
44Cecilia Metra [21]
45Xavier Michel [39]
46G. Mojoli [21]
47Pascal Nouet [51] [69]
48Franc Novak [51]
49Satoshi Ohtake [81]
50S. Pastore [21]
51Gustavo Pereira [73]
52Ilia Polian [54] [58] [70] [74] [76] [77] [86]
53Jean Michel Portal [15] [16] [18] [20] [21] [22] [27] [30] [31] [37] [41]
54Serge Pravossoudovitch [55] [62] [63] [71] [75]
55Paolo Prinetto [47]
56Sumbal Rafiq [28] [29] [38]
57Bruno Rouzeyre [61]
58Adoración Rueda [67]
59Davide Salvi [21]
60Giacomo R. Sechi [21]
61Bharath Seshadri [58] [86]
62Sassan Tabatabaei [28] [52]
63Mehdi Baradaran Tahoori [59]
64Gustavo Vieira [65]
65Antonio Zenteno [64]
66Peter Zipf [48]
67Yervant Zorian [13] [15] [16] [18] [20] [21] [22] [27] [30] [31] [33] [37] [41] [47]

Colors in the list of coauthors

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