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Marc Renaudin Vis

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*2008
60EESumanta Chaudhuri, Sylvain Guilley, Philippe Hoogvorst, Jean-Luc Danger, Taha Beyrouthy, Alin Razafindraibe, Laurent Fesquet, Marc Renaudin: Physical Design of FPGA Interconnect to Prevent Information Leakage. ARC 2008: 87-98
2007
59EECedric Koch-Hofer, Marc Renaudin: Timed Asynchronous Circuits Modeling using SystemC. FDL 2007: 110-115
58EEYannick Monnet, Marc Renaudin, Régis Leveugle: Formal Analysis of Quasi Delay Insensitive Circuits Behavior in the Presence of SEUs. IOLTS 2007: 113-120
57EECedric Koch-Hofer, Marc Renaudin, Yvain Thonnart, Pascal Vivet: ASC, a SystemC Extension for Modeling Asynchronous Systems, and Its Application to an Asynchronous NoC. NOCS 2007: 295-306
56EESylvain Miermont, Pascal Vivet, Marc Renaudin: A Power Supply Selector for Energy- and Area-Efficient Local Dynamic Voltage Scaling. PATMOS 2007: 556-565
55EEMischa Dohler, Dominique Barthel, Florence Maraninchi, Laurent Mounier, Stephane Aubert, Christophe Dugas, Aurélien Buhrig, Franck Paugnat, Marc Renaudin, Andrzej Duda, Martin Heusse, Fabrice Valois: The ARESA Project: Facilitating Research, Development and Commercialization of WSNs. SECON 2007: 590-599
54EEJulien Goulier, Eric André, Marc Renaudin: A new analytical approach of the impact of jitter on continuous time delta sigma converters. VLSI-SoC 2007: 110-115
53EEG. Fraidy Bouesse, Marc Renaudin, Sophie Dumont, Fabien Germain: DPA on quasi delay insensitive asynchronous circuits: formalization and improvement CoRR abs/0710.3443: (2007)
52EEN. Huot, H. Dubreuil, Laurent Fesquet, Marc Renaudin: FPGA Architecture for Multi-Style Asynchronous Logic CoRR abs/0710.4711: (2007)
51EEBruno Galilée, Franck Mamalet, Marc Renaudin, Pierre-Yves Coulon: Parallel Asynchronous Watershed Algorithm-Architecture. IEEE Trans. Parallel Distrib. Syst. 18(1): 44-56 (2007)
50EEJ. Fragoso, Gilles Sicard, Marc Renaudin: Estimation rapide du couple énergie/délai des circuits asynchrones QDI. Technique et Science Informatiques 26(5): 535-565 (2007)
2006
49EED. Caucheteux, Edith Beigné, Elisabeth Crochon, Marc Renaudin: AsyncRFID: Fully Asynchronous Contactless Systems, Providing High Data Rates, Low Power and Dynamic Adaptation. ASYNC 2006: 86-97
48EEG. Fraidy Bouesse, Gilles Sicard, Marc Renaudin: Path Swapping Method to Improve DPA Resistance of Quasi Delay Insensitive Asynchronous Circuits. CHES 2006: 384-398
47EEYannick Monnet, Marc Renaudin, Régis Leveugle, Christophe Clavier, Pascal Moitrel: Case Study of a Fault Attack on Asynchronous DES Crypto-Processors. FDTC 2006: 88-97
46EEYannick Monnet, Marc Renaudin, Régis Leveugle, Nathalie Feyt, Pascal Moitrel, F. M'Buwa Nzenguet: Practical Evaluation of Fault Countermeasures on an Asynchronous DES Crypto Processor. IOLTS 2006: 125-130
45EEMarc Renaudin, Yannick Monnet: Asynchronous Design: Fault Robustness and Security Characteristics. IOLTS 2006: 92-95
44EEEslam Yahya, Marc Renaudin: QDI Latches Characteristics and Asynchronous Linear-Pipeline Performance Analysis. PATMOS 2006: 583-592
43EELaurent Fesquet, Bertrand Folco, M. Steiner, Marc Renaudin: State-holding in Look-Up Tables: application to asynchronous logic. VLSI-SoC 2006: 12-17
42EEAlin Razafindraibe, Philippe Maurine, Michel Robert, Marc Renaudin: Security evaluation of dual rail logic against DPA attacks. VLSI-SoC 2006: 181-186
41EEYannick Monnet, Marc Renaudin, Régis Leveugle: Designing Resistant Circuits against Malicious Faults Injection Using Asynchronous Logic. IEEE Trans. Computers 55(9): 1104-1115 (2006)
40EEDavid Rios-Arambula, Aurélien Buhrig, Gilles Sicard, Marc Renaudin: On the Use of Feedback Systems to Dynamically Control the Supply Voltage of Low-Power Circuits. J. Low Power Electronics 2(1): 45-55 (2006)
2005
39EEEdith Beigné, Fabien Clermidy, Pascal Vivet, Alain Clouard, Marc Renaudin: An Asynchronous NOC Architecture Providing Low Latency Service and Its Multi-Level Design Framework. ASYNC 2005: 54-63
38EEYannick Monnet, Marc Renaudin, Régis Leveugle: Asynchronous circuits transient faults sensitivity evaluation. DAC 2005: 863-868
37EEN. Huot, H. Dubreuil, Laurent Fesquet, Marc Renaudin: FPGA Architecture for Multi-Style Asynchronous Logic. DATE 2005: 32-33
36EEG. Fraidy Bouesse, Marc Renaudin, Sophie Dumont, Fabien Germain: DPA on Quasi Delay Insensitive Asynchronous Circuits: Formalization and Improvement. DATE 2005: 424-429
35 Laurent Fesquet, Marc Renaudin: A Programmable Logic Architecture for Prototyping Clockless Circuits. FPL 2005: 293-298
34 Jerome Quartana, Salim Renane, Arnaud Baixas, Laurent Fesquet, Marc Renaudin: GALS systems prototyping using multiclock FPGAs and asynchronous network-on-chips. FPL 2005: 299-304
33EEYannick Monnet, Marc Renaudin, Régis Leveugle: Hardening Techniques against Transient Faults for Asynchronous Circuits. IOLTS 2005: 129-134
32EEEmmanuel Allier, Julien Goulier, Gilles Sicard, A. Dezzani, Eric André, Marc Renaudin: A 120nm low power asynchronous ADC. ISLPED 2005: 60-65
31EEDavid Rios-Arambula, Aurélien Buhrig, Marc Renaudin: Power Consumption Reduction Using Dynamic Control of Micro Processor Performance. PATMOS 2005: 10-18
30EEAlin Razafindraibe, Michel Robert, Marc Renaudin, Philippe Maurine: A Method to Design Compact Dual-rail Asynchronous Primitives. PATMOS 2005: 571-580
29 Laurent Fesquet, Jerome Quartana, Marc Renaudin: Asynchronous Systems on Programmable Logic. ReCoSoC 2005: 105-112
28EEG. Fraidy Bouesse, Marc Renaudin, Gilles Sicard: Improving DPA Resistance of Quasi Delay Insensitive Circuits Using Randomly Time-shifted Acknowledgment Signals. VLSI-SoC 2005: 11-24
27EEJerome Quartana, Laurent Fesquet, Marc Renaudin: Modular Asynchronous Network-on-Chip: Application to GALS Systems Rapid Prototyping. VLSI-SoC 2005: 195-207
26EEBertrand Folco, Vivian Brégier, Laurent Fesquet, Marc Renaudin: Technology Mapping for Area Optimized Quasi Delay Insensitive Circuits. VLSI-SoC 2005: 55-69
2004
25EEF. Aeschlimann, Emmanuel Allier, Laurent Fesquet, Marc Renaudin: Asynchronous FIR Filters: Towards a New Digital Processing Chain. ASYNC 2004: 198-206
24EEMarc Renaudin, G. Fraidy Bouesse, Ph. Proust, J. P. Tual, Laurent Sourgen, Fabien Germain: High Security Smartcards. DATE 2004: 228-233
23EEYannick Monnet, Marc Renaudin, Régis Leveugle: Asynchronous Circuits Sensitivity to Fault Injection. IOLTS 2004: 121-128
22EEKamel Slimani, Yann Rémond, Gilles Sicard, Marc Renaudin: TAST Profiler and Low Energy Asynchronous Design Methodology. PATMOS 2004: 268-277
21EEDhanistha Panyasak, Gilles Sicard, Marc Renaudin: A current shaping methodology for lowering em disturbances in asynchronous circuits. Microelectronics Journal 35(6): 531-540 (2004)
2003
20EEEmmanuel Allier, Gilles Sicard, Laurent Fesquet, Marc Renaudin: A New Class of Asynchronous A/D Converters Based on Time Quantization. ASYNC 2003: 196-205
19EEDominique Borrione, Menouer Boubekeur, Emil Dumitrescu, Marc Renaudin, Jean-Baptiste Rigaud, Antoine Sirianni: An Approach to the Introduction of Formal Validation in an Asynchronous Circuit Design Flow. HICSS 2003: 279
18EEJoão Leonardo Fragoso, Gilles Sicard, Marc Renaudin: Power/Area Tradeoffs in 1-of-M Parallel-Prefix Asynchronous Adders. PATMOS 2003: 171-180
17EEPhilippe Maurine, Jean-Baptiste Rigaud, G. Fraidy Bouesse, Gilles Sicard, Marc Renaudin: Statistic Implementation of QDI Asynchronous Primitives. PATMOS 2003: 181-191
16EEJoão Leonardo Fragoso, Gilles Sicard, Marc Renaudin: Automatic Generation of 1-of-M QDI Asynchronous Adders. SBCCI 2003: 149-154
15 Dominique Borrione, Menouer Boubekeur, Laurent Mounier, Marc Renaudin, Antoine Sirianni: Validation of asynchronous circuit specifications using IF/CADP. VLSI-SOC 2003: 86-91
2002
14EEJean-Baptiste Rigaud, Laurent Fesquet, Marc Renaudin, Jerome Quartana: High-Level Modeling and Design of Asynchronous Arbiters for On-Chip Communication Systems. DATE 2002: 1090
13EEQuoc Thai Ho, Jean-Baptiste Rigaud, Laurent Fesquet, Marc Renaudin, Robin Rolland: Implementing Asynchronous Circuits on LUT Based FPGAs. FPL 2002: 36-46
12 Anh Vu Dihn Duc, Laurent Fesquet, Marc Renaudin: Synthesis of QDI Asynchronous Circuits from DTL-Style Petri-Net. IWLS 2002: 191-196
11EEMohammed Es Salhiene, Laurent Fesquet, Marc Renaudin: Dynamic Voltage Scheduling for Real Time Asynchronous Systems. PATMOS 2002: 390-399
10EEEmmanuel Allier, Laurent Fesquet, Marc Renaudin, Gilles Sicard: Low-Power Asynchronous A/D Conversion. PATMOS 2002: 81-91
2001
9EEChristian Piguet, Marc Renaudin, Thierry J.-F. Omnés: Low-power systems on chips (SOCs). DATE 2001: 488
8 Jean-Baptiste Rigaud, Jerome Quartana, Laurent Fesquet, Marc Renaudin: Modeling and Design of Asynchronous Priority Arbiters for On-Chip Communication Systems. VLSI-SOC 2001: 313-324
1999
7EEMarc Renaudin, Pascal Vivet, Frédéric Robin: A Design Framework for Asynchronous/Synchronous Circuits Based on CHP to VHDL Translation. ASYNC 1999: 135-144
1998
6EEMarc Renaudin, Pascal Vivet, Frédéric Robin: ASPRO-216: A Standard-Cell Q.D.I. 16-Bit RISC Asynchronous Microprocessor. ASYNC 1998: 22-31
1997
5 Frédéric Robin, Gilles Privat, Marc Renaudin: Asynchronous Relaxation of Morphological Operators: A Joint Algorithm-Architecture Perspective. IJPRAI 11(7): 1085-1094 (1997)
1996
4EEAlain Guyot, Marc Renaudin, Bachar El Hassan, Volker Levering: Self timed division and square-root extraction. VLSI Design 1996: 376-381
1995
3 Gilles Privat, Frédéric Robin, Marc Renaudin, Bachar El Hassan: A Fine-Grain Asynchronous VLSI Cellular Array Processor Architecture. ISCAS 1995: 1041-1044
1994
2 Marc Renaudin, Bachar El Hassan: The Design of Fast Asynchronous Adder Structures and their Implementation Using D.C.V.S. Logic. ISCAS 1994: 291-294
1993
1EEA. K. Betts, Ivo Bolsens, E. Sicard, Marc Renaudin, A. Johnstone: SMILE: A scalable microcontroller library element. Microprocessing and Microprogramming 39(2-5): 259-262 (1993)

Coauthor Index

1F. Aeschlimann [25]
2Emmanuel Allier [10] [20] [25] [32]
3Eric André [32] [54]
4Stephane Aubert [55]
5Arnaud Baixas [34]
6Dominique Barthel [55]
7Edith Beigné [39] [49]
8A. K. Betts [1]
9Taha Beyrouthy [60]
10Ivo Bolsens [1]
11Dominique Borrione [15] [19]
12Menouer Boubekeur [15] [19]
13G. Fraidy Bouesse [17] [24] [28] [36] [48] [53]
14Vivian Brégier [26]
15Aurélien Buhrig [31] [40] [55]
16D. Caucheteux [49]
17Sumanta Chaudhuri [60]
18Christophe Clavier [47]
19Fabien Clermidy [39]
20Alain Clouard [39]
21Pierre-Yves Coulon [51]
22Elisabeth Crochon [49]
23Jean-Luc Danger [60]
24A. Dezzani [32]
25Mischa Dohler [55]
26H. Dubreuil [37] [52]
27Anh Vu Dihn Duc [12]
28Andrzej Duda [55]
29Christophe Dugas [55]
30Emil Dumitrescu [19]
31Sophie Dumont [36] [53]
32Laurent Fesquet [8] [10] [11] [12] [13] [14] [20] [25] [26] [27] [29] [34] [35] [37] [43] [52] [60]
33Nathalie Feyt [46]
34Bertrand Folco [26] [43]
35J. Fragoso [50]
36João Leonardo Fragoso [16] [18]
37Bruno Galilée [51]
38Fabien Germain [24] [36] [53]
39Julien Goulier [32] [54]
40Sylvain Guilley [60]
41Alain Guyot [4]
42Bachar El Hassan [2] [3] [4]
43Martin Heusse [55]
44Quoc Thai Ho [13]
45Philippe Hoogvorst [60]
46N. Huot [37] [52]
47A. Johnstone [1]
48Cedric Koch-Hofer [57] [59]
49Volker Levering [4]
50Régis Leveugle [23] [33] [38] [41] [46] [47] [58]
51Franck Mamalet [51]
52Florence Maraninchi [55]
53Philippe Maurine [17] [30] [42]
54Sylvain Miermont [56]
55Pascal Moitrel [46] [47]
56Yannick Monnet [23] [33] [38] [41] [45] [46] [47] [58]
57Laurent Mounier [15] [55]
58F. M'Buwa Nzenguet [46]
59Thierry J.-F. Omnés [9]
60Dhanistha Panyasak [21]
61Franck Paugnat [55]
62Christian Piguet [9]
63Gilles Privat [3] [5]
64Ph. Proust [24]
65Jerome Quartana [8] [14] [27] [29] [34]
66Alin Razafindraibe [30] [42] [60]
67Yann Rémond [22]
68Salim Renane [34]
69Jean-Baptiste Rigaud [8] [13] [14] [17] [19]
70David Rios-Arambula [31] [40]
71Michel Robert [30] [42]
72Frédéric Robin [3] [5] [6] [7]
73Robin Rolland [13]
74Mohammed Es Salhiene [11]
75E. Sicard [1]
76Gilles Sicard [10] [16] [17] [18] [20] [21] [22] [28] [32] [40] [48] [50]
77Antoine Sirianni [15] [19]
78Kamel Slimani [22]
79Laurent Sourgen [24]
80M. Steiner [43]
81Yvain Thonnart [57]
82J. P. Tual [24]
83Fabrice Valois [55]
84Pascal Vivet [6] [7] [39] [56] [57]
85Eslam Yahya [44]

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Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)