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Sudhakar M. Reddy Vis

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*2009
451EEIrith Pomeranz, Sudhakar M. Reddy: Definition and application of approximate necessary assignments. ACM Great Lakes Symposium on VLSI 2009: 105-108
450EEIrith Pomeranz, Sudhakar M. Reddy: State persistence: a property for guiding test generation. ACM Great Lakes Symposium on VLSI 2009: 523-528
449EEIrith Pomeranz, Sudhakar M. Reddy: Partitioned n-detection test generation. ACM Great Lakes Symposium on VLSI 2009: 93-98
448EEIrith Pomeranz, Sudhakar M. Reddy: Dynamic test compaction for a random test generation procedure with input cube avoidance. ASP-DAC 2009: 672-677
447EEFan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz: Detectability of internal bridging faults in scan chains. ASP-DAC 2009: 678-683
446EEXun Tang, Ruifeng Guo, Wu-Tung Cheng, Sudhakar M. Reddy: Improving compressed test pattern generation for multiple scan chain failure diagnosis. DATE 2009: 1000-1005
445EESantiago Remersaro, Janusz Rajski, Sudhakar M. Reddy, Irith Pomeranz: A scalable method for the generation of small test sets. DATE 2009: 1136-1141
444EEIrith Pomeranz, Sudhakar M. Reddy: Selection of a fault model for fault diagnosis based on unique responses. DATE 2009: 994-999
443EEAftab Farooqi, Richard O. Gale, Sudhakar M. Reddy, Brian Nutter, Chris Monico: Markov source based test length optimized SCAN-BIST architecture. ISQED 2009: 708-713
442EEIrith Pomeranz, Sudhakar M. Reddy: The Effect of Filling the Unspecified Values of a Test Set on the Test Set Quality. VLSI Design 2009: 215-220
441EEAlejandro Czutro, Ilia Polian, Matthew D. T. Lewis, Piet Engelke, Sudhakar M. Reddy, Bernd Becker: TIGUAN: Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability ANalysis. VLSI Design 2009: 227-232
440EEIrith Pomeranz, Sudhakar M. Reddy: Functional Broadside Tests Under an Expanded Definition of Functional Operation Conditions. IEEE Trans. on CAD of Integrated Circuits and Systems 28(1): 121-129 (2009)
439EES. Saqib Khursheed, Bashir M. Al-Hashimi, Sudhakar M. Reddy, Peter Harrod: Diagnosis of Multiple-Voltage Design With Bridge Defect. IEEE Trans. on CAD of Integrated Circuits and Systems 28(3): 406-416 (2009)
438EEIrith Pomeranz, Sudhakar M. Reddy: Double-Single Stuck-at Faults: A Delay Fault Model for Synchronous Sequential Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 28(3): 426-432 (2009)
2008
437EEIrith Pomeranz, Sudhakar M. Reddy: Circuit lines for guiding the generation of random test sequences for synchronous sequential circuits. ASP-DAC 2008: 641-646
436EEIrith Pomeranz, Sudhakar M. Reddy: Test vector chains for increased targeted and untargeted fault coverage. ASP-DAC 2008: 663-666
435EESudhakar M. Reddy, Irith Pomeranz, Chen Liu: On tests to detect via opens in digital CMOS circuits. DAC 2008: 840-845
434EEIrith Pomeranz, Sudhakar M. Reddy: A Bridging Fault Model Where Undetectable Faults Imply Logic Redundancy. DATE 2008: 1166-1171
433EEIrith Pomeranz, Sudhakar M. Reddy: A Same/Different Fault Dictionary: An Extended Pass/Fail Fault Dictionary with Improved Diagnostic Resolution. DATE 2008: 1474-1479
432EEIlia Polian, Sudhakar M. Reddy, Irith Pomeranz, Xun Tang, Bernd Becker: On Reducing Circuit Malfunctions Caused by Soft Errors. DFT 2008: 245-253
431EESantiago Remersaro, Janusz Rajski, Thomas Rinderknecht, Sudhakar M. Reddy, Irith Pomeranz: ATPG Heuristics Dependant Observation Point Insertion for Enhanced Compaction and Data Volume Reduction. DFT 2008: 385-393
430EEFan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz: Detection of Transistor Stuck-Open Faults in Asynchronous Inputs of Scan Cells. DFT 2008: 394-402
429EEIlia Polian, Sudhakar M. Reddy, Bernd Becker: Scalable Calculation of Logical Masking Effects for Selective Hardening Against Soft Errors. ISVLSI 2008: 257-262
428EEIrith Pomeranz, Sudhakar M. Reddy, Sandip Kundu: On Common-Mode Skewed-Load and Broadside Tests. VLSI Design 2008: 151-156
427EEIrith Pomeranz, Sudhakar M. Reddy: Design-for-Testability for Improved Path Delay Fault Coverage of Critical Paths. VLSI Design 2008: 175-180
426EEIrith Pomeranz, Sudhakar M. Reddy: Design-for-Testability for Synchronous Sequential Circuits that Maintains Functional Switching Activity. VLSI Design 2008: 181-186
425EEIrith Pomeranz, Sudhakar M. Reddy: Synthesis for Broadside Testability of Transition Faults. VTS 2008: 221-226
424EEIrith Pomeranz, Sudhakar M. Reddy: Expanded Definition of Functional Operation Conditions and its Effects on the Computation of Functional Broadside Tests. VTS 2008: 317-322
423EEFan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz: On the Detectability of Scan Chain Internal Faults — An Industrial Case Study. VTS 2008: 79-84
422EEIrith Pomeranz, Sudhakar M. Reddy: Transition Path Delay Faults: A New Path Delay Fault Model for Small and Large Delay Defects. IEEE Trans. VLSI Syst. 16(1): 98-107 (2008)
421EEIrith Pomeranz, Sudhakar M. Reddy: Improving the Transition Fault Coverage of Functional Broadside Tests by Observation Point Insertion. IEEE Trans. VLSI Syst. 16(7): 931-936 (2008)
420EEIrith Pomeranz, Sudhakar M. Reddy: Unspecified Transition Faults: A Transition Fault Model for At-Speed Fault Simulation and Test Generation. IEEE Trans. on CAD of Integrated Circuits and Systems 27(1): 137-146 (2008)
419EEIrith Pomeranz, Sudhakar M. Reddy: Primary Input Vectors to Avoid in Random Test Sequences for Synchronous Sequential Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 27(1): 193-197 (2008)
418EEIrith Pomeranz, Sudhakar M. Reddy: Scan-Based Delay Test Types and Their Effect on Power Dissipation During Test. IEEE Trans. on CAD of Integrated Circuits and Systems 27(2): 398-403 (2008)
417EEHangkyu Lee, Irith Pomeranz, Sudhakar M. Reddy: On Complete Functional Broadside Tests for Transition Faults. IEEE Trans. on CAD of Integrated Circuits and Systems 27(3): 583-587 (2008)
416EEIrith Pomeranz, Sudhakar M. Reddy: On the Saturation of n-Detection Test Generation by Different Definitions With Increased n. IEEE Trans. on CAD of Integrated Circuits and Systems 27(5): 946-957 (2008)
415EEKohei Miyase, Kenta Terashima, Xiaoqing Wen, Seiji Kajihara, Sudhakar M. Reddy: On Detection of Bridge Defects with Stuck-at Tests. IEICE Transactions 91-D(3): 683-689 (2008)
2007
414EEZhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz: Warning: Launch off Shift Tests for Delay Faults May Contribute to Test Escapes. ASP-DAC 2007: 817-822
413EEIrith Pomeranz, Sudhakar M. Reddy: On test generation by input cube avoidance. DATE 2007: 522-527
412EEIrith Pomeranz, Sudhakar M. Reddy: A-Diagnosis: A Complement to Z-Diagnosis. DFT 2007: 235-242
411EEIrith Pomeranz, Sudhakar M. Reddy: Semi-Concurrent On-Line Testing of Transition Faults Through Output Response Comparison of Identical Circuits. DFT 2007: 457-455
410EEIrith Pomeranz, Sudhakar M. Reddy: Diagnostic Test Generation Based on Subsets of Faults. European Test Symposium 2007: 151-158
409EEYuan Cai, Sudhakar M. Reddy, Bashir M. Al-Hashimi: Reducing the Energy Consumption in Fault-Tolerant Distributed Embedded Systems with Time-Constraint. ISQED 2007: 368-373
408EEIrith Pomeranz, Sudhakar M. Reddy: Equivalence and Dominance Relations Between Fault Pairs and Their Use in Fault Pair Collapsing for Fault Diagnosis. VLSI Design 2007: 498-503
407EESantiago Remersaro, Xijiang Lin, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski: Low Shift and Capture Power Scan Tests. VLSI Design 2007: 793-798
406EEIrith Pomeranz, Sudhakar M. Reddy: Functional Broadside Tests with Different Levels of Reachability. VLSI Design 2007: 799-804
405EEWei Zou, Wu-Tung Cheng, Sudhakar M. Reddy, Huaxing Tang: Speeding Up Effect-Cause Defect Diagnosis Using a Small Dictionary. VTS 2007: 225-230
404EEIrith Pomeranz, Sudhakar M. Reddy: Autoscan-Invert: An Improved Scan Design without External Scan Inputs or Outputs. VTS 2007: 416-421
403EEYuan Cai, Marcus T. Schmitz, Bashir M. Al-Hashimi, Sudhakar M. Reddy: Workload-ahead-driven online energy minimization techniques for battery-powered embedded systems with time-constraints. ACM Trans. Design Autom. Electr. Syst. 12(1): (2007)
402EEIrith Pomeranz, Sudhakar M. Reddy: Forming N-detection test sets without test generation. ACM Trans. Design Autom. Electr. Syst. 12(2): (2007)
401EEIrith Pomeranz, Sudhakar M. Reddy: The Accidental Detection Index as a Fault Ordering Heuristic for Full-Scan Circuits CoRR abs/0710.4637: (2007)
400EEIrith Pomeranz, Sudhakar M. Reddy: Worst-Case and Average-Case Analysis of n-Detection Test Sets CoRR abs/0710.4735: (2007)
399EEIrith Pomeranz, Sudhakar M. Reddy: On the Use of Functional Test Generation in Diagnostic Test Generation for Synchronous Sequential Circuits. Electr. Notes Theor. Comput. Sci. 174(4): 83-93 (2007)
398EESantiago Remersaro, Xijiang Lin, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski: Scan-Based Tests with Low Switching Activity. IEEE Design & Test of Computers 24(3): 268-275 (2007)
397EEIrith Pomeranz, Sudhakar M. Reddy: Generation of Broadside Transition-Fault Test Sets That Detect Four-Way Bridging Faults. IEEE Trans. on CAD of Integrated Circuits and Systems 26(7): 1311-1319 (2007)
396EEIrith Pomeranz, Sudhakar M. Reddy, Srikanth Venkataraman: z-Diagnosis: A Framework for Diagnostic Fault Simulation and Test Generation Utilizing Subsets of Outputs. IEEE Trans. on CAD of Integrated Circuits and Systems 26(9): 1700-1712 (2007)
2006
395EEYuan Cai, Marcus T. Schmitz, Alireza Ejlali, Bashir M. Al-Hashimi, Sudhakar M. Reddy: Cache size selection for performance, energy and reliability of time-constrained systems. ASP-DAC 2006: 923-928
394EEGang Chen, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski: A test pattern ordering algorithm for diagnosis with truncated fail data. DAC 2006: 399-404
393EEIrith Pomeranz, Sudhakar M. Reddy: Test compaction for transition faults under transparent-scan. DATE 2006: 1264-1269
392EEIrith Pomeranz, Sudhakar M. Reddy: Generation of broadside transition fault test sets that detect four-way bridging faults. DATE 2006: 907-912
391EENarendra Devta-Prasanna, Arun Gunda, P. Krishnamurthy, Sudhakar M. Reddy, Irith Pomeranz: Test Generation for Open Defects in CMOS Circuits. DFT 2006: 41-49
390EEIrith Pomeranz, Sudhakar M. Reddy: Scan-Based Delay Fault Tests for Diagnosis of Transition Faults. DFT 2006: 419-427
389EEIrith Pomeranz, Sudhakar M. Reddy: Fault Collapsing for Transition Faults Using Extended Transition Faults. European Test Symposium 2006: 173-178
388EENarendra Devta-Prasanna, Arun Gunda, P. Krishnamurthy, Sudhakar M. Reddy, Irith Pomeranz: A Unified Method to Detect Transistor Stuck-Open Faults and Transition Delay Faults. European Test Symposium 2006: 185-192
387EEZhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski, Bashir M. Al-Hashimi: Enhancing Delay Fault Coverage through Low Power Segmented Scan. European Test Symposium 2006: 21-28
386EEIrith Pomeranz, Sudhakar M. Reddy: A delay fault model for at-speed fault simulation and test generation. ICCAD 2006: 89-95
385EEChaowen Yu, Sudhakar M. Reddy, Irith Pomeranz: A Partitioning Technique for Identification of Error-Capturing Scan Cells in Scan-BIST. IOLTS 2006: 37-42
384EEWei Zou, Wu-Tung Cheng, Sudhakar M. Reddy, Huaxing Tang: On Methods to Improve Location Based Logic Diagnosis. VLSI Design 2006: 181-187
383EEGang Chen, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski: New Procedures to Identify Redundant Stuck-At Faults and Removal of Redundant Logic. VLSI Design 2006: 419-424
382EEIrith Pomeranz, Sudhakar M. Reddy: The Cut Delay Fault Model for Guiding the Generation of n-Detection Test Sets for Transition Faults. VLSI Design 2006: 828-831
381EEHangkyu Lee, Irith Pomeranz, Sudhakar M. Reddy: A Test Generation Procedure for Avoiding the Detection of Functionally Redundant Transition Faults. VTS 2006: 294-299
380EEZhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz, Xijiang Lin, Janusz Rajski: Scan Tests with Multiple Fault Activation Cycles for Delay Faults. VTS 2006: 343-348
379EEBharath Seshadri, Irith Pomeranz, Srikanth Venkataraman, Enamul Amyeen, Sudhakar M. Reddy: Dominance Based Analysis for Large Volume Production Fail Diagnosis. VTS 2006: 392-399
378EEIrith Pomeranz, Sudhakar M. Reddy: On Generating Tests that Avoid the Detection of Redundant Faults in Synchronous Sequential Circuits with Full Scan. IEEE Trans. Computers 55(4): 491-495 (2006)
377EEIrith Pomeranz, Sudhakar M. Reddy: Generation of Functional Broadside Tests for Transition Faults. IEEE Trans. on CAD of Integrated Circuits and Systems 25(10): 2207-2218 (2006)
376EEIrith Pomeranz, Sudhakar M. Reddy: Using Dummy Bridging Faults to Define Reduced Sets of Target Faults. IEEE Trans. on CAD of Integrated Circuits and Systems 25(10): 2219-2227 (2006)
375EEIrith Pomeranz, Sudhakar M. Reddy: Improved n-Detection Test Sequences Under Transparent Scan. IEEE Trans. on CAD of Integrated Circuits and Systems 25(11): 2492-2501 (2006)
374EEIrith Pomeranz, Sudhakar M. Reddy: Scan-BIST based on transition probabilities for circuits with single and multiple scan chains. IEEE Trans. on CAD of Integrated Circuits and Systems 25(3): 591-596 (2006)
373EEIrith Pomeranz, Sudhakar M. Reddy: Transparent DFT: a design for testability and test generation approach for synchronous sequential circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 25(6): 1170-1175 (2006)
2005
372EEChaowen Yu, Sudhakar M. Reddy, Irith Pomeranz: Circuit Independent Weighted Pseudo-Random BIST Pattern Generator. Asian Test Symposium 2005: 132-137
371EENarendra Devta-Prasanna, Sudhakar M. Reddy, Arun Gunda, P. Krishnamurthy, Irith Pomeranz: Improved Delay Fault Coverage Using Subsets of Flip-flops to Launch Transitions. Asian Test Symposium 2005: 202-207
370EEKohei Miyase, Kenta Terashima, Seiji Kajihara, Xiaoqing Wen, Sudhakar M. Reddy: On Improving Defect Coverage of Stuck-at Fault Tests. Asian Test Symposium 2005: 216-223
369EEWei Zou, Wu-Tung Cheng, Sudhakar M. Reddy: Bridge Defect Diagnosis with Physical Information. Asian Test Symposium 2005: 248-253
368EEIrith Pomeranz, Sudhakar M. Reddy: The Accidental Detection Index as a Fault Ordering Heuristic for Full-Scan Circuits. DATE 2005: 1008-1013
367EEIrith Pomeranz, Sudhakar M. Reddy: Worst-Case and Average-Case Analysis of n-Detection Test Sets. DATE 2005: 444-449
366EEHuaxing Tang, Gang Chen, Sudhakar M. Reddy, Chen Wang, Janusz Rajski, Irith Pomeranz: Defect Aware Test Patterns. DATE 2005: 450-455
365EEZhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz: On Generating Pseudo-Functional Delay Fault Tests for Scan Designs. DFT 2005: 398-405
364EEIrith Pomeranz, Sudhakar M. Reddy: Recovery During Concurrent On-Line Testing of Identical Circuits. DFT 2005: 475-483
363EENarendra Devta-Prasanna, Arun Gunda, P. Krishnamurthy, Sudhakar M. Reddy, Irith Pomeranz: A Novel Method of Improving Transition Delay Fault Coverage Using Multiple Scan Enable Signals. ICCD 2005: 471-474
362EEYuan Cai, Sudhakar M. Reddy, Irith Pomeranz, Bashir M. Al-Hashimi: Battery-aware dynamic voltage scaling in multiprocessor embedded system. ISCAS (1) 2005: 616-619
361EEIrith Pomeranz, Sudhakar M. Reddy: Dynamic Test Compaction for Bridging Faults. ISQED 2005: 250-255
360EEWei Li, Sudhakar M. Reddy, Irith Pomeranz: On Reducing Peak Current and Power during Test. ISVLSI 2005: 156-161
359EEIrith Pomeranz, Srikanth Venkataraman, Sudhakar M. Reddy: Fault Diagnosis and Fault Model Aliasing. ISVLSI 2005: 206-211
358EEIrith Pomeranz, Sudhakar M. Reddy: Tuple Detection for Path Delay Faults: A Method for Improving Test Set Quality. VLSI Design 2005: 41-46
357EEWei Li, Seongmoon Wang, Srimat T. Chakradhar, Sudhakar M. Reddy: Distance Restricted Scan Chain Reordering to Enhance Delay Fault Coverage. VLSI Design 2005: 471-478
356EEHuaxing Tang, Chen Wang, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer, Irith Pomeranz: On Efficient X-Handling Using a Selective Compaction Scheme to Achieve High Test Response Compaction Ratios. VLSI Design 2005: 59-64
355EEIrith Pomeranz, Sudhakar M. Reddy: Concurrent Online Testing of Identical Circuits Using Nonidentical Input Vectors. IEEE Trans. Dependable Sec. Comput. 2(3): 190-200 (2005)
354EEIrith Pomeranz, Sudhakar M. Reddy: Autoscan: a scan design without external scan inputs or outputs. IEEE Trans. VLSI Syst. 13(9): 1087-1095 (2005)
353EEYonsang Cho, Irith Pomeranz, Sudhakar M. Reddy: On reducing test application time for scan circuits using limited scan operations and transfer sequences. IEEE Trans. on CAD of Integrated Circuits and Systems 24(10): 1594-1605 (2005)
352EEIrith Pomeranz, Sudhakar M. Reddy: On masking of redundant faults in synchronous sequential circuits with design-for-testability logic. IEEE Trans. on CAD of Integrated Circuits and Systems 24(2): 288-294 (2005)
351EEJanusz Rajski, Jerzy Tyszer, Chen Wang, Sudhakar M. Reddy: Finite memory test response compactors for embedded test applications. IEEE Trans. on CAD of Integrated Circuits and Systems 24(4): 622-634 (2005)
350EEIrith Pomeranz, Sudhakar M. Reddy: On fault equivalence, fault dominance, and incompletely specified test sets. IEEE Trans. on CAD of Integrated Circuits and Systems 24(8): 1271-1274 (2005)
2004
349EEIrith Pomeranz, Sudhakar M. Reddy: Properties of Maximally Dominating Faults. Asian Test Symposium 2004: 106-111
348EEChaowen Yu, Sudhakar M. Reddy, Irith Pomeranz: Weighted Pseudo-Random BIST for N-Detection of Single Stuck-at Faults. Asian Test Symposium 2004: 178-183
347EEIrith Pomeranz, Sudhakar M. Reddy: A Postprocessing Procedure of Test Enrichment for Path Delay Faults. Asian Test Symposium 2004: 448-453
346EEKohei Miyase, Seiji Kajihara, Sudhakar M. Reddy: Multiple Scan Tree Design with Test Vector Modification. Asian Test Symposium 2004: 76-81
345EEWei Li, Sudhakar M. Reddy, Irith Pomeranz: On test generation for transition faults with minimized peak power dissipation. DAC 2004: 504-509
344EEIrith Pomeranz, Sudhakar M. Reddy: Level of Similarity: A Metric for Fault Collapsing. DATE 2004: 56-61
343EEIrith Pomeranz, Srikanth Venkataraman, Sudhakar M. Reddy, Bharath Seshadri: Z-Sets and Z-Detections: Circuit Characteristics that Simplify Fault Diagnosis. DATE 2004: 68-75
342EEIrith Pomeranz, Sudhakar M. Reddy: Reducing Fault Latency in Concurrent On-Line Testing by Using Checking Functions over Internal Lines. DFT 2004: 183-190
341EEIrith Pomeranz, Sudhakar M. Reddy: Concurrent On-Line Testing of Identical Circuits Through Output Comparison Using Non-Identical Input Vectors. DFT 2004: 469-476
340EEIrith Pomeranz, Sudhakar M. Reddy: On Undetectable Faults in Partial Scan Circuits Using Transparent-Scan. ICCD 2004: 82-84
339EEYonsang Cho, Irith Pomeranz, Sudhakar M. Reddy: Test Application Time Reduction for Scan Circuits Using Limited Scan Operations. ISQED 2004: 211-216
338EEHangkyu Lee, Irith Pomeranz, Sudhakar M. Reddy: Scan BIST Targeting Transition Faults Using a Markov Source. ISQED 2004: 497-502
337EEIrith Pomeranz, Srikanth Venkataraman, Sudhakar M. Reddy: Z-DFD: Design-for-Diagnosability Based on the Concept of Z-Detection. ITC 2004: 489-497
336EEIrith Pomeranz, Srikanth Venkataraman, Sudhakar M. Reddy, Enamul Amyeen: Defect Diagnosis Based on Pattern-Dependent Stuck-At Faults. VLSI Design 2004: 475-480
335EEIrith Pomeranz, Sudhakar M. Reddy: On Interconnecting Circuits with Multiple Scan Chains for Improved Test Data Compression. VLSI Design 2004: 741-744
334EEXiaogang Du, Sudhakar M. Reddy, Wu-Tung Cheng, Joseph Rayhawk, Nilanjan Mukherjee: At-Speed Built-in Self-Repair Analyzer for Embedded Word-Oriented Memories. VLSI Design 2004: 895-900
333EEXiaogang Du, Sudhakar M. Reddy, Don E. Ross, Wu-Tung Cheng, Joseph Rayhawk: Memory BIST Using ESP. VTS 2004: 243-248
332EEIrith Pomeranz, Sandip Kundu, Sudhakar M. Reddy: Masking of Unknown Output Values during Output Response Compression byUsing Comparison Units. IEEE Trans. Computers 53(1): 83-88 (2004)
331EEIrith Pomeranz, Sudhakar M. Reddy: A Measure of Quality for n-Detection Test Sets. IEEE Trans. Computers 53(11): 1497-1503 (2004)
330EEIrith Pomeranz, Sudhakar M. Reddy: Static Test Compaction for Full-Scan Circuits Based on Combinational Test Sets and Nonscan Input Sequences and a Lower Bound on the Number of Tests. IEEE Trans. Computers 53(12): 1569-1581 (2004)
329EEIrith Pomeranz, Sudhakar M. Reddy: On Maximizing the Fault Coverage for a Given Test Length Limit in a Synchronous Sequential Circuit. IEEE Trans. Computers 53(9): 1121-1133 (2004)
328EEIrith Pomeranz, Sudhakar M. Reddy: Improving the stuck-at fault coverage of functional test sequences by using limited-scan operations. IEEE Trans. VLSI Syst. 12(7): 780-788 (2004)
327EEIrith Pomeranz, Sudhakar M. Reddy: Vector-restoration-based static compaction using random initial omission. IEEE Trans. on CAD of Integrated Circuits and Systems 23(11): 1587-1592 (2004)
326EEIrith Pomeranz, Sudhakar M. Reddy, Sandip Kundu: On the characterization and efficient computation of hard-to-detect bridging faults. IEEE Trans. on CAD of Integrated Circuits and Systems 23(12): 1640-1649 (2004)
2003
325EEXiaogang Du, Sudhakar M. Reddy, Joseph Rayhawk, Wu-Tung Cheng: Testing Delay Faults in Embedded CAMs. Asian Test Symposium 2003: 378-383
324EEIrith Pomeranz, Sudhakar M. Reddy: Test Data Volume Reduction by Test Data Realignment. Asian Test Symposium 2003: 434-439
323EEIrith Pomeranz, Sudhakar M. Reddy: A DFT Approach for Path Delay Faults in Interconnected Circuits. Asian Test Symposium 2003: 72-77
322EEWei Li, Chaowen Yu, Sudhakar M. Reddy, Irith Pomeranz: A scan BIST generation method using a markov source and partial bit-fixing. DAC 2003: 554-559
321EEIrith Pomeranz, Sudhakar M. Reddy: On test data compression and n-detection test sets. DAC 2003: 748-751
320EEIrith Pomeranz, Sudhakar M. Reddy: A New Approach to Test Generation and Test Compaction for Scan Circuits. DATE 2003: 11000-11005
319EEIrith Pomeranz, Sudhakar M. Reddy, Sandip Kundu: On the Characterization of Hard-to-Detect Bridging Faults. DATE 2003: 11012-11019
318EEIlia Polian, Bernd Becker, Sudhakar M. Reddy: Evolutionary Optimization of Markov Sources for Pseudo Random Scan BIST. DATE 2003: 11184-11185
317EEIrith Pomeranz, Sudhakar M. Reddy: Test Data Compression Based on Output Dependence. DATE 2003: 11186-11187
316EEChen Wang, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski, Jerzy Tyszer: On Compacting Test Response Data Containing Unknown Values. ICCAD 2003: 855-862
315EEIrith Pomeranz, Sudhakar M. Reddy: On Application of Output Masking to Undetectable Faults in Synchronous Sequential Circuits with Design-for-Testability Logic. ICCAD 2003: 867-873
314EEGang Chen, Sudhakar M. Reddy, Irith Pomeranz: Procedures for Identifying Untestable and Redundant Transition Faults in Synchronous Sequential Circuits. ICCD 2003: 36-41
313EEIrith Pomeranz, Sudhakar M. Reddy: Static Test Compaction for Multiple Full-Scan Circuits. ICCD 2003: 393-396
312EEChaowen Yu, Wei Li, Sudhakar M. Reddy, Irith Pomeranz: An Improved Markov Source Design for Scan BIST. IOLTS 2003: 106-110
311EEYu Huang, Wu-Tung Cheng, Chien-Chung Tsai, Nilanjan Mukherjee, Sudhakar M. Reddy: Static Pin Mapping and SOC Test Scheduling for Cores with Multiple Test Sets. ISQED 2003: 99-104
310EEMasao Naruse, Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu: On-chip Compression of Output Responses with Unknown Values Using LFSR Reseeding. ITC 2003: 1060-1068
309EEHuaxing Tang, Sudhakar M. Reddy, Irith Pomeranz: On Reducing Test Data Volume and Test Application Time for Multiple Scan Chain Designs. ITC 2003: 1079-1088
308EEYu Huang, Wu-Tung Cheng, Sudhakar M. Reddy, Cheng-Ju Hsieh, Yu-Ting Hung: Statistical Diagnosis for Intermittent Scan Chain Hold-Time Fault. ITC 2003: 319-328
307EEJanusz Rajski, Jerzy Tyszer, Chen Wang, Sudhakar M. Reddy: Convolutional Compaction of Test Responses. ITC 2003: 745-754
306EEIrith Pomeranz, Sudhakar M. Reddy: Static Test Compaction for Full-Scan Circuits Based on Combinational Test Sets and Non-Scan Sequential Test Sequences. VLSI Design 2003: 335-340
305EEGanesh Venkataraman, Sudhakar M. Reddy, Irith Pomeranz: GALLOP: Genetic Algorithm based Low Power FSM Synthesis by Simultaneous Partitioning and State Assignment. VLSI Design 2003: 533-538
304 Wei Zou, C. N. Chu, Sudhakar M. Reddy, Irith Pomeranz: Optimizing SOC Test Resources using Dual Sequences. VLSI-SOC 2003: 180-185
303EEJanak H. Patel, Steven S. Lumetta, Sudhakar M. Reddy: Application of Saluja-Karpovsky Compactors to Test Responses with Many Unknowns. VTS 2003: 107-112
302EEIrith Pomeranz, Sudhakar M. Reddy: On Maximizing the Fault Coverage for a Given Test Length Limit in a Synchronous Sequential Circuit. VTS 2003: 173-178
301EEWei Zou, Sudhakar M. Reddy, Irith Pomeranz, Yu Huang: SOC Test Scheduling Using Simulated Annealing. VTS 2003: 325-330
300EEIrith Pomeranz, Sudhakar M. Reddy, Yervant Zorian: A Test Interface for Built-In Test of Non-Isolated Scanned Cores. VTS 2003: 371-378
299EESudhakar M. Reddy, Kohei Miyase, Seiji Kajihara, Irith Pomeranz: On test data volume reduction for multiple scan chain designs. ACM Trans. Design Autom. Electr. Syst. 8(4): 460-469 (2003)
298EEIrith Pomeranz, Sudhakar M. Reddy: Test enrichment for path delay faults using multiple sets of target faults. IEEE Trans. on CAD of Integrated Circuits and Systems 22(1): 82-90 (2003)
297EEIrith Pomeranz, Sudhakar M. Reddy: Test data compression based on input-output dependence. IEEE Trans. on CAD of Integrated Circuits and Systems 22(10): 1450-1455 (2003)
296EEIrith Pomeranz, Sudhakar M. Reddy: Transparent scan: a new approach to test generation and test compaction for scan circuits that incorporates limited scan operations. IEEE Trans. on CAD of Integrated Circuits and Systems 22(12): 1663-1670 (2003)
295EERuifeng Guo, Sudhakar M. Reddy, Irith Pomeranz: Reverse-order-restoration-based static test compaction for synchronous sequential circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 22(3): 293-304 (2003)
294EERuifeng Guo, Sudhakar M. Reddy, Irith Pomeranz: PROPTEST: a property-based test generator for synchronous sequential circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 22(8): 1080-1091 (2003)
293EEIrith Pomeranz, Sudhakar M. Reddy: Theorems for identifying undetectable faults in partial-scan circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 22(8): 1092-1097 (2003)
292EEYun Shao, Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara: On Selecting Testable Paths in Scan Designs. J. Electronic Testing 19(4): 447-456 (2003)
291EENadir Z. Basturkmen, Sudhakar M. Reddy, Irith Pomeranz: A Low Power Pseudo-Random BIST Technique. J. Electronic Testing 19(6): 637-644 (2003)
2002
290EEYun Shao, Irith Pomeranz, Sudhakar M. Reddy: On Generating High Quality Tests for Transition Faults. Asian Test Symposium 2002: 1
289EEIrith Pomeranz, Sudhakar M. Reddy: A Partitioning and Storage Based Built-In Test Pattern Generation Method for Delay Faults in Scan Circuits. Asian Test Symposium 2002: 110-115
288EEYu Huang, Sudhakar M. Reddy, Wu-Tung Cheng: Core - Clustering Based SOC Test Scheduling Optimization. Asian Test Symposium 2002: 405-410
287EEIrith Pomeranz, Sudhakar M. Reddy: Improving the Efficiency of Static Compaction Based on Chronological Order Enumeration of Test Sequences. Asian Test Symposium 2002: 61-66
286EESeiji Kajihara, Kenjiro Taniguchi, Kohei Miyase, Irith Pomeranz, Sudhakar M. Reddy: Test Data Compression Using Don?t-Care Identification and Statistical Encoding. Asian Test Symposium 2002: 67-
285EEIrith Pomeranz, Sandip Kundu, Sudhakar M. Reddy: On output response compression in the presence of unknown output values. DAC 2002: 255-258
284EEIrith Pomeranz, Janusz Rajski, Sudhakar M. Reddy: Finding a Common Fault Response for Diagnosis during Silicon Debug. DATE 2002: 1116
283EEIrith Pomeranz, Sudhakar M. Reddy: Test Enrichment for Path Delay Faults Using Multiple Sets of Target Faults. DATE 2002: 722-729
282EEIrith Pomeranz, Sudhakar M. Reddy: Properties of Output Sequences and their Use in Guiding Property-Based Test Generation for Synchronous Sequential Circuits. DELTA 2002: 377-381
281EEKohei Miyase, Seiji Kajihara, Sudhakar M. Reddy: A Method of Static Test Compaction Based on Don't Care Identification. DELTA 2002: 392-395
280EESeiji Kajihara, Kenjiro Taniguchi, Irith Pomeranz, Sudhakar M. Reddy: Test Data Compression Using Don't-Care Identification and Statistical Encoding. DELTA 2002: 413-416
279EEIrith Pomeranz, Sudhakar M. Reddy: On undetectable faults in partial scan circuits. ICCAD 2002: 82-86
278EEChen Wang, Sudhakar M. Reddy, Irith Pomeranz, Xijiang Lin, Janusz Rajski: Conflict driven techniques for improving deterministic test pattern generation. ICCAD 2002: 87-93
277EEKohei Miyase, Seiji Kajihara, Irith Pomeranz, Sudhakar M. Reddy: Don't-Care Identification on Specific Bits of Test Patterns. ICCD 2002: 194-199
276EEIrith Pomeranz, Sudhakar M. Reddy: On the Coverage of Delay Faults in Scan Designs with Multiple Scan Chains. ICCD 2002: 206-209
275EENadir Z. Basturkmen, Sudhakar M. Reddy, Irith Pomeranz: A Low Power Pseudo-Random BIST Technique. ICCD 2002: 468-473
274EENadir Z. Basturkmen, Sudhakar M. Reddy, Irith Pomeranz: A Low Power Pseudo-Random BIST Technique. IOLTW 2002: 140-
273EENadir Z. Basturkmen, Sudhakar M. Reddy, Irith Pomeranz: Pseudo Random Patterns Using Markov Sources for Scan BIST. ITC 2002: 1013-1021
272EEYu Huang, Sudhakar M. Reddy, Wu-Tung Cheng, Paul Reuter, Nilanjan Mukherjee, Chien-Chung Tsai, Omer Samman, Yahya Zaidan: Optimal Core Wrapper Width Selection and SOC Test Scheduling Based on 3-D Bin Packing Algorithm. ITC 2002: 74-82
271EESudhakar M. Reddy, Irith Pomeranz, Huaxing Tang, Seiji Kajihara, Kozo Kinoshita: On Testing of Interconnect Open Defects in Combinational Logic Circuits with Stems of Large Fanout. ITC 2002: 83-89
270EEYu Huang, Nilanjan Mukherjee, Chien-Chung Tsai, Omer Samman, Yahya Zaidan, Yanping Zhang, Wu-Tung Cheng, Sudhakar M. Reddy: Constraint Driven Pin Mapping for Concurrent SOC Testing. VLSI Design 2002: 511-516
269EENadir Z. Basturkmen, Sudhakar M. Reddy, Janusz Rajski: Improved Algorithms for Constructive Multi-Phase Test Point Insertion for Scan Based BIST. VLSI Design 2002: 604-
268EEIrith Pomeranz, Sudhakar M. Reddy: A Partitioning and Storage Based Built-In Test Pattern Generation Method for Scan Circuits. VLSI Design 2002: 677-682
267EEYun Shao, Irith Pomeranz, Sudhakar M. Reddy: Path Delay Fault Test Generation for Standard Scan Designs Using State Tuples. VLSI Design 2002: 767-772
266EESudhakar M. Reddy, Kohei Miyase, Seiji Kajihara, Irith Pomeranz: On Test Data Volume Reduction for Multiple Scan Chain Designs. VTS 2002: 103-110
265EEIrith Pomeranz, Sudhakar M. Reddy: A Storage-Based Built-In Test Pattern Generation Method for Scan Circuits Based on Partitioning and Reduction of a Precomputed Test Set. IEEE Trans. Computers 51(11): 1282-1293 (2002)
264EEIrith Pomeranz, Sudhakar M. Reddy: Built-In Test Sequence Generation for Synchronous Sequential Circuits Based on Loading and Expansion of Input Sequences Using Single and Multiple Fault Detection Times. IEEE Trans. Computers 51(4): 409-419 (2002)
263EEIrith Pomeranz, Sudhakar M. Reddy: Enumeration of Test Sequences in Increasing Chronological Order to Improve the Levels of Compaction Achieved by Vector Omission. IEEE Trans. Computers 51(7): 866-872 (2002)
262EEIrith Pomeranz, Sudhakar M. Reddy: Property-based test generation for scan designs and the effects ofthe test application scheme and scan selection on the number ofdetectable faults. IEEE Trans. on CAD of Integrated Circuits and Systems 21(5): 628-637 (2002)
261EEIrith Pomeranz, Sudhakar M. Reddy: Test compaction for at-speed testing of scan circuits based onnonscan test. sequences and removal of transfer sequences. IEEE Trans. on CAD of Integrated Circuits and Systems 21(6): 706-714 (2002)
260EEIrith Pomeranz, Sudhakar M. Reddy: n-pass n-detection fault simulation and its applications. IEEE Trans. on CAD of Integrated Circuits and Systems 21(8): 980-986 (2002)
259EEYu Huang, Chien-Chung Tsai, Nilanjan Mukherjee, Omer Samman, Wu-Tung Cheng, Sudhakar M. Reddy: Synthesis of Scan Chains for Netlist Descriptions at RT-Level. J. Electronic Testing 18(2): 189-201 (2002)
258EEYu Huang, Wu-Tung Cheng, Chien-Chung Tsai, Nilanjan Mukherjee, Omer Samman, Yahya Zaidan, Sudhakar M. Reddy: On Concurrent Test of Core-Based SOC Design. J. Electronic Testing 18(4-5): 401-414 (2002)
2001
257EEIrith Pomeranz, Sudhakar M. Reddy: ITEM: an iterative improvement test generation procedure for synchronous sequential circuits. ACM Great Lakes Symposium on VLSI 2001: 13-18
256EEIrith Pomeranz, Sudhakar M. Reddy: A Postprocessing Procedure to Reduce the Number of Different Test Lengths in a Test Set for Scan Circuits. Asian Test Symposium 2001: 131-136
255EEYun Shao, Sudhakar M. Reddy, Seiji Kajihara, Irith Pomeranz: An Efficient Method to Identify Untestable Path Delay Faults. Asian Test Symposium 2001: 233-238
254EEYu Huang, Wu-Tung Cheng, Chien-Chung Tsai, Nilanjan Mukherjee, Omer Samman, Yahya Zaidan, Sudhakar M. Reddy: Resource Allocation and Test Scheduling for Concurrent Test of Core-Based SoC D. Asian Test Symposium 2001: 265-
253EEIrith Pomeranz, Sudhakar M. Reddy, Xijiang Lin: Experimental Results of Forward-Looking Reverse Order Fault Simulation on Industrial Circuits with Scan. Asian Test Symposium 2001: 467
252EERuifeng Guo, Sudhakar M. Reddy, Irith Pomeranz: On Improving a Fault Simulation Based Test Generator for Synchronous Sequential Circuits. Asian Test Symposium 2001: 82-
251EEIrith Pomeranz, Sudhakar M. Reddy: An Approach to Test Compaction for Scan Circuits that Enhances At-Speed Testing. DAC 2001: 156-161
250EEIrith Pomeranz, Sudhakar M. Reddy: Sequence reordering to improve the levels of compaction achievable by static compaction procedures. DATE 2001: 214-218
249EEIrith Pomeranz, Sudhakar M. Reddy: Definitions of the numbers of detections of target faults and their effectiveness in guiding test generation for high defect coverage. DATE 2001: 504-508
248EEChen Wang, Irith Pomeranz, Sudhakar M. Reddy: REDI: An Efficient Fault Oriented Procedure to Identify Redundant Faults in Combinational Logic Circuits. ICCAD 2001: 370-374
247 Irith Pomeranz, Sudhakar M. Reddy: COREL: A Dynamic Compaction Procedure for Synchronous Sequential Circuits with Repetition and Local Static Compaction. ICCD 2001: 142-147
246 Irith Pomeranz, Sudhakar M. Reddy: A Partitioning and Storage Based Built-in Test Pattern Generation Method for Synchronous Sequential Circuits. ICCD 2001: 148-153
245 Xijiang Lin, Janusz Rajski, Irith Pomeranz, Sudhakar M. Reddy: On static test compaction and test pattern ordering for scan designs. ITC 2001: 1088-1097
244 Irith Pomeranz, Sudhakar M. Reddy: A method to enhance the fault coverage obtained by output response comparison of identical circuits. ITC 2001: 196-203
243 Irith Pomeranz, Sudhakar M. Reddy: On improving the stuck-at fault coverage of functional test sequences by using limited-scan operations. ITC 2001: 211-220
242 Yu Huang, Chien-Chung Tsai, Neelanjan Mukherjee, Omer Samman, Dan Devries, Wu-Tung Cheng, Sudhakar M. Reddy: On RTL scan design. ITC 2001: 728-737
241EERuifeng Guo, Irith Pomeranz, Sudhakar M. Reddy: On Improving Static Test Compaction for Sequential Circuits. VLSI Design 2001: 111-116
240EEIrith Pomeranz, Sudhakar M. Reddy: On the Use of Fault Dominance in n-Detection Test Generation. VTS 2001: 352-357
239EEIrith Pomeranz, Sudhakar M. Reddy: A built-in self-test method for diagnosis of synchronous sequential circuits. IEEE Trans. VLSI Syst. 9(2): 290-296 (2001)
238EEIrith Pomeranz, Sudhakar M. Reddy: Resynthesis of combinational logic circuits for improved path delay fault testability using comparison units. IEEE Trans. VLSI Syst. 9(5): 679-689 (2001)
237EEIrith Pomeranz, Sudhakar M. Reddy: Forward-looking fault simulation for improved static compaction. IEEE Trans. on CAD of Integrated Circuits and Systems 20(10): 1262-1265 (2001)
236EEIrith Pomeranz, Sudhakar M. Reddy: Vector replacement to improve static-test compaction forsynchronous sequential circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 20(2): 336-342 (2001)
235EEIrith Pomeranz, Sudhakar M. Reddy: On diagnosis and diagnostic test generation for pattern-dependenttransition faults. IEEE Trans. on CAD of Integrated Circuits and Systems 20(6): 791-800 (2001)
234EEIrith Pomeranz, Sudhakar M. Reddy: Design-for-testability to achieve complete coverage of delay faults in standard full scan circuits. Journal of Systems Architecture 47(3-4): 357-373 (2001)
2000
233EEIrith Pomeranz, Sudhakar M. Reddy: On the feasibility of fault simulation using partial circuit descriptions. Asian Test Symposium 2000: 108-113
232EESeiji Kajihara, Takashi Shimono, Irith Pomeranz, Sudhakar M. Reddy: Enhanced untestable path analysis using edge graphs. Asian Test Symposium 2000: 139-144
231EEIrith Pomeranz, Sudhakar M. Reddy: Reducing test application time for full scan circuits by the addition of transfer sequences. Asian Test Symposium 2000: 317-322
230EEShi-Yu Huang, Sudhakar M. Reddy: High Performance/Delay Testing. Asian Test Symposium 2000: 490-
229EEIrith Pomeranz, Sudhakar M. Reddy: On diagnosis of pattern-dependent delay faults. DAC 2000: 59-62
228EEIrith Pomeranz, Sudhakar M. Reddy: Built-In Generation of Weighted Test Sequences for Synchronous Sequential Circuits. DATE 2000: 298-304
227EEIrith Pomeranz, Sudhakar M. Reddy: Functional Test Generation for Full Scan Circuits. DATE 2000: 396-
226EEIrith Pomeranz, Sudhakar M. Reddy: Test-Point Insertion to Enhance Test Compaction for Scan Designs. DSN 2000: 375-381
225 Yu Huang, Irith Pomeranz, Sudhakar M. Reddy, Janusz Rajski: Improving the Proportion of At-Speed Tests in Scan BIST. ICCAD 2000: 459-463
224 Irith Pomeranz, Sudhakar M. Reddy: Simulation Based Test Generation for Scan Designs. ICCAD 2000: 544-549
223EEIrith Pomeranz, Sudhakar M. Reddy: Sensitivity Levels of Test Patterns and Their Usefulness in Simulation-Based Test Generation. ICCD 2000: 389-394
222EEIrith Pomeranz, Sudhakar M. Reddy: On Test Application Time and Defect Detection Capabilities of Test Sets for Scan Designs. ICCD 2000: 395-
221 Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara, Atsushi Murakami, Sadami Takeoka, Mitsuyasu Ohta: On validating data hold times for flip-flops in sequential circuits. ITC 2000: 317-325
220 Atsushi Murakami, Seiji Kajihara, Tsutomu Sasao, Irith Pomeranz, Sudhakar M. Reddy: Selection of potentially testable path delay faults for test generation. ITC 2000: 376-384
219EEIrith Pomeranz, Sudhakar M. Reddy: Fault diagnosis based on parameters of output responses. PRDC 2000: 139-147
218EEHideyuki Ichihara, Kozo Kinoshita, Irith Pomeranz, Sudhakar M. Reddy: Test Transformation to Improve Compaction by Statistical Encoding. VLSI Design 2000: 294-299
217EEIrith Pomeranz, Sudhakar M. Reddy: On Synchronizing Sequences and Unspecified Values in Output Responses of Synchronous Sequential Circuits. VLSI Design 2000: 392-397
216EEXijiang Lin, Wu-Tung Cheng, Irith Pomeranz, Sudhakar M. Reddy: SIFAR: Static Test Compaction for Synchronous Sequential Circuits Based on Single Fault Restoration. VTS 2000: 205-212
215EEIrith Pomeranz, Sudhakar M. Reddy: On Finding a Minimal Functional Description of a Finite-State Machine for Test Generation for Adjacent Machines. IEEE Trans. Computers 49(1): 88-94 (2000)
214EEIrith Pomeranz, Sudhakar M. Reddy: On the Use of Fully Specified Initial States for Testing of Synchronous Sequential Circuits. IEEE Trans. Computers 49(2): 175-181 (2000)
213EEIrith Pomeranz, Sudhakar M. Reddy: Procedures for Static Compaction of Test Sequences for Synchronous Sequential Circuits. IEEE Trans. Computers 49(6): 596-607 (2000)
212EEIrith Pomeranz, Sudhakar M. Reddy: On n-detection test sets and variable n-detection test sets fortransition faults. IEEE Trans. on CAD of Integrated Circuits and Systems 19(3): 372-383 (2000)
211EEIrith Pomeranz, Sudhakar M. Reddy: A diagnostic test generation procedure based on test elimination byvector omission for synchronous sequential circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 19(5): 589-600 (2000)
210EEIrith Pomeranz, Sudhakar M. Reddy: On synchronizable circuits and their synchronizing sequences. IEEE Trans. on CAD of Integrated Circuits and Systems 19(9): 1086-1092 (2000)
209EEIrith Pomeranz, Sudhakar M. Reddy: Static Test Compaction for Scan-Based Designs to Reduce Test Application Time. J. Electronic Testing 16(5): 541-552 (2000)
1999
208EEIrith Pomeranz, Sudhakar M. Reddy: Vector-Based Functional Fault Models for Delay Faults. Asian Test Symposium 1999: 41-46
207EEIrith Pomeranz, Sudhakar M. Reddy: Pattern Sensitivity: A Property to Guide Test Generation for Combinational Circuits. Asian Test Symposium 1999: 75-80
206EERuifeng Guo, Sudhakar M. Reddy, Irith Pomeranz: Proptest: A Property Based Test Pattern Generator for Sequential Circuits Using Test Compaction. DAC 1999: 653-659
205EEIrith Pomeranz, Sudhakar M. Reddy: Built-In Test Sequence Generation for Synchronous Sequential Circuits Based on Loading and Expansion of Test Subsequences. DAC 1999: 754-759
204EEXijiang Lin, Irith Pomeranz, Sudhakar M. Reddy: Full Scan Fault Coverage With Partial Scan. DATE 1999: 468-472
203EEIrith Pomeranz, Sudhakar M. Reddy: PASTA: Partial Scan to Enhance Test Compaction. Great Lakes Symposium on VLSI 1999: 4-7
202EEXijiang Lin, Irith Pomeranz, Sudhakar M. Reddy: Techniques for improving the efficiency of sequential circuit test generation. ICCAD 1999: 147-151
201EEIrith Pomeranz, Sudhakar M. Reddy: An approach for improving the levels of compaction achieved by vector omission. ICCAD 1999: 463-466
200EEIrith Pomeranz, Sudhakar M. Reddy: Fault Simulation Based Test Generation for Combinational Circuits Using Dynamically Selected Sub-Circuits. ICCD 1999: 412-417
199 Yun Shao, Ruifeng Guo, Sudhakar M. Reddy, Irith Pomeranz: The effects of test compaction on fault diagnosis. ITC 1999: 1083-1089
198 Sudhakar M. Reddy: Application of Tools Developed at the University of Iowa to ITC Benchmarks. ITC 1999: 1128
197 Sitaran Yadavalli, Sudhakar M. Reddy: SymSim: symbolic fault simulation of data-flow data-path designs at the Register-Transfer level. ITC 1999: 606-615
196 Irith Pomeranz, Sudhakar M. Reddy: On achieving complete coverage of delay faults in full scan circuits using locally available lines. ITC 1999: 923-931
195EEIrith Pomeranz, Sudhakar M. Reddy: VERSE: A Vector Replacement Procedure for Improving Test Compaction in Synchronous Sequential Circuits. VLSI Design 1999: 250-255
194EEIrith Pomeranz, Sudhakar M. Reddy: A Flexible Path Selection Procedure for Path Delay Fault Testing. VTS 1999: 152-159
193EEIrith Pomeranz, Sudhakar M. Reddy: On n-Detection Test Sets and Variable n-Detection Test Sets for Transition Faults. VTS 1999: 173-181
192EERuifeng Guo, Irith Pomeranz, Sudhakar M. Reddy: A Fault Simulation Based Test Pattern Generator for Synchronous Sequential Circuits. VTS 1999: 260-267
191EESudhakar M. Reddy, Irith Pomeranz, Nadir Z. Basturkmen, Xijiang Lin: Procedures for Identifying Undetectable and Redundant Faults In Synchronous Sequential Circuits. VTS 1999: 275-283
190 Irith Pomeranz, Sudhakar M. Reddy: A Cone-Based Genetic Optimization Procedure for Test Generation and Its Application to n-Detections in Combinational Circuits. IEEE Trans. Computers 48(10): 1145-1152 (1999)
189EEUwe Sparmann, H. Mueller, Sudhakar M. Reddy: Universal delay test sets for logic networks. IEEE Trans. VLSI Syst. 7(2): 156-166 (1999)
188EEIrith Pomeranz, Sudhakar M. Reddy: A comment on "Improving a nonenumerative method to estimate path delay fault coverage". IEEE Trans. on CAD of Integrated Circuits and Systems 18(5): 665-666 (1999)
187EEIrith Pomeranz, Sudhakar M. Reddy, Ruifeng Guo: Static test compaction for synchronous sequential circuits based on vector restoration. IEEE Trans. on CAD of Integrated Circuits and Systems 18(7): 1040-1049 (1999)
1998
186EEIrith Pomeranz, Sudhakar M. Reddy: Static Test Compaction for Scan-Based Designs to Reduce Test Application Time. Asian Test Symposium 1998: 198-203
185EEIrith Pomeranz, Sudhakar M. Reddy: Test Generation for Synchronous Sequential Circuits to Reduce Storage Requirements. Asian Test Symposium 1998: 446-451
184EERuifeng Guo, Irith Pomeranz, Sudhakar M. Reddy: On Speeding-Up Vector Restoration Based Static Compaction of Test Sequences for Sequential Circuits . Asian Test Symposium 1998: 467-471
183EERuifeng Guo, Irith Pomeranz, Sudhakar M. Reddy: Procedures for Static Compaction of Test Sequences for Synchronous Sequential Circuits Based on Vector Restoration. DATE 1998: 583-
182EEIrith Pomeranz, Sudhakar M. Reddy: A Synthesis Procedure for Flexible Logic Functions. DATE 1998: 973-974
181EEIrith Pomeranz, Sudhakar M. Reddy: Design-for-Testability for Synchronous Sequential Circuits using Locally Available Lines. DATE 1998: 983-984
180 Irith Pomeranz, Sudhakar M. Reddy: A Generalized Test Generation Procedure for Path Delay Faults. FTCS 1998: 274-283
179EEIrith Pomeranz, Sudhakar M. Reddy: Test Compaction for Synchronous Sequential Circuits by Test Sequence Recycling. Great Lakes Symposium on VLSI 1998: 216-221
178EEIrith Pomeranz, Sudhakar M. Reddy: A diagnostic test generation procedure for synchronous sequential circuits based on test elimination. ITC 1998: 1074-1083
177EEIrith Pomeranz, Sudhakar M. Reddy: On Test Compaction Objectives for Combinational and Sequential Circuits. VLSI Design 1998: 279-284
176EEXijiang Lin, Irith Pomeranz, Sudhakar M. Reddy: MIX: A Test Generation System for Synchronous Sequential Circuits. VLSI Design 1998: 456-463
175EEIrith Pomeranz, Sudhakar M. Reddy: On Synchronizing Sequences and Test Sequence Partitioning. VTS 1998: 158-167
174EEXijiang Lin, Irith Pomeranz, Sudhakar M. Reddy: On Removing Redundant Faults in Synchronous Sequential Circuits. VTS 1998: 168-175
173EEIrith Pomeranz, Sudhakar M. Reddy: Stuck-At Tuple-Detection: A Fault Model Based on Stuck-At Faults for Improved Defect Coverage. VTS 1998: 289-295
172EEIrith Pomeranz, Sudhakar M. Reddy: Functional test generation for delay faults in combinational circuits. ACM Trans. Design Autom. Electr. Syst. 3(2): 231-248 (1998)
171 Irith Pomeranz, Sudhakar M. Reddy: Location of Stuck-At Faults and Bridging Faults Based on Circuit Partitioning. IEEE Trans. Computers 47(10): 1124-1135 (1998)
170EEIrith Pomeranz, Sudhakar M. Reddy: On methods to match a test pattern generator to a circuit-under-test. IEEE Trans. VLSI Syst. 6(3): 432-444 (1998)
169EEIrith Pomeranz, Sudhakar M. Reddy: Test sequences to achieve high defect coverage for synchronous sequential circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 17(10): 1017-1029 (1998)
168EEVinay Dabholkar, Sreejit Chakravarty, Irith Pomeranz, Sudhakar M. Reddy: Techniques for minimizing power dissipation in scan and combinational circuits during test application. IEEE Trans. on CAD of Integrated Circuits and Systems 17(12): 1325-1333 (1998)
167EEIrith Pomeranz, Sudhakar M. Reddy: Low-complexity fault simulation under the multiple observation time and the restricted multiple observation time testing approaches. IEEE Trans. on CAD of Integrated Circuits and Systems 17(3): 269-278 (1998)
166EEIrith Pomeranz, Sudhakar M. Reddy: Design-for-testability for path delay faults in large combinational circuits using test points. IEEE Trans. on CAD of Integrated Circuits and Systems 17(4): 333-343 (1998)
165 Doowon Paik, Sudhakar M. Reddy, Sartaj Sahni: Vertex Splitting in Dags and Applications to Partial Scan Designs and Lossy Circuits. Int. J. Found. Comput. Sci. 9(4): 377-398 (1998)
164EEIrith Pomeranz, Sudhakar M. Reddy: Delay fault models for VLSI circuits1. Integration 26(1-2): 21-40 (1998)
1997
163EEIrith Pomeranz, Sudhakar M. Reddy: On the Compaction of Test Sets Produced by Genetic Optimization. Asian Test Symposium 1997: 4-9
162EEIrith Pomeranz, Sudhakar M. Reddy: TEMPLATES: A Test Generation Procedure for Synchronous Sequential Circuits. Asian Test Symposium 1997: 74-
161EEIrith Pomeranz, Sudhakar M. Reddy: Fault Simulation under the Multiple Observation Time Approach using Backward Implications. DAC 1997: 608-613
160EEIrith Pomeranz, Sudhakar M. Reddy: On improving genetic optimization based test generation. ED&TC 1997: 506-511
159EEIrith Pomeranz, Sudhakar M. Reddy: On the use of reset to increase the testability of interconnected finite-state machines. ED&TC 1997: 554-559
158 Irith Pomeranz, Sudhakar M. Reddy: ACTIV-LOCSTEP: A Test Generation Procedure Based on Logic Simulation and Fault Activation. FTCS 1997: 144-151
157EEIrith Pomeranz, Sudhakar M. Reddy: On Generating Test Sets that Remain Valid in the Presence of Undetected Faults. Great Lakes Symposium on VLSI 1997: 20-25
156EEIrith Pomeranz, Sudhakar M. Reddy: Built-in test generation for synchronous sequential circuits. ICCAD 1997: 421-426
155 Irith Pomeranz, Sudhakar M. Reddy: Vector Restoration Based Static Compaction of Test Sequences for Synchronous Sequential Circuits. ICCD 1997: 360-365
154EEBernd Becker, Rolf Drechsler, Sudhakar M. Reddy: (Quasi-) Linear Path Delay Fault Tests for Adders. VLSI Design 1997: 101-105
153EEIrith Pomeranz, Sudhakar M. Reddy: On the Detection of Reset Faults in Synchronous Sequential Circuits. VLSI Design 1997: 470-474
152EEIrith Pomeranz, Sudhakar M. Reddy: On Full Reset as a Design-For-Testability Technique. VLSI Design 1997: 534-536
151EESeiji Kajihara, Kozo Kinoshita, Irith Pomeranz, Sudhakar M. Reddy: A Method for Identifying Robust Dependent and Functionally Unsensitizable Paths. VLSI Design 1997: 82-87
150EEIrith Pomeranz, Sudhakar M. Reddy: EXTEST: a method to extend test sequences of synchronous sequential circuits to increase the fault coverage. VTS 1997: 329-335
149EEIrith Pomeranz, Sudhakar M. Reddy: On n-detection test sequences for synchronous sequential circuits343. VTS 1997: 336-343
148 Irith Pomeranz, Sudhakar M. Reddy: On Dictionary-Based Fault Location in Digital Logic Circuits. IEEE Trans. Computers 46(1): 48-59 (1997)
147 Irith Pomeranz, Sudhakar M. Reddy: Test Generation for Multiple State-Table Faults in Finite-State Machines. IEEE Trans. Computers 46(7): 783-794 (1997)
146EEAnkan K. Pramanick, Sudhakar M. Reddy: On the fault coverage of gate delay fault detecting tests. IEEE Trans. on CAD of Integrated Circuits and Systems 16(1): 78-94 (1997)
145EEIrith Pomeranz, Sudhakar M. Reddy: On error correction in macro-based circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 16(10): 1088-1100 (1997)
144EEIrith Pomeranz, Sudhakar M. Reddy: LOCSTEP: a logic-simulation-based test generation procedure. IEEE Trans. on CAD of Integrated Circuits and Systems 16(5): 544-554 (1997)
143EESudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara: Compact test sets for high defect coverage. IEEE Trans. on CAD of Integrated Circuits and Systems 16(8): 923-930 (1997)
1996
142EEUwe Sparmann, H. Mueller, Sudhakar M. Reddy: Minimal Delay Test Sets for Unate Gate Networks. Asian Test Symposium 1996: 155-
141EEIrith Pomeranz, Sudhakar M. Reddy: On Test Generation for Interconnected Finite-State Machines: The Input Sequence Propagation Problem. Asian Test Symposium 1996: 16-21
140EESudhakar M. Reddy: "Challenges in Testing". Asian Test Symposium 1996: 2-
139EEIrith Pomeranz, Sudhakar M. Reddy: Low-Complexity Fault Diagnosis Under the Multiple Observation Time Testing Approach. Asian Test Symposium 1996: 226-231
138EEIrith Pomeranz, Sudhakar M. Reddy: On Static Compaction of Test Sequences for Synchronous Sequential Circuits. DAC 1996: 215-220
137 Irith Pomeranz, Sudhakar M. Reddy: Dynamic Test Compaction for Synchronous Sequential Circuits using Static Compaction Techniques. FTCS 1996: 53-61
136EEIrith Pomeranz, Sudhakar M. Reddy, Janak H. Patel: On Double Transition Faults as a Delay Fault Model. Great Lakes Symposium on VLSI 1996: 282-287
135 Volker Strumpen, Balkrishna Ramkumar, Thomas L. Casavant, Sudhakar M. Reddy: Perspectives for High Performance Computing in Workstation Networks. HPCN Europe 1996: 880-889
134EEIrith Pomeranz, Sudhakar M. Reddy: Fault Location based on Circuit Partitioning. ICCD 1996: 154-
133EEIrith Pomeranz, Sudhakar M. Reddy: Fault Location Based on Circuit Partitioning. ICCD 1996: 242-247
132 Harry Hengster, Uwe Sparmann, Bernd Becker, Sudhakar M. Reddy: Local Transformations and Robust Dependent Path Delay. ITC 1996: 347-356
131 Irith Pomeranz, Sudhakar M. Reddy: On Cancelling the Effects of Logic Sharing for Improved Path Delay Fault Testability. ITC 1996: 357-366
130EEIrith Pomeranz, Sudhakar M. Reddy: On Finding Functionally Identical and Functionally Opposite Lines in Combinational Logic Circuits. VLSI Design 1996: 254-259
129EESudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara: On the effects of test compaction on defect coverage. VTS 1996: 430-437
128EESandeep K. Gupta, Slawomir Pilarski, Sudhakar M. Reddy, Jacob Savir, Prab Varma: Delay Fault Testing: How Robust are Our Models? VTS 1996: 502-503
127 Irith Pomeranz, Sudhakar M. Reddy: On Removing Redundancies from Synchronous Sequential Circuits with Synchronizing Sequences. IEEE Trans. Computers 45(1): 20-32 (1996)
126 Irith Pomeranz, Sudhakar M. Reddy: On the Number of Tests to Detect All Path Delay Faults in Combinational Logic Circuits. IEEE Trans. Computers 45(1): 50-62 (1996)
125EEUwe Sparmann, Sudhakar M. Reddy: On the effectiveness of residue code checking for parallel two's complement multipliers. IEEE Trans. VLSI Syst. 4(2): 227-239 (1996)
124EEWolfgang Kunz, Dhiraj K. Pradhan, Sudhakar M. Reddy: A novel framework for logic verification in a synthesis environment. IEEE Trans. on CAD of Integrated Circuits and Systems 15(1): 20-32 (1996)
1995
123EEIrith Pomeranz, Sudhakar M. Reddy: Static compaction for two-pattern test sets. Asian Test Symposium 1995: 222-228
122EEUwe Sparmann, D. Luxenburger, Kwang-Ting Cheng, Sudhakar M. Reddy: Fast Identification of Robust Dependent Path Delay Faults. DAC 1995: 119-125
121EEIrith Pomeranz, Sudhakar M. Reddy: On Synthesis-for-Testability of Combinational Logic Circuits. DAC 1995: 126-132
120EEIrith Pomeranz, Sudhakar M. Reddy: On generating compact test sequences for synchronous sequential circuits. EURO-DAC 1995: 105-110
119 Irith Pomeranz, Sudhakar M. Reddy: LOCSTEP: A Logic Simulation Based Test Generation Procedure. FTCS 1995: 110-119
118EEIrith Pomeranz, Sudhakar M. Reddy: Functional test generation for delay faults in combinational circuits. ICCAD 1995: 687-694
117EEIrith Pomeranz, Sudhakar M. Reddy: Test generation for multiple state-table faults in finite-state machines. ICCD 1995: 292-
116EESudhakar M. Reddy: Testing-what's missing? An incomplete list of challenges. ICCD 1995: 426-
115 Irith Pomeranz, Sudhakar M. Reddy: Low-Complexity Fault Simulation under the Multiplie Observation Time Testing Approach. ITC 1995: 272-281
114EESitaran Yadavalli, Irith Pomeranz, Sudhakar M. Reddy: MUSTC-Testing: Multi-Stage-Combinational Test scheduling at the Register-Transfer Level. VLSI Design 1995: 110-115
113EERemata S. Reddy, Irith Pomeranz, Sudhakar M. Reddy, Seiji Kajihara: Compact test generation for bridging faults under I/sub DDQ/ testing. VTS 1995: 310-316
112 Irith Pomeranz, Sudhakar M. Reddy: Aliasing Computation Using Fault Simulation with Fault Dropping. IEEE Trans. Computers 44(1): 139-144 (1995)
111 Irith Pomeranz, Sudhakar M. Reddy: On Fault Simulation for Synchronous Sequential Circuits. IEEE Trans. Computers 44(2): 335-340 (1995)
110 Irith Pomeranz, Sudhakar M. Reddy: INCREDYBLE: A New Search Strategy for Design Automation Problems with Applications to Testing. IEEE Trans. Computers 44(6): 792-804 (1995)
109EESeiji Kajihara, Irith Pomeranz, Kozo Kinoshita, Sudhakar M. Reddy: Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 14(12): 1496-1504 (1995)
108EEIrith Pomeranz, Sudhakar M. Reddy, Prasanti Uppaluri: NEST: a nonenumerative test generation method for path delay faults in combinational circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 14(12): 1505-1515 (1995)
107EEIrith Pomeranz, Sudhakar M. Reddy: On correction of multiple design errors. IEEE Trans. on CAD of Integrated Circuits and Systems 14(2): 255-264 (1995)
106EEAnkan K. Pramanick, Sudhakar M. Reddy: Efficient multiple path propagating tests for delay faults. J. Electronic Testing 7(3): 157-172 (1995)
1994
105EEIrith Pomeranz, Sudhakar M. Reddy: Design-for-Testability for Path Delay Faults in Large Combinatorial Circuits Using Test-Points. DAC 1994: 358-364
104EEIrith Pomeranz, Sudhakar M. Reddy: On Improving Fault Diagnosis for Synchronous Sequential Circuits. DAC 1994: 504-509
103 Sudhakar M. Reddy, Irith Pomeranz, Rahul Jain: On Codeword Testing of Two-Rail and Parity TSC Checkers. FTCS 1994: 116-125
102 Uwe Sparmann, Sudhakar M. Reddy: On the Effectiveness of Residue Code Checking for Parallel Two's Complement Multipliers. FTCS 1994: 219-228
101 Prasanti Uppaluri, Irith Pomeranz, Sudhakar M. Reddy: Test Pattern Generation for Path Delay Faults in Synchronous Sequential Circuits Using Multiple Fast Clocks and Multiple Observations Times. FTCS 1994: 456-465
100EEIrith Pomeranz, Sudhakar M. Reddy: On testing delay faults in macro-based combinational circuits. ICCAD 1994: 332-339
99EEIrith Pomeranz, Sudhakar M. Reddy: On error correction in macro-based circuits. ICCAD 1994: 568-575
98 Irith Pomeranz, Sudhakar M. Reddy: On Achieving Complete Testability of Synchronous Sequential Circuits with Synchronizing Sequences. ITC 1994: 1007-1016
97 Thomas Burch, J. Hartmann, Günter Hotz, M. Krallmann, U. Nikolaus, Sudhakar M. Reddy, Uwe Sparmann: A Hierarchical Environment for Interactive Test Engineering. ITC 1994: 461-470
96 Irith Pomeranz, Sudhakar M. Reddy: On Determining Symmetries in Inputs of Logic Circuits. VLSI Design 1994: 255-260
95 Irith Pomeranz, Sudhakar M. Reddy: Application of Homing Sequences to Synchronous Sequential Circuit Testing. IEEE Trans. Computers 43(5): 569-580 (1994)
94 Doowon Paik, Sudhakar M. Reddy, Sartaj Sahni: Deleting Vertices to Bound Path Length. IEEE Trans. Computers 43(9): 1091-1096 (1994)
93 Irith Pomeranz, Sudhakar M. Reddy: On the Role of Hardware Reset in Synchronous Sequential Circuit Test Generation. IEEE Trans. Computers 43(9): 1100-1105 (1994)
92EEIrith Pomeranz, Sudhakar M. Reddy: On determining symmetries in inputs of logic circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 13(11): 1428-1434 (1994)
91EEIrith Pomeranz, Sudhakar M. Reddy: An efficient nonenumerative method to estimate the path delay fault coverage in combinational circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 13(2): 240-250 (1994)
90EEIrith Pomeranz, Sudhakar M. Reddy: SPADES-ACE: a simulator for path delay faults in sequential circuits with extensions to arbitrary clocking schemes. IEEE Trans. on CAD of Integrated Circuits and Systems 13(2): 251-263 (1994)
89EEIrith Pomeranz, Sudhakar M. Reddy: On achieving complete fault coverage for sequential machines. IEEE Trans. on CAD of Integrated Circuits and Systems 13(3): 378-386 (1994)
1993
88EESeiji Kajihara, Irith Pomeranz, Kozo Kinoshita, Sudhakar M. Reddy: Cost-Effective Generation of Minimal Test Sets for Stuck-at Faults in Combinational Logic Circuits. DAC 1993: 102-106
87EEIrith Pomeranz, Sudhakar M. Reddy, Prasanti Uppaluri: NEST: A Non-Enumerative Test Generation Method for Path Delay Faults in Combinational Circuits. DAC 1993: 439-445
86EEIrith Pomeranz, Sudhakar M. Reddy: INCREDYBLE-TG: INCREmental DYnamic test generation based on LEarning. DAC 1993: 80-85
85 Irith Pomeranz, Sudhakar M. Reddy: EXOP (Extended Operation): A New Logical Fault Model for Digital Circuits. FTCS 1993: 166-175
84 Irith Pomeranz, Sudhakar M. Reddy, Janak H. Patel: Theory and Practice of Sequential Machine Testing and Testability. FTCS 1993: 330-337
83 Irith Pomeranz, Sudhakar M. Reddy: Design and Synthesis for Testability of Synchronous Sequential Circuits Based on Strong-Connectivity. FTCS 1993: 492-501
82EEIrith Pomeranz, Sudhakar M. Reddy: Test generation for path delay faults based on learning. ICCAD 1993: 428-435
81EEIrith Pomeranz, Sudhakar M. Reddy: On diagnosis and correction of design errors. ICCAD 1993: 500-507
80 Irith Pomeranz, Sudhakar M. Reddy: A Learning-Based Method to Match a Test Pattern Generator to a Circuit-Under-Test. ITC 1993: 998-1007
79 Khushro Shahookar, W. Khamisani, Pinaki Mazumder, Sudhakar M. Reddy: Genetic Beam Search for Gate Matrix Layout. VLSI Design 1993: 208-213
78 Ankan K. Pramanick, Sudhakar M. Reddy: On Unified Delay Fault Testing. VLSI Design 1993: 265-268
77 Doowon Paik, Sudhakar M. Reddy, Sartaj Sahni: Heuristics for the Placement of Flip-Flops in Partial Scan Designs and the Placement of Signal Boosters in Lossy Circuits. VLSI Design 1993: 45-50
76 Irith Pomeranz, Sudhakar M. Reddy: On the Generation of Weights for Weighted Pseudo Random Testing. VLSI Design 1993: 69-72
75 Irith Pomeranz, Sudhakar M. Reddy: Testing of Fault-Tolerant Hardware Through Partial Control of Inputs. IEEE Trans. Computers 42(10): 1267-1271 (1993)
74 Irith Pomeranz, Sudhakar M. Reddy: Classification of Faults in Synchronous Sequential Circuits. IEEE Trans. Computers 42(9): 1066-1077 (1993)
73EEIrith Pomeranz, Lakshmi N. Reddy, Sudhakar M. Reddy: COMPACTEST: a method to generate compact test sets for combinational circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 12(7): 1040-1049 (1993)
72EEIrith Pomeranz, Sudhakar M. Reddy: 3-weight pseudo-random test generation based on a deterministic test set for combinational and sequential circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 12(7): 1050-1058 (1993)
1992
71EEIrith Pomeranz, Sudhakar M. Reddy: At-Speed Delay Testing of Synchronous Sequential Circuits. DAC 1992: 177-181
70EEDong-Ho Lee, Sudhakar M. Reddy: On Efficient Concurrent Fault Simulation for Synchronous Sequential Circuits. DAC 1992: 327-331
69 Irith Pomeranz, Sudhakar M. Reddy: A Divide-And-Conquer Approach to Test Generation for Large Synchronous Sequential Circuits. FTCS 1992: 230-237
68 Niraj K. Jha, Irith Pomeranz, Sudhakar M. Reddy, Robert J. Miller: Synthesis of Multi-Level Combinational Circuits for Complete Robust Path Delay Fault Testability. FTCS 1992: 280-287
67EEIrith Pomeranz, Sudhakar M. Reddy: On the generation of small dictionaries for fault location. ICCAD 1992: 272-279
66EEIrith Pomeranz, Sudhakar M. Reddy: An efficient non-enumerative method to estimate path delay fault coverage. ICCAD 1992: 560-567
65EELakshmi N. Reddy, Irith Pomeranz, Sudhakar M. Reddy: COMPACTEST-II: a method to generate compact two-pattern test sets for combinational logic circuits. ICCAD 1992: 568-574
64 Irith Pomeranz, Sudhakar M. Reddy: The Multiple Observation Time Test Strategy. IEEE Trans. Computers 41(5): 627-637 (1992)
63EEDong Sam Ha, Sudhakar M. Reddy: On the design of random pattern testable PLA based on weighted random pattern testing. J. Electronic Testing 3(2): 149-157 (1992)
1991
62EEIrith Pomeranz, Sudhakar M. Reddy: On Achieving a Complete Fault Coverage for Sequential Machines Using the Transition Fault Model. DAC 1991: 341-346
61 Irith Pomeranz, Sudhakar M. Reddy: Test Generation for Synchronous Sequential Circuits Using Multiple Observation Times. FTCS 1991: 52-59
60 Irith Pomeranz, Sudhakar M. Reddy: Testing of Fault-Tolerant Hardware. Fault-Tolerant Computing Systems 1991: 148-159
59 Dong-Ho Lee, Sudhakar M. Reddy: A New Test Generation Method for Sequential Circuits. ICCAD 1991: 446-449
58 Irith Pomeranz, Sudhakar M. Reddy: Test Generation for Synchronous Sequential Circuits Based on Fault Extraction. ICCAD 1991: 450-453
57 Irith Pomeranz, Sudhakar M. Reddy, Lakshmi N. Reddy: Increasing Fault Coverage for Synchronous Sequential Circuits by the Multiple Observation Time Test Strategy. ICCAD 1991: 454-457
56 Irith Pomeranz, Lakshmi N. Reddy, Sudhakar M. Reddy: COMPACTEST: A Method to Generate Compact Test Sets for Combinatorial Circuits. ITC 1991: 194-203
55 Irith Pomeranz, Sudhakar M. Reddy: Achieving Complete Delay Fault Testability by Extra Inputs. ITC 1991: 273-282
54 Ankan K. Pramanick, Sudhakar M. Reddy: On Multiple Path Propagating Tests for Path Delay Faults. ITC 1991: 393-402
53EESandip Kundu, Sudhakar M. Reddy, Niraj K. Jha: Design of robustly testable combinational logic circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 10(8): 1036-1048 (1991)
1990
52EEAnkan K. Pramanick, Sudhakar M. Reddy: On the fault coverage of delay fault detecting tests. EURO-DAC 1990: 334-338
51 Dong-Ho Lee, Sudhakar M. Reddy: On Determining Scan Flip-Flops in Partial-Scan Designs. ICCAD 1990: 322-325
50EESandip Kundu, Sudhakar M. Reddy: Embedded Totally Self-Checking Checkers: A Practical Design. IEEE Design & Test of Computers 7(4): 5-12 (1990)
49 Sandip Kundu, Sudhakar M. Reddy: On Symmetric Error Correcting and All Unidirectional Error Detecting Codes. IEEE Trans. Computers 39(6): 752-761 (1990)
48EEWing Ning Li, Sudhakar M. Reddy, Sartaj Sahni: Long and short covering edges in combination logic circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 9(12): 1245-1253 (1990)
47EESandip Kundu, Sudhakar M. Reddy: Robust tests for parity trees. J. Electronic Testing 1(3): 191-200 (1990)
1989
46EEV. G. Hemmady, Sudhakar M. Reddy: On the Repair of Redundant RAMs. DAC 1989: 710-713
45 Jung Hwan Kim, Sudhakar M. Reddy: On the Design of Fault-Tolerant Two-Dimensional Systolic Arrays for Yield Enhancement. IEEE Trans. Computers 38(4): 515- (1989)
44EEWing Ning Li, Sudhakar M. Reddy, Sartaj K. Sahni: On path selection in combinational logic circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 8(1): 56-63 (1989)
1988
43EEWing Ning Li, Sudhakar M. Reddy, Sartaj Sahni: On Path Selection in Combinational Logic Circuits. DAC 1988: 142-147
42 Sandip Kundu, Sudhakar M. Reddy: Robust Tests for Parity Trees. ITC 1988: 680-687
41 Ankan K. Pramanick, Sudhakar M. Reddy: On the Detection of Delay Faults. ITC 1988: 845-856
40 Seyed H. Hosseini, Jon G. Kuhl, Sudhakar M. Reddy: On Self-Fault Diagnosis of the Distributed Systems. IEEE Trans. Computers 37(2): 248-251 (1988)
39 Dong Sam Ha, Sudhakar M. Reddy: On the Design of Pseudoexhaustive Testable PLA's. IEEE Trans. Computers 37(4): 468-472 (1988)
38 Sudhakar M. Reddy, Kewal K. Saluja, Mark G. Karpovsky: A Data Compression Technique for Built-In Self-Test. IEEE Trans. Computers 37(9): 1151-1156 (1988)
1987
37EER. Galivanche, Sudhakar M. Reddy: A Parallel PLA Minimization Program. DAC 1987: 600-607
36 Seyed H. Hosseini, Jon G. Kuhl, Sudhakar M. Reddy: Distributed Fault-Tolerance of Tree Structures. IEEE Trans. Computers 36(11): 1378-1382 (1987)
35 Sudhakar M. Reddy, Dong Sam Ha: A New Approach to the Design of Testable PLA's. IEEE Trans. Computers 36(2): 201-211 (1987)
34EEChin Jen Lin, Sudhakar M. Reddy: On Delay Fault Testing in Logic Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 6(5): 694-703 (1987)
1986
33 Dong Sam Ha, Sudhakar M. Reddy: On the Design of Random Pattern Testable PLAs. ITC 1986: 688-695
32 Jon G. Kuhl, Sudhakar M. Reddy: Fault-Tolerance Considerations in Large Multiple-Processor Systems. IEEE Computer 19(3): 56-67 (1986)
31 Sudhakar M. Reddy, Madhukar K. Reddy: Testable Realizations for FET Stuck-Open Faults CMOS Combinational Logic Circuits. IEEE Trans. Computers 35(8): 742-754 (1986)
1985
30EEMadhukar K. Reddy, Sudhakar M. Reddy, Prathima Agrawal: Transistor level test generation for MOS circuits. DAC 1985: 825-828
29 Sudhakar M. Reddy, Vijay Kumar: On Multipath Multistage Interconnection Networks. ICDCS 1985: 210-217
28 Vijay P. Kumar, Sudhakar M. Reddy: Design and Analysis of Fault-Tolerant Multistage Interconnection Networks With Low Link Complexity. ISCA 1985: 376-386
27 Dong Sam Ha, Sudhakar M. Reddy: On the Design of Testable Domino PLAs. ITC 1985: 567-573
1984
26 Vijay P. Kumar, Sudhakar M. Reddy: A Class of Graphs for Fault-Tolerant Processor Interconnections. ICDCS 1984: 448-460
25 Sridhar R. Manthani, Sudhakar M. Reddy: On CMOS Totally Self-Checking Circuits. ITC 1984: 866-877
24 Seyed H. Hosseini, Jon G. Kuhl, Sudhakar M. Reddy: A Diagnosis Algorithm for Distributed Computing Systems with Dynamic Failure and Repair. IEEE Trans. Computers 33(3): 223-233 (1984)
1983
23 Jon G. Kuhl, Sudhakar M. Reddy, P. Raghavan: A Class of Graphs for Processor Interconnection. ICPP 1983: 154-157
22 Jon G. Kuhl, Sudhakar M. Reddy: On Testable Design for CMOS Logic Circuits. ITC 1983: 435-445
1982
21 Sunil Nanda, Sudhakar M. Reddy: Design of Easily Testable Microprocessors : A Case Study. ITC 1982: 480-483
20 Dhiraj K. Pradhan, Sudhakar M. Reddy: A Fault-Tolerant Communication Architecture for Distributed Systems. IEEE Trans. Computers 31(9): 863-870 (1982)
1981
19 R. Parthasarathy, Sudhakar M. Reddy: A Testable Design of Iterative Logic Arrays. IEEE Trans. Computers 30(11): 833-841 (1981)
18 Dong S. Suk, Sudhakar M. Reddy: A March Test for Functional Faults in Semiconductor Random Access Memories. IEEE Trans. Computers 30(12): 982-985 (1981)
1980
17 Jon G. Kuhl, Sudhakar M. Reddy: Distributed Fault-Tolerance For Large Multiprocessor Systems. ISCA 1980: 23-30
16 Dong S. Suk, Sudhakar M. Reddy: Test Procedures for a Class of Pattern-Sensitive Faults in Semiconductor Random-Access Memories. IEEE Trans. Computers 29(6): 419-429 (1980)
1978
15 Jon G. Kuhl, Sudhakar M. Reddy: A Multicode Single Transition-Time State Assignment for Asynchronous Sequential Machines. IEEE Trans. Computers 27(10): 927-934 (1978)
14 Sudhakar M. Reddy: A Class of Linear Codes for Error Control in Byte-per-Card Organized Digital Systems. IEEE Trans. Computers 27(5): 455-459 (1978)
13 Jon G. Kuhl, Sudhakar M. Reddy: On the Detection of Terminal Stuck-Faults. IEEE Trans. Computers 27(5): 467-469 (1978)
1977
12 Sudhakar M. Reddy: A Note on Testing Logic Circuits by Transition Counting. IEEE Trans. Computers 26(3): 313-314 (1977)
11 Sudhakar M. Reddy: Comments on ``Minimal Fault Tests for Combinational Networks''. IEEE Trans. Computers 26(3): 318-319 (1977)
10 Mohammad Javad Ashjaee, Sudhakar M. Reddy: On Totally Self-Checking Checkers for Separable Codes. IEEE Trans. Computers 26(8): 737-744 (1977)
1976
9 Dhiraj K. Pradhan, Sudhakar M. Reddy: Techniques to Construct (2, 1) Separating Systems from Linear Error-Correcting Codes. IEEE Trans. Computers 25(9): 945-949 (1976)
1975
8 Kewal K. Saluja, Sudhakar M. Reddy: Fault Detecting Test Sets for Reed-Muller Canonic Networks. IEEE Trans. Computers 24(10): 995-998 (1975)
1972
7 Kewal K. Saluja, Sudhakar M. Reddy: Multiple Faults in Reed-Muller Canonic Networks FOCS 1972: 185-191
6 George I. Davida, Sudhakar M. Reddy: Forward-Error Correction with Decision Feedback Information and Control 21(2): 117-133 (1972)
1971
5 Sudhakar M. Reddy: Linear Convolutional Codes for Compound Channels Information and Control 19(5): 387-400 (1971)
1970
4 Sudhakar M. Reddy, George I. Davida, John P. Robinson: A Class of High-Rate Double-Error-Correcting Convolutional Codes Information and Control 16(3): 225-230 (1970)
1968
3 Sudhakar M. Reddy, John P. Robinson: A Construction for Convolutional Codes Using Block Codes Information and Control 12(1): 55-70 (1968)
2 Sudhakar M. Reddy: Further Results on Convolutional Codes Derived from Block Codes Information and Control 13(4): 357-362 (1968)
1 Sudhakar M. Reddy, John P. Robinson: A Decoding Algorithm for Some Convolutional Codes Constructed from Block Codes Information and Control 13(5): 492-507 (1968)

Coauthor Index

1Prathima Agrawal [30]
2Bashir M. Al-Hashimi [362] [387] [395] [403] [409] [439]
3Enamul Amyeen [336] [379]
4Mohammad Javad Ashjaee [10]
5Nadir Z. Basturkmen [191] [269] [273] [274] [275] [291]
6Bernd Becker [132] [154] [318] [429] [432] [441]
7Thomas Burch [97]
8Yuan Cai [362] [395] [403] [409]
9Thomas L. Casavant [135]
10Srimat T. Chakradhar [357]
11Sreejit Chakravarty [168] [423] [430] [447]
12Gang Chen [314] [366] [383] [394]
13Kwang-Ting Cheng (Kwang-Ting (Tim) Cheng) [122]
14Wu-Tung Cheng [216] [242] [254] [258] [259] [270] [272] [288] [308] [311] [325] [333] [334] [369] [384] [405] [446]
15Yonsang Cho [339] [353]
16C. N. Chu [304]
17Alejandro Czutro [441]
18Vinay Dabholkar [168]
19George I. Davida [4] [6]
20Dan Devries [242]
21Narendra Devta-Prasanna [363] [371] [388] [391] [423] [430] [447]
22Rolf Drechsler [154]
23Xiaogang Du [325] [333] [334]
24Alireza Ejlali (Ali Reza Ejlali) [395]
25Piet Engelke [441]
26Aftab Farooqi [443]
27Richard O. Gale [443]
28R. Galivanche [37]
29Arun Gunda [363] [371] [388] [391]
30Ruifeng Guo [183] [184] [187] [192] [199] [206] [241] [252] [294] [295] [446]
31Sandeep K. Gupta [128]
32Dong Sam Ha [27] [33] [35] [39] [63]
33Peter Harrod [439]
34J. Hartmann [97]
35V. G. Hemmady [46]
36Harry Hengster [132]
37Seyed H. Hosseini (S. Hossein Hosseini) [24] [36] [40]
38Günter Hotz [97]
39Cheng-Ju Hsieh [308]
40Shi-Yu Huang [230]
41Yu Huang [225] [242] [254] [258] [259] [270] [272] [288] [301] [308] [311]
42Yu-Ting Hung [308]
43Hideyuki Ichihara [218]
44Rahul Jain [103]
45Niraj K. Jha [53] [68]
46Seiji Kajihara [88] [109] [113] [129] [143] [151] [220] [221] [232] [255] [266] [271] [277] [280] [281] [286] [292] [299] [346] [370] [415]
47Mark G. Karpovsky [38]
48W. Khamisani [79]
49S. Saqib Khursheed [439]
50Jung Hwan Kim [45]
51Kozo Kinoshita [88] [109] [151] [218] [271]
52M. Krallmann [97]
53P. Krishnamurthy [363] [371] [388] [391]
54Jon G. Kuhl [13] [15] [17] [22] [23] [24] [32] [36] [40]
55Vijay Kumar [29]
56Vijay P. Kumar [26] [28]
57Sandip Kundu [42] [47] [49] [50] [53] [285] [310] [319] [326] [332] [428]
58Wolfgang Kunz [124]
59Dong-Ho Lee [51] [59] [70]
60Hangkyu Lee [338] [381] [417]
61Matthew D. T. Lewis [441]
62Wei Li [312] [322] [345] [357] [360]
63Wing Ning Li [43] [44] [48]
64Chin Jen Lin [34]
65Xijiang Lin [174] [176] [191] [202] [204] [216] [245] [253] [278] [380] [398] [407]
66Chen Liu [435]
67Steven S. Lumetta (Steven Lumetta) [303]
68D. Luxenburger [122]
69Sridhar R. Manthani [25]
70Pinaki Mazumder [79]
71Robert J. Miller [68]
72Kohei Miyase [266] [277] [281] [286] [299] [346] [370] [415]
73Chris Monico [443]
74H. Mueller [142] [189]
75Neelanjan Mukherjee [242]
76Nilanjan Mukherjee [254] [258] [259] [270] [272] [311] [334]
77Atsushi Murakami [220] [221]
78Sunil Nanda [21]
79Masao Naruse [310]
80U. Nikolaus [97]
81Brian Nutter [443]
82Mitsuyasu Ohta [221]
83Doowon Paik [77] [94] [165]
84R. Parthasarathy [19]
85Janak H. Patel [84] [136] [303]
86Slawomir Pilarski [128]
87Ilia Polian [318] [429] [432] [441]
88Irith Pomeranz [55] [56] [57] [58] [60] [61] [62] [64] [65] [66] [67] [68] [69] [71] [72] [73] [74] [75] [76] [80] [81] [82] [83] [84] [85] [86] [87] [88] [89] [90] [91] [92] [93] [95] [96] [98] [99] [100] [101] [103] [104] [105] [107] [108] [109] [110] [111] [112] [113] [114] [115] [117] [118] [119] [120] [121] [123] [126] [127] [129] [130] [131] [133] [134] [136] [137] [138] [139] [141] [143] [144] [145] [147] [148] [149] [150] [151] [152] [153] [155] [156] [157] [158] [159] [160] [161] [162] [163] [164] [166] [167] [168] [169] [170] [171] [172] [173] [174] [175] [176] [177] [178] [179] [180] [181] [182] [183] [184] [185] [186] [187] [188] [190] [191] [192] [193] [194] [195] [196] [199] [200] [201] [202] [203] [204] [205] [206] [207] [208] [209] [210] [211] [212] [213] [214] [215] [216] [217] [218] [219] [220] [221] [222] [223] [224] [225] [226] [227] [228] [229] [231] [232] [233] [234] [235] [236] [237] [238] [239] [240] [241] [243] [244] [245] [246] [247] [248] [249] [250] [251] [252] [253] [255] [256] [257] [260] [261] [262] [263] [264] [265] [266] [267] [268] [271] [273] [274] [275] [276] [277] [278] [279] [280] [282] [283] [284] [285] [286] [287] [289] [290] [291] [292] [293] [294] [295] [296] [297] [298] [299] [300] [301] [302] [304] [305] [306] [309] [310] [312] [313] [314] [315] [316] [317] [319] [320] [321] [322] [323] [324] [326] [327] [328] [329] [330] [331] [332] [335] [336] [337] [338] [339] [340] [341] [342] [343] [344] [345] [347] [348] [349] [350] [352] [353] [354] [355] [356] [358] [359] [360] [361] [362] [363] [364] [365] [366] [367] [368] [371] [372] [373] [374] [375] [376] [377] [378] [379] [380] [381] [382] [383] [385] [386] [387] [388] [389] [390] [391] [392] [393] [394] [396] [397] [398] [399] [400] [401] [402] [404] [406] [407] [408] [410] [411] [412] [413] [414] [416] [417] [418] [419] [420] [421] [422] [423] [424] [425] [426] [427] [428] [430] [431] [432] [433] [434] [435] [436] [437] [438] [440] [442] [444] [445] [447] [448] [449] [450] [451]
89Dhiraj K. Pradhan [9] [20] [124]
90Ankan K. Pramanick [41] [52] [54] [78] [106] [146]
91P. Raghavan [23]
92Janusz Rajski [225] [245] [269] [278] [284] [307] [316] [351] [356] [366] [380] [383] [387] [394] [398] [407] [431] [445]
93Balkrishna Ramkumar [135]
94Joseph Rayhawk [325] [333] [334]
95Lakshmi N. Reddy [56] [57] [65] [73]
96Madhukar K. Reddy [30] [31]
97Remata S. Reddy [113]
98Santiago Remersaro [398] [407] [431] [445]
99Paul Reuter [272]
100Thomas Rinderknecht [431]
101John P. Robinson [1] [3] [4]
102Don E. Ross [333]
103Sartaj Sahni (Sartaj K. Sahni) [43] [44] [48] [77] [94] [165]
104Kewal K. Saluja [7] [8] [38]
105Omer Samman [242] [254] [258] [259] [270] [272]
106Tsutomu Sasao [220]
107Jacob Savir [128]
108Marcus T. Schmitz [395] [403]
109Bharath Seshadri [343] [379]
110Khushro Shahookar [79]
111Yun Shao [199] [255] [267] [290] [292]
112Takashi Shimono [232]
113Uwe Sparmann [97] [102] [122] [125] [132] [142] [189]
114Volker Strumpen [135]
115Dong S. Suk [16] [18]
116Sadami Takeoka [221]
117Huaxing Tang [271] [309] [356] [366] [384] [405]
118Xun Tang [432] [446]
119Kenjiro Taniguchi [280] [286]
120Kenta Terashima [370] [415]
121Chien-Chung Tsai [242] [254] [258] [259] [270] [272] [311]
122Jerzy Tyszer [307] [316] [351] [356]
123Prasanti Uppaluri [87] [101] [108]
124Prab Varma [128]
125Ganesh Venkataraman [305]
126Srikanth Venkataraman [336] [337] [343] [359] [379] [396]
127Chen Wang [248] [278] [307] [316] [351] [356] [366]
128Seongmoon Wang [357]
129Xiaoqing Wen [370] [415]
130Sitaran Yadavalli [114] [197]
131Fan Yang [423] [430] [447]
132Chaowen Yu [312] [322] [348] [372] [385]
133Yahya Zaidan [254] [258] [270] [272]
134Yanping Zhang [270]
135Zhuo Zhang [365] [380] [387] [414]
136Yervant Zorian [300]
137Wei Zou [301] [304] [369] [384] [405]

Colors in the list of coauthors

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)