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B. Ramakrishna Rau Vis

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*2002
35EEAlain Darte, Robert Schreiber, B. Ramakrishna Rau, Frédéric Vivien: Constructing and exploiting linear schedules with prescribed parallelism. ACM Trans. Design Autom. Electr. Syst. 7(1): 159-172 (2002)
34EEVinod Kathail, Shail Aditya, Robert Schreiber, B. Ramakrishna Rau, Darren C. Cronquist, Mukund Sivaraman: PICO: Automatically Designing Custom Computers. IEEE Computer 35(9): 39-47 (2002)
33EERobert Schreiber, Shail Aditya, Scott A. Mahlke, Vinod Kathail, B. Ramakrishna Rau, Darren C. Cronquist, Mukund Sivaraman: PICO-NPA: High-Level Synthesis of Nonprogrammable Hardware Accelerators. VLSI Signal Processing 31(2): 127-142 (2002)
2001
32EEB. Ramakrishna Rau, Michael S. Schlansker: Embedded Computer Architecture and Automation. IEEE Computer 34(4): 75-83 (2001)
2000
31EERobert Schreiber, Shail Aditya, B. Ramakrishna Rau, Vinod Kathail, Scott A. Mahlke, Santosh G. Abraham, Greg Snider: High-Level Synthesis of Nonprogrammable Hardware Accelerators. ASAP 2000: 113-
30EEB. Ramakrishna Rau: The era of embedded computing. CASES 2000: 119
29EESantosh G. Abraham, B. Ramakrishna Rau: Efficient design space exploration in PICO. CASES 2000: 71-79
28EEB. Ramakrishna Rau, Michael S. Schlansker: Embedded Computing: New Directions in Architecture and Automation. HiPC 2000: 225-244
27EEAlain Darte, Robert Schreiber, B. Ramakrishna Rau, Frédéric Vivien: A Constructive Solution to the Juggling Problem in Processor Array Synthesis. IPDPS 2000: 815-822
26EEShail Aditya, Scott A. Mahlke, B. Ramakrishna Rau: Code size minimization and retargetable assembly for custom EPIC and VLIW instruction formats. ACM Trans. Design Autom. Electr. Syst. 5(4): 752-773 (2000)
25EEMichael S. Schlansker, B. Ramakrishna Rau: EPIC: Explicititly Parallel Instruction Computing. IEEE Computer 33(2): 37-45 (2000)
1999
24EEShail Aditya, B. Ramakrishna Rau, Vinod Kathail: Automatic Architectural Synthesis of VLIW and EPIC Processors. ISSS 1999: 107-113
1998
23 John C. Gyllenhaal, Wen-mei W. Hwu, B. Ramakrishna Rau: Optimization of Machine Descriptions for Efficient Use. International Journal of Parallel Programming 26(4): 417-447 (1998)
1996
22EEJohn C. Gyllenhaal, Wen-mei W. Hwu, B. Ramakrishna Rau: Optimization of Machine Descriptions for Efficient Use. MICRO 1996: 349-358
21EEChandra Chekuri, Richard Johnson, Rajeev Motwani, B. Natarajan, B. Ramakrishna Rau, Michael S. Schlansker: Profile-driven Instruction Level Parallel Scheduling with Application to Super Blocks. MICRO 1996: 58-67
1995
20EERichard E. Hank, Wen-mei W. Hwu, B. Ramakrishna Rau: Region-based compilation: an introduction and motivation. MICRO 1995: 158-168
1994
19EEB. Ramakrishna Rau: Iterative modulo scheduling: an algorithm for software pipelining loops. MICRO 1994: 63-74
1993
18EESantosh G. Abraham, Rabin A. Sugumar, Daniel Windheiser, B. Ramakrishna Rau, Rajiv Gupta: Predictability of load/store instruction latencies. MICRO 1993: 139-152
17EEB. Ramakrishna Rau: Dynamically scheduled VLIW processors. MICRO 1993: 80-92
16 Nancy J. Warter, Scott A. Mahlke, Wen-mei W. Hwu, B. Ramakrishna Rau: Reverse If-Conversion. PLDI 1993: 290-299
15EEScott A. Mahlke, William Y. Chen, Roger A. Bringmann, Richard E. Hank, Wen-mei W. Hwu, B. Ramakrishna Rau, Michael S. Schlansker: Sentinel Scheduling for VLIW and Superscalar Processors. ACM Trans. Comput. Syst. 11(4): 376-408 (1993)
1992
14 Scott A. Mahlke, William Y. Chen, Wen-mei W. Hwu, B. Ramakrishna Rau, Michael S. Schlansker: Sentinel Scheduling for VLIW and Superscalar Processors. ASPLOS 1992: 238-247
13EEB. Ramakrishna Rau, Michael S. Schlansker, Parthasarathy P. Tirumalai: Code generation schema for modulo scheduled loops. MICRO 1992: 158-169
12 B. Ramakrishna Rau, M. Lee, Parthasarathy P. Tirumalai, Michael S. Schlansker: Register Allocation for Software Pipelined Loops. PLDI 1992: 283-299
1991
11EEB. Ramakrishna Rau: Pseudo-Randomly Interleaved Memory. ISCA 1991: 74-83
10 B. Ramakrishna Rau: Data Flow and Dependence Analysis for Instruction Level Parallelism. LCPC 1991: 236-250
1989
9 B. Ramakrishna Rau, Michael S. Schlansker, David W. L. Yen: The Cydram 5 Stride-Insensitive Memory System. ICPP (1) 1989: 242-246
8 B. Ramakrishna Rau, David W. L. Yen, Wei C. Yen, Ross A. Towle: The Cydra 5 Departmental Supercomputer: Design Philosophies, Decisions, and Trade-offs. IEEE Computer 22(1): 12-35 (1989)
1988
7 B. Ramakrishna Rau: Cydra 5 Directed Dataflow Architecture. COMPCON 1988: 106-113
1982
6EEPradip Bose, B. Ramakrishna Rau, Michael S. Schlansker: Systematically derived instruction sets for high-level language support. ACM Southeast Regional Conference 1982: 73-84
5 B. Ramakrishna Rau, Christopher D. Glaeser, E. M. Greenawalt: Architectural Support for the Efficient Generation of Code for Horizontal Architectures. ASPLOS 1982: 96-99
4EEB. Ramakrishna Rau, Christopher D. Glaeser, Raymond L. Picard: Efficient code generation for horizontal architectures: Compiler techniques and architectural support. ISCA 1982: 131-139
1979
3 B. Ramakrishna Rau: Program Behavior and the Performance of Interleaved Memories. IEEE Trans. Computers 28(3): 191-199 (1979)
2 B. Ramakrishna Rau: Interleaved Memory Bandwidth in a Model of a Muyltiprocessor Computer System. IEEE Trans. Computers 28(9): 678-681 (1979)
1977
1 B. Ramakrishna Rau, George E. Rossman: The Effect of Instruction Fetch Strategies upon the Performance of Pipelined Instruction Units. ISCA 1977: 80-89

Coauthor Index

1Santosh G. Abraham [18] [29] [31]
2Shail Aditya [24] [26] [31] [33] [34]
3Pradip Bose [6]
4Roger A. Bringmann [15]
5Chandra Chekuri [21]
6William Y. Chen [14] [15]
7Darren C. Cronquist [33] [34]
8Alain Darte [27] [35]
9Christopher D. Glaeser [4] [5]
10E. M. Greenawalt [5]
11Rajiv Gupta [18]
12John C. Gyllenhaal [22] [23]
13Richard E. Hank [15] [20]
14Wen-mei W. Hwu [14] [15] [16] [20] [22] [23]
15Richard Johnson [21]
16Vinod Kathail [24] [31] [33] [34]
17M. Lee [12]
18Scott A. Mahlke [14] [15] [16] [26] [31] [33]
19Rajeev Motwani [21]
20B. Natarajan [21]
21Raymond L. Picard [4]
22George E. Rossman [1]
23Michael S. Schlansker [6] [9] [12] [13] [14] [15] [21] [25] [28] [32]
24Robert Schreiber [27] [31] [33] [34] [35]
25Mukund Sivaraman [33] [34]
26Greg Snider [31]
27Rabin A. Sugumar [18]
28Parthasarathy P. Tirumalai [12] [13]
29Ross A. Towle [8]
30Frédéric Vivien [27] [35]
31Nancy J. Warter [16]
32Daniel Windheiser [18]
33David W. L. Yen [8] [9]
34Wei C. Yen [8]

Colors in the list of coauthors

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)