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Vasant B. Rao Vis

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*2002
14EEVasant B. Rao, Jeffrey Soreff, Ravichander Ledalla, Fred L. Yang: Aggressive crunching of extracted RC netlists. Timing Issues in the Specification and Synthesis of Digital Systems 2002: 70-77
1996
13EEJohn Y. Sayah, Rajesh Gupta, Deepak D. Sherlekar, Philip S. Honsinger, Jitendra M. Apte, S. Wayne Bollinger, Hai Hsia Chen, Sumit DasGupta, Edward P. Hsieh, Andrew D. Huber, Edward J. Hughes, Zahi M. Kurzum, Vasant B. Rao, Thepthai Tabtieng, Vigen Valijan, David Y. Yang: Design planning for high-performance ASICs. IBM Journal of Research and Development 40(4): 431-452 (1996)
1995
12EEVasant B. Rao: Delay Analysis of the Distributed RC Line. DAC 1995: 370-375
1993
11EESachin S. Sapatnekar, Vasant B. Rao, Pravin M. Vaidya, Sung-Mo Kang: An exact solution to the transistor sizing problem for CMOS circuits using convex optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 12(11): 1621-1634 (1993)
1991
10 Sachin S. Sapatnekar, Vasant B. Rao, Pravin M. Vaidya: A Convex Optimization Approach to Transistor Sizing for CMOS Circuits. ICCAD 1991: 482-485
9EEYoussef Saab, Vasant B. Rao: Combinatorial optimization by stochastic evolution. IEEE Trans. on CAD of Integrated Circuits and Systems 10(4): 525-535 (1991)
8EEYun-Cheng Ju, Vasant B. Rao, Resve A. Saleh: Consistency checking and optimization of macromodels. IEEE Trans. on CAD of Integrated Circuits and Systems 10(8): 957-967 (1991)
1990
7EEYoussef Saab, Vasant B. Rao: Stochastic Evolution: a Fast Effective Heuristic for Some Generic Layout Problems. DAC 1990: 26-31
6EEYoussef Saab, Vasant B. Rao: Fast effective heuristics for the graph bisectioning problem. IEEE Trans. on CAD of Integrated Circuits and Systems 9(1): 91-98 (1990)
1989
5EEYoussef Saab, Vasant B. Rao: An Evolution-Based Approach to Partitioning ASIC Systems. DAC 1989: 767-770
4EEYoussef Saab, Vasant B. Rao: A Stochastic Algorithm for Circuit Bi-Partitioning. Great Lakes Computer Science Conference 1989: 313-321
1988
3EEM. A. Manzoul, Vasant B. Rao: Multi-Input Fuzzy Inference Engine on a Systolic Array. IEA/AIE (Vol. 2) 1988: 958-964
1987
2EEShun-Lin Su, Vasant B. Rao, Timothy N. Trick: HPEX: A Hierarchical Parasitic Circuit Extractor. DAC 1987: 566-569
1EEVasant B. Rao, Timothy N. Trick: Network Partitioning and Ordering for MOS VLSI Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 6(1): 128-144 (1987)

Coauthor Index

1Jitendra M. Apte [13]
2S. Wayne Bollinger [13]
3Hai Hsia Chen [13]
4Sumit DasGupta [13]
5Rajesh K. Gupta (Rajesh Gupta) [13]
6Philip S. Honsinger [13]
7Edward P. Hsieh [13]
8Andrew D. Huber [13]
9Edward J. Hughes [13]
10Yun-Cheng Ju [8]
11Sung-Mo Kang [11]
12Zahi M. Kurzum [13]
13Ravichander Ledalla [14]
14M. A. Manzoul [3]
15Youssef Saab [4] [5] [6] [7] [9]
16Resve A. Saleh (Resve Saleh, Res Saleh) [8]
17Sachin S. Sapatnekar [10] [11]
18John Y. Sayah [13]
19Deepak D. Sherlekar [13]
20Jeffrey Soreff [14]
21Shun-Lin Su [2]
22Thepthai Tabtieng [13]
23Timothy N. Trick [1] [2]
24Pravin M. Vaidya [10] [11]
25Vigen Valijan [13]
26David Y. Yang [13]
27Fred L. Yang [14]

Colors in the list of coauthors

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)