| 2008 |
|---|
| 9 | EE | Carlo Curino,
Luca Fossati,
Vincenzo Rana,
F. Redaelli,
Marco D. Santambrogio,
Donatella Sciuto:
The Shining embedded system design methodology based on self dynamic reconfigurable architectures.
ASP-DAC 2008: 595-600 |
| 8 | EE | Andrea Cuoccio,
Paolo R. Grassi,
Vincenzo Rana,
Marco D. Santambrogio,
Donatella Sciuto:
A Generation Flow for Self-Reconfiguration Controllers Customization.
DELTA 2008: 279-284 |
| 7 | EE | Alessandro Meroni,
Vincenzo Rana,
Marco D. Santambrogio,
Donatella Sciuto:
A Requirements-Driven Reconfigurable SoC Communication Infrastructure Design Flow.
DELTA 2008: 405-409 |
| 2007 |
|---|
| 6 | EE | Marco D. Santambrogio,
Seda Ogrenci Memik,
Vincenzo Rana,
Umut A. Acar,
Donatella Sciuto:
A novel SoC design methodology combining adaptive software and reconfigurable hardware.
ICCAD 2007: 303-308 |
| 5 | EE | Vincenzo Rana,
Marco D. Santambrogio,
Donatella Sciuto,
Boris Kettelhoit,
Markus Köster,
Mario Porrmann,
Ulrich Rückert:
Partial Dynamic Reconfiguration in a Multi-FPGA Clustered Architecture Based on Linux.
IPDPS 2007: 1-8 |
| 4 | EE | Vincenzo Rana,
Marco D. Santambrogio,
Donatella Sciuto:
Dynamic Reconfigurability in Embedded System Design.
ISCAS 2007: 2734-2737 |
| 3 | EE | Vincenzo Rana,
Chiara Sandionigi,
Marco D. Santambrogio,
Donatella Sciuto:
An adaptive genetic algorithm for dynamically reconfigurable modules allocation.
VLSI-SoC 2007: 128-133 |
| 2006 |
|---|
| 2 | EE | Fabrizio Ferrandi,
G. Ferrara,
R. Palazzo,
Vincenzo Rana,
Marco D. Santambrogio:
VHDL to FPGA automatic IP-Core generation: a case study on Xilinx design flow.
IPDPS 2006 |
| 1 | EE | Matteo Murgida,
Alessandro Panella,
Vincenzo Rana,
Marco D. Santambrogio,
Donatella Sciuto:
Fast IP-Core Generation in a Partial Dynamic Reconfiguration Workflow.
VLSI-SoC 2006: 74-79 |
