| |
| * | 2008 | |
|---|---|---|
| 2 | EE | Witold A. Pleskacz, Maksim Jenihhin, Jaan Raik, Michal Rakowski, Raimund Ubar, Wieslaw Kuzmicz: Hierarchical Analysis of Short Defects between Metal Lines in CMOS IC. DSD 2008: 729-734 |
| 2007 | ||
| 1 | Maksim Jenihhin, Jaan Raik, Raimund Ubar, Witold A. Pleskacz, Michal Rakowski: Layout to Logic Defect Analysis for Hierarchical Test Generation. DDECS 2007: 35-40 | |
| 1 | Maksim Jenihhin | [1] [2] |
| 2 | Wieslaw Kuzmicz | [2] |
| 3 | Witold A. Pleskacz | [1] [2] |
| 4 | Jaan Raik | [1] [2] |
| 5 | Raimund Ubar | [1] [2] |