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Anand Raghunathan Vis

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*2009
158EEChunxiao Li, Anand Raghunathan, Niraj K. Jha: An architecture for secure software defined radio. DATE 2009: 448-453
157EENarayanan Sundaram, Anand Raghunathan, Srimat T. Chakradhar: A framework for efficient and scalable execution of domain-specific templates on GPUs. IPDPS 2009: 1-12
156EEJiayuan Meng, Srimat T. Chakradhar, Anand Raghunathan: Best-effort parallel execution framework for Recognition and mining applications. IPDPS 2009: 1-12
155EENilanjan Banerjee, Saumya Chandra, Swaroop Ghosh, Sujit Dey, Anand Raghunathan, Kaushik Roy: Coping with Variations through System-Level Design. VLSI Design 2009: 581-586
2008
154EEJanar Thoguluva, Anand Raghunathan, Srimat T. Chakradhar: Efficient Software Architecture for IPSec Acceleration Using a Programmable Security Processor. DATE 2008: 1148-1153
153EENajwa Aaraj, Anand Raghunathan, Niraj K. Jha: Dynamic Binary Instrumentation-Based Framework for Malware Defense. DIMVA 2008: 64-87
152EENajwa Aaraj, Anand Raghunathan, Niraj K. Jha: Analysis and design of a hardware/software trusted platform module for embedded systems. ACM Trans. Embedded Comput. Syst. 8(1): (2008)
151EEKrishna Sekar, Kanishka Lahiri, Anand Raghunathan, Sujit Dey: Dynamically Configurable Bus Topologies for High-Performance On-Chip Communication. IEEE Trans. VLSI Syst. 16(10): 1413-1426 (2008)
150EEDimitris Gizopoulos, Mihalis Psarakis, Miltiadis Hatzimihail, M. Maniatakos, Antonis M. Paschalis, Anand Raghunathan, Srivaths Ravi: Systematic Software-Based Self-Test for Pipelined Processors. IEEE Trans. VLSI Syst. 16(11): 1441-1453 (2008)
2007
149 Diana Marculescu, Anand Raghunathan, Ali Keshavarzi, Vijaykrishnan Narayanan: Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007, Portland, OR, USA, August 27-29, 2007 ACM 2007
148EESaumya Chandra, Kanishka Lahiri, Anand Raghunathan, Sujit Dey: System-on-Chip Power Management Considering Leakage Power Variations. DAC 2007: 877-882
147EEMohammad Ali Ghodrat, Kanishka Lahiri, Anand Raghunathan: Accelerating System-on-Chip Power Analysis Using Hybrid Power Estimation. DAC 2007: 883-886
146EENajwa Aaraj, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha: Energy and execution time analysis of a software-based trusted platform module. DATE 2007: 1128-1133
145EENikhil Bansal, Kanishka Lahiri, Anand Raghunathan: Automatic Power Modeling of Infrastructure IP for System-on-Chip Power Analysis. VLSI Design 2007: 513-520
144EEYunsi Fei, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha: Energy-optimizing source code transformations for operating system-driven embedded software. ACM Trans. Embedded Comput. Syst. 7(1): (2007)
143EEJoel Coburn, Srivaths Ravi, Anand Raghunathan: Hardware Accelerated Power Estimation CoRR abs/0710.4742: (2007)
142EEPatrick Schaumont, Anand Raghunathan: Guest Editors' Introduction: Security and Trust in Embedded-Systems Design. IEEE Design & Test of Computers 24(6): 518-520 (2007)
141EEChao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha: Generation of Heterogeneous Distributed Architectures for Memory-Intensive Applications Through High-Level Synthesis. IEEE Trans. VLSI Syst. 15(11): 1191-1204 (2007)
140EENajwa Aaraj, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha: Hybrid Architectures for Efficient and Secure Face Authentication in Embedded Systems. IEEE Trans. VLSI Syst. 15(3): 296-308 (2007)
139EENachiketh R. Potlapally, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha, Ruby B. Lee: Aiding Side-Channel Attacks on Cryptographic Software With Satisfiability-Based Analysis. IEEE Trans. VLSI Syst. 15(4): 465-470 (2007)
138EEDivya Arora, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha: Architectural Support for Run-Time Validation of Program Data Properties. IEEE Trans. VLSI Syst. 15(5): 546-559 (2007)
137EENachiketh R. Potlapally, Srivaths Ravi, Anand Raghunathan, Ruby B. Lee, Niraj K. Jha: Configuration and Extension of Embedded Processors to Optimize IPSec Protocol Execution. IEEE Trans. VLSI Syst. 15(5): 605-609 (2007)
136EEDivya Arora, Anand Raghunathan, Srivaths Ravi, Murugan Sankaradass, Niraj K. Jha, Srimat T. Chakradhar: Exploring Software Partitions for Fast Security Processing on a Multiprocessor Mobile SoC. IEEE Trans. VLSI Syst. 15(6): 699-710 (2007)
135EEAnish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha: Hybrid Simulation for Energy Estimation of Embedded Software. IEEE Trans. on CAD of Integrated Circuits and Systems 26(10): 1843-1854 (2007)
134EEFei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha: A Synthesis Methodology for Hybrid Custom Instruction and Coprocessor Generation for Extensible Processors. IEEE Trans. on CAD of Integrated Circuits and Systems 26(11): 2035-2045 (2007)
133EEAnish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha: Automated Energy/Performance Macromodeling of Embedded Software. IEEE Trans. on CAD of Integrated Circuits and Systems 26(3): 542-552 (2007)
2006
132 Wolfgang Nebel, Mircea R. Stan, Anand Raghunathan, Jörg Henkel, Diana Marculescu: Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006, Tegernsee, Bavaria, Germany, October 4-6, 2006 ACM 2006
131EEDivya Arora, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha: Architectural support for safe software execution on embedded processors. CODES+ISSS 2006: 106-111
130EEMihalis Psarakis, Dimitris Gizopoulos, Miltiadis Hatzimihail, Antonis M. Paschalis, Anand Raghunathan, Srivaths Ravi: Systematic software-based self-test for pipelined processors. DAC 2006: 393-398
129EEDivya Arora, Anand Raghunathan, Srivaths Ravi, Murugan Sankaradass, Niraj K. Jha, Srimat T. Chakradhar: Software architecture exploration for high-performance security processing on a multiprocessor mobile SoC. DAC 2006: 496-501
128EEPhillip Stanley-Marbell, Kanishka Lahiri, Anand Raghunathan: Adaptive data placement in an embedded multiprocessor thread library. DATE 2006: 698-699
127EEKrishna Sekar, Kanishka Lahiri, Anand Raghunathan, Sujit Dey: Integrated data relocation and bus reconfiguration for adaptive system-on-chip platforms. DATE 2006: 728-733
126EENajwa Aaraj, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha: Architectures for efficient face authentication in embedded systems. DATE Designers' Forum 2006: 1-6
125EENachiketh R. Potlapally, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha, Ruby B. Lee: Satisfiability-based framework for enabling side-channel attacks on cryptographic software. DATE Designers' Forum 2006: 18-23
124EEAnish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha: Active Learning Driven Data Acquisition for Sensor Networks. ISCC 2006: 929-934
123EESaumya Chandra, Kanishka Lahiri, Anand Raghunathan, Sujit Dey: Considering process variations during system-level power analysis. ISLPED 2006: 342-345
122EENachiketh R. Potlapally, Srivaths Ravi, Anand Raghunathan, Ruby B. Lee, Niraj K. Jha: Impact of Configurability and Extensibility on IPSec Protocol Execution on Embedded Processors. VLSI Design 2006: 299-304
121EEFei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha: Hybrid Custom Instruction and Co-Processor Synthesis Methodology for Extensible Processors. VLSI Design 2006: 473-476
120EENachiketh R. Potlapally, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha: A Study of the Energy Consumption Characteristics of Cryptographic Algorithms and Security Protocols. IEEE Trans. Mob. Comput. 5(2): 128-143 (2006)
119EEFei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha: A Scalable Synthesis Methodology for Application-Specific Processors. IEEE Trans. VLSI Syst. 14(11): 1175-1188 (2006)
118EEDivya Arora, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha: Hardware-Assisted Run-Time Monitoring for Secure Program Execution on Embedded Processors. IEEE Trans. VLSI Syst. 14(12): 1295-1308 (2006)
117EEKanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana: The LOTTERYBUS on-chip communication architecture. IEEE Trans. VLSI Syst. 14(6): 596-608 (2006)
116EEChao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha: Use of Computation-Unit Integrated Memories in High-Level Synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 25(10): 1969-1989 (2006)
115EELin Zhong, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha: RTL-Aware Cycle-Accurate Functional Power Estimation. IEEE Trans. on CAD of Integrated Circuits and Systems 25(10): 2103-2117 (2006)
114EELoganathan Lingappan, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha, Srimat T. Chakradhar: Test-Volume Reduction in Systems-on-a-Chip Using Heterogeneous and Multilevel Compression Techniques. IEEE Trans. on CAD of Integrated Circuits and Systems 25(10): 2193-2206 (2006)
113EEFei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha: Application-specific heterogeneous multiprocessor synthesis using extensible processors. IEEE Trans. on CAD of Integrated Circuits and Systems 25(9): 1589-1602 (2006)
2005
112EEJoel Coburn, Srivaths Ravi, Anand Raghunathan, Srimat T. Chakradhar: SECA: security-enhanced communication architecture. CASES 2005: 78-89
111EEDivya Arora, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha: Enhancing security through hardware-assisted run-time validation of program data properties. CODES+ISSS 2005: 190-195
110EEAnish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha: Hybrid simulation for embedded software energy estimation. DAC 2005: 23-26
109EEPallav Gupta, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha: Efficient fingerprint-based user authentication for embedded systems. DAC 2005: 244-247
108EEKrishna Sekar, Kanishka Lahiri, Anand Raghunathan, Sujit Dey: FLEXBUS: a high-performance system-on-chip communication architecture with a dynamically configurable topology. DAC 2005: 571-574
107EEJoel Coburn, Srivaths Ravi, Anand Raghunathan: Power emulation: a new paradigm for power estimation. DAC 2005: 700-705
106EEDivya Arora, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha: Secure Embedded Processing through Hardware-Assisted Run-Time Monitoring. DATE 2005: 178-183
105EEJoel Coburn, Srivaths Ravi, Anand Raghunathan: Hardware Accelerated Power Estimation. DATE 2005: 528-529
104EEFei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha: Synthesis of Application-Specific Heterogeneous Multiprocessor Architectures Using Extensible Processors. VLSI Design 2005: 551-556
103EENikhil Bansal, Kanishka Lahiri, Anand Raghunathan, Srimat T. Chakradhar: Power Monitors: A Framework for System-Level Power Estimation Using Heterogeneous Power Models. VLSI Design 2005: 579-585
102EELoganathan Lingappan, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha, Srimat T. Chakradhar: Heterogeneous and Multi-Level Compression Techniques for Test Volume Reduction in Systems-on-Chip. VLSI Design 2005: 65-70
101EETat Kee Tan, Anand Raghunathan, Niraj K. Jha: Energy macromodeling of embedded operating systems. ACM Trans. Embedded Comput. Syst. 4(1): 231-254 (2005)
100EEWeidong Wang, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha: Input space-adaptive optimization for embedded-software synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 24(11): 1677-1693 (2005)
99EEChao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha: Generation of distributed logic-memory architectures through high-level synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 24(11): 1694-1711 (2005)
2004
98EEKanishka Lahiri, Anand Raghunathan: Power analysis of system-level on-chip communication architectures. CODES+ISSS 2004: 236-241
97EESrivaths Ravi, Paul C. Kocher, Ruby B. Lee, Gary McGraw, Anand Raghunathan: Security as a new dimension in embedded system design. DAC 2004: 753-760
96EEAnish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha: Automated energy/performance macromodeling of embedded software. DAC 2004: 99-102
95 Tat Kee Tan, Anand Raghunathan, Niraj K. Jha: An Energy-Aware Synthesis Methodology for OS-Driven Multi-Process Embedded Software. ESA/VLSI 2004: 601-605
94EELin Zhong, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha: Power estimation for cycle-accurate functional descriptions of hardware. ICCAD 2004: 668-675
93EEChao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha: High-level synthesis using computation-unit integrated memories. ICCAD 2004: 783-790
92EEYunsi Fei, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha: Energy-Optimizing Source Code Transformations for OS-driven Embedded Software. VLSI Design 2004: 261-266
91EEWeidong Wang, Anand Raghunathan, Niraj K. Jha: Profiling Driven Computation Reuse: An Embedded Software Synthesis Technique for Energy and Performance Optimization. VLSI Design 2004: 267-
90EESrivaths Ravi, Anand Raghunathan, Srimat T. Chakradhar: Tamper Resistance Mechanisms for Secure, Embedded Systems. VLSI Design 2004: 605-
89EESrivaths Ravi, Anand Raghunathan, Paul C. Kocher, Sunil Hattangady: Security in embedded systems: Design challenges. ACM Trans. Embedded Comput. Syst. 3(3): 461-491 (2004)
88EEWeidong Wang, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha: Input space adaptive design: a high-level methodology for optimizing energy and performance. IEEE Trans. VLSI Syst. 12(6): 590-602 (2004)
87EEGanesh Lakshminarayana, Anand Raghunathan, Kamal S. Khouri, Niraj K. Jha, Sujit Dey: Common-case computation: a high-level energy and performance optimization technique. IEEE Trans. on CAD of Integrated Circuits and Systems 23(1): 33-49 (2004)
86EEFei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha: Custom-instruction synthesis for extensible-processor platforms. IEEE Trans. on CAD of Integrated Circuits and Systems 23(2): 216-228 (2004)
85EEKanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana, Sujit Dey: Design of high-performance system-on-chips using communication architecture tuners. IEEE Trans. on CAD of Integrated Circuits and Systems 23(5): 620-636 (2004)
84EEYunsi Fei, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha: A hybrid energy-estimation technique for extensible processors. IEEE Trans. on CAD of Integrated Circuits and Systems 23(5): 652-664 (2004)
83EEKanishka Lahiri, Anand Raghunathan, Sujit Dey: Efficient power profiling for battery-driven embedded system design. IEEE Trans. on CAD of Integrated Circuits and Systems 23(6): 919-932 (2004)
82EEKanishka Lahiri, Anand Raghunathan, Sujit Dey: Design space exploration for optimizing on-chip communication architectures. IEEE Trans. on CAD of Integrated Circuits and Systems 23(6): 952-961 (2004)
81EEWeidong Wang, Anand Raghunathan, Niraj K. Jha, Sujit Dey: Resource budgeting for Multiprocess High-level synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 23(7): 1010-1019 (2004)
2003
80EEWeidong Wang, Tat Kee Tan, Jiong Luo, Yunsi Fei, Li Shang, Keith S. Vallerio, Lin Zhong, Anand Raghunathan, Niraj K. Jha: A comprehensive high-level synthesis system for control-flow intensive behaviors. ACM Great Lakes Symposium on VLSI 2003: 11-14
79EELi Chen, Srivaths Ravi, Anand Raghunathan, Sujit Dey: A scalable software-based self-test methodology for programmable processors. DAC 2003: 548-553
78EEAnand Raghunathan, Srivaths Ravi, Sunil Hattangady, Jean-Jacques Quisquater: Securing Mobile Appliances: New Challenges for the System Designer. DATE 2003: 10176-10183
77EEYunsi Fei, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha: Energy Estimation for Extensible Processors. DATE 2003: 10682-10687
76EEDavide Bertozzi, Anand Raghunathan, Luca Benini, Srivaths Ravi: Transport Protocol Optimization for Energy Efficient Wireless Embedded Systems. DATE 2003: 10706-10713
75EETat Kee Tan, Anand Raghunathan, Niraj K. Jha: Software Architectural Transformations: A New Approach to Low Energy Embedded Software. DATE 2003: 11046-11051
74EEFei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha: A Scalable Application-Specific Processor Synthesis Methodology. ICCAD 2003: 283-290
73EEChao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha: Synthesis of Heterogeneous Distributed Architectures for Memory-Intensive Applications. ICCAD 2003: 46-53
72EENachiketh R. Potlapally, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha: Analyzing the energy consumption of security protocols. ISLPED 2003: 30-35
71EESrivaths Ravi, Anand Raghunathan, Srimat T. Chakradhar: Embedding Security in Wireless Embedded Systems. VLSI Design 2003: 269-270
70EESrivaths Ravi, Anand Raghunathan, Srimat T. Chakradhar: Efficient RTL Power Estimation for Large Designs. VLSI Design 2003: 431-439
69EEWeidong Wang, Niraj K. Jha, Anand Raghunathan, Sujit Dey: High-level Synthesis of Multi-process Behavioral Descriptions. VLSI Design 2003: 467-473
68EEAnand Raghunathan, Sujit Dey, Niraj K. Jha: High-level macro-modeling and estimation techniques for switching activity and power consumption. IEEE Trans. VLSI Syst. 11(4): 538-557 (2003)
67EERobert P. Dick, Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha: Analysis of power dissipation in embedded systems using real-time operating systems. IEEE Trans. on CAD of Integrated Circuits and Systems 22(5): 615-627 (2003)
66EETat Kee Tan, Anand Raghunathan, Niraj K. Jha: A simulation framework for energy-consumption analysis of OS-driven embedded applications. IEEE Trans. on CAD of Integrated Circuits and Systems 22(9): 1284-1294 (2003)
2002
65EEKanishka Lahiri, Anand Raghunathan, Sujit Dey: Fast system-level power profiling for battery-efficient system design. CODES 2002: 157-162
64EEKanishka Lahiri, Sujit Dey, Anand Raghunathan: Communication architecture based power management for battery efficient system design. DAC 2002: 691-696
63EESrivaths Ravi, Anand Raghunathan, Nachiketh R. Potlapally, Murugan Sankaradass: System design methodologies for a wireless security processing platform. DAC 2002: 777-782
62EEChao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha: High-level synthesis of distributed logic-memory architectures. ICCAD 2002: 564-571
61EEFei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha: Synthesis of custom processors based on extensible platforms. ICCAD 2002: 641-648
60EETat Kee Tan, Anand Raghunathan, Niraj K. Jha: Embedded Operating System Energy Analysis and Macro-Modeling. ICCD 2002: 515-520
59EEAnand Raghunathan, Nachiketh R. Potlapally, Srivaths Ravi: Securing Wireless Data: System Architecture Challenges. ISSS 2002: 195-200
58EEKanishka Lahiri, Anand Raghunathan, Sujit Dey, Debashis Panigrahi: Embedded Tutorial: Battery-Driven System Design: A New Frontier in Low Power Design. VLSI Design 2002: 261-267
57EEVijay Raghunathan, Anand Raghunathan, Mani B. Srivastava, Milos D. Ercegovac: High-Level Synthesis with SIMD Units. VLSI Design 2002: 407-413
56EEWeidong Wang, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha: Input Space Adaptive Embedded Software Synthesis. VLSI Design 2002: 711-718
55EEJ. Borel, Anand Raghunathan, Jim Sproch, Michael Howells, Janusz Rajski: Innovations in Test Automation. VTS 2002: 43-46
54EEKanishka Lahiri, Sujit Dey, Anand Raghunathan: Communication-Based Power Management. IEEE Design & Test of Computers 19(4): 118-130 (2002)
53EEMarcello Lajolo, Anand Raghunathan, Sujit Dey, Luciano Lavagno: Cosimulation-based power estimation for system-on-chip design. IEEE Trans. VLSI Syst. 10(3): 253-266 (2002)
52EETat Kee Tan, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha: High-level energy macromodeling of embedded software. IEEE Trans. on CAD of Integrated Circuits and Systems 21(9): 1037-1050 (2002)
2001
51EEKanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana: LOTTERYBUS: A New High-Performance Communication Architecture for System-on-Chip Designs. DAC 2001: 15-20
50EETat Kee Tan, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha: High-level Software Energy Macro-modeling. DAC 2001: 605-610
49EEWeidong Wang, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha: Input Space Adaptive Design: A High-level Methodology for Energy and Performance Optimization. DAC 2001: 738-743
48EEVijay Raghunathan, Srivaths Ravi, Anand Raghunathan, Ganesh Lakshminarayana: Transient Power Management Through High Level Synthesis. ICCAD 2001: 545-552
47EENachiketh R. Potlapally, Michael S. Hsiao, Anand Raghunathan, Ganesh Lakshminarayana, Srimat T. Chakradhar: Accurate Power Macro-modeling Techniques for Complex RTL Circuits. VLSI Design 2001: 235-241
46EEKanishka Lahiri, Sujit Dey, Anand Raghunathan: Evaluation of the Traffic-Performance Characteristics of System-on-Chip Communication Architectures. VLSI Design 2001: 29-35
45EEDebashis Panigrahi, Sujit Dey, Ramesh R. Rao, Kanishka Lahiri, Carla-Fabiana Chiasserini, Anand Raghunathan: Battery Life Estimation of Mobile Embedded Systems. VLSI Design 2001: 57-63
44 Anand Raghunathan, Sujit Dey: Low-Power Mobile Wireless Communication System Design: Protocols, Architectures, and Design Methodologies. VLSI Design 2001: 9-10
43EEKanishka Lahiri, Anand Raghunathan, Sujit Dey: System-level performance analysis for designing on-chipcommunication architectures. IEEE Trans. on CAD of Integrated Circuits and Systems 20(6): 768-783 (2001)
2000
42EERobert P. Dick, Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha: Power analysis of embedded operating systems. DAC 2000: 312-315
41EEKanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana, Sujit Dey: Communication architecture tuners: a methodology for the design of high-performance communication architectures for systems-on-chips. DAC 2000: 513-518
40EEMarcello Lajolo, Anand Raghunathan, Sujit Dey, Luciano Lavagno: Efficient Power Co-Estimation Techniques for System-on-Chip Design. DATE 2000: 27-34
39 Kanishka Lahiri, Anand Raghunathan, Sujit Dey: Efficient Exploration of the SoC Communication Architecture Design Space. ICCAD 2000: 424-430
38EEKanishka Lahiri, Sujit Dey, Anand Raghunathan: Performance Analysis of Systems with Multi-Channel Communication Architectures. VLSI Design 2000: 530-537
37EEGanesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha: Behavioral Synthesis of Fault Secure Controller/Datapaths Based on Aliasing Probability Analysis. IEEE Trans. Computers 49(9): 865-885 (2000)
36EEGanesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha: Incorporating speculative execution into scheduling ofcontrol-flow-intensive designs. IEEE Trans. on CAD of Integrated Circuits and Systems 19(3): 308-324 (2000)
1999
35EEGanesh Lakshminarayana, Anand Raghunathan, Kamal S. Khouri, Niraj K. Jha, Sujit Dey: Common-Case Computation: A High-Level Technique for Power and Performance Optimization. DAC 1999: 56-61
34EEKanishka Lahiri, Anand Raghunathan, Sujit Dey: Fast performance analysis of bus-based system-on-chip communication architectures. ICCAD 1999: 566-573
33EEPranav Ashar, Anand Raghunathan, Aarti Gupta, Subhrajit Bhattacharya: Verification of Scheduling in the Presence of Loops Using Uninterpreted Symbolic Simulation. ICCD 1999: 458-466
32 Kaushik Roy, Anand Raghunathan, Sujit Dey: Low Power Design Methodologies for Systems-on-Chips. VLSI Design 1999: 609
31EEGanesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha, Sujit Dey: Power management in high-level synthesis. IEEE Trans. VLSI Syst. 7(1): 7-15 (1999)
30EESujit Dey, Anand Raghunathan, Niraj K. Jha, Kazutoshi Wakabayashi: Controller-based power management for control-flow intensive designs. IEEE Trans. on CAD of Integrated Circuits and Systems 18(10): 1496-1508 (1999)
29EEIndradeep Ghosh, Anand Raghunathan, Niraj K. Jha: Hierarchical test generation and design for testability methods for ASPPs and ASIPs. IEEE Trans. on CAD of Integrated Circuits and Systems 18(3): 357-370 (1999)
28EEAnand Raghunathan, Sujit Dey, Niraj K. Jha: Register transfer level power optimization with emphasis on glitch analysis and reduction. IEEE Trans. on CAD of Integrated Circuits and Systems 18(8): 1114-1131 (1999)
1998
27 Sujit Dey, Anand Raghunathan, Rabindra K. Roy: Considering Testability during High-level Design (Embedded Tutorial). ASP-DAC 1998: 205-210
26EEMarcello Lajolo, Anand Raghunathan, Sujit Dey, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli: A case study on modeling shared memory access effects during performance analysis of HW/SW systems. CODES 1998: 117-121
25EEGanesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha: Incorporating Speculative Execution into Scheduling of Control-Flow Intensive Behavioral Descriptions. DAC 1998: 108-113
24EEPranav Ashar, Subhrajit Bhattacharya, Anand Raghunathan, Akira Mukaiyama: Verification of RTL generated from scheduled behavior in a high-level synthesis flow. ICCAD 1998: 517-524
23EEGanesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha, Sujit Dey: Transforming control-flow intensive designs to facilitate power management. ICCAD 1998: 657-664
22 Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha, Sujit Dey: A Power Management Methodology for High-Level Synthesis. VLSI Design 1998: 24-19
21EEIndradeep Ghosh, Anand Raghunathan, Niraj K. Jha: A design-for-testability technique for register-transfer level circuits using control/data flow extraction. IEEE Trans. on CAD of Integrated Circuits and Systems 17(8): 706-723 (1998)
20EESujit Dey, Anand Raghunathan, Kenneth D. Wagner: Design for Testability Techniques at the Behavioral and Register-Transfer Levels. J. Electronic Testing 13(2): 79-91 (1998)
1997
19EEAnand Raghunathan, Sujit Dey, Niraj K. Jha, Kazutoshi Wakabayashi: Power Management Techniques for Control-Flow Intensive Designs. DAC 1997: 429-434
18EEIndradeep Ghosh, Anand Raghunathan, Niraj K. Jha: Hierarchical Test Generation and Design for Testability of ASPPs and ASIPs. DAC 1997: 534-539
17EESrimat T. Chakradhar, Anand Raghunathan: Bottleneck removal algorithm for dynamic compaction in sequential circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 16(10): 1157-1172 (1997)
16EEAnand Raghunathan, Niraj K. Jha: SCALP: an iterative-improvement-based low-power data path synthesis system. IEEE Trans. on CAD of Integrated Circuits and Systems 16(11): 1260-1277 (1997)
15EEIndradeep Ghosh, Anand Raghunathan, Niraj K. Jha: Design for hierarchical testability of RTL circuits obtained by behavioral synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 16(9): 1001-1014 (1997)
1996
14EEAnand Raghunathan, Sujit Dey, Niraj K. Jha: Glitch Analysis and Reduction in Register Transfer Level. DAC 1996: 331-336
13 Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha: Behavioral Synthesis of Fault Secure Controller?Datapaths using Aliasing Probability Analysis. FTCS 1996: 336-345
12EEAnand Raghunathan, Sujit Dey, Niraj K. Jha: Register-transfer level estimation techniques for switching activity and power consumption. ICCAD 1996: 158-165
11EEIndradeep Ghosh, Anand Raghunathan, Niraj K. Jha: A design for testability technique for RTL circuits using control/data flow extraction. ICCAD 1996: 329-336
10EEAnand Raghunathan, Sujit Dey, Niraj K. Jha, Kazutoshi Wakabayashi: Controller re-specification to minimize switching activity in controller/data path circuits. ISLPED 1996: 301-304
9EEAnand Raghunathan, Srimat T. Chakradhar: Dynamic test Sequence compaction for Sequential Circuits. VLSI Design 1996: 170-173
1995
8EESrimat T. Chakradhar, Anand Raghunathan: Bottleneck removal algorithm for dynamic compaction and test cycles reduction. EURO-DAC 1995: 98-104
7EEAnand Raghunathan, Srimat T. Chakradhar: Acceleration techniques for dynamic vector compaction. ICCAD 1995: 310-317
6EEAnand Raghunathan, Niraj K. Jha: An iterative improvement algorithm for low power data path synthesis. ICCAD 1995: 597-602
5EEIndradeep Ghosh, Anand Raghunathan, Niraj K. Jha: Design for hierarchical testability of RTL circuits obtained by behavioral synthesis. ICCD 1995: 173-179
4 Anand Raghunathan, Niraj K. Jha: An ILP Formulation for Low Power Based on Minimizing Switched Capacitance During Data Path Allocation. ISCAS 1995: 1069-1073
3EEAnand Raghunathan, Pranav Ashar, Sharad Malik: Test generation for cyclic combinational circuits. VLSI Design 1995: 104-109
2EEAnand Raghunathan, Pranav Ashar, Sharad Malik: Test generation for cyclic combinational circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 14(11): 1408-1414 (1995)
1994
1 Anand Raghunathan, Niraj K. Jha: Behavioral Synthesis for low Power. ICCD 1994: 318-322

Coauthor Index

1Najwa Aaraj [126] [140] [146] [152] [153]
2Divya Arora [106] [111] [118] [129] [131] [136] [138]
3Pranav Ashar [2] [3] [24] [33]
4Nilanjan Banerjee [155]
5Nikhil Bansal [103] [145]
6Luca Benini [76]
7Davide Bertozzi [76]
8Subhrajit Bhattacharya [24] [33]
9J. Borel [55]
10Srimat T. Chakradhar [7] [8] [9] [17] [47] [70] [71] [90] [102] [103] [112] [114] [129] [136] [154] [156] [157]
11Saumya Chandra [123] [148] [155]
12Li Chen [79]
13Carla-Fabiana Chiasserini [45]
14Joel Coburn [105] [107] [112] [143]
15Sujit Dey [10] [12] [14] [19] [20] [22] [23] [26] [27] [28] [30] [31] [32] [34] [35] [38] [39] [40] [41] [43] [44] [45] [46] [53] [54] [58] [64] [65] [68] [69] [79] [81] [82] [83] [85] [87] [108] [123] [127] [148] [151] [155]
16Robert P. Dick [42] [67]
17Milos D. Ercegovac [57]
18Yunsi Fei [77] [80] [84] [92] [144]
19Mohammad Ali Ghodrat [147]
20Indradeep Ghosh [5] [11] [15] [18] [21] [29]
21Swaroop Ghosh [155]
22Dimitris Gizopoulos [130] [150]
23Aarti Gupta [33]
24Pallav Gupta [109]
25Sunil Hattangady [78] [89]
26Miltiadis Hatzimihail [130] [150]
27Jörg Henkel [132]
28Michael Howells [55]
29Michael S. Hsiao [47]
30Chao Huang [62] [73] [93] [99] [116] [141]
31Niraj K. Jha [1] [4] [5] [6] [10] [11] [12] [13] [14] [15] [16] [18] [19] [21] [22] [23] [25] [28] [29] [30] [31] [35] [36] [37] [42] [49] [50] [52] [56] [60] [61] [62] [66] [67] [68] [69] [72] [73] [74] [75] [77] [80] [81] [84] [86] [87] [88] [91] [92] [93] [94] [95] [96] [99] [100] [101] [102] [104] [106] [109] [110] [111] [113] [114] [115] [116] [118] [119] [120] [121] [122] [124] [125] [126] [129] [131] [133] [134] [135] [136] [137] [138] [139] [140] [141] [144] [146] [152] [153] [158]
32Ali Keshavarzi [149]
33Kamal S. Khouri [35] [87]
34Paul C. Kocher [89] [97]
35Kanishka Lahiri [34] [38] [39] [41] [43] [45] [46] [51] [54] [58] [64] [65] [82] [83] [85] [98] [103] [108] [117] [123] [127] [128] [145] [147] [148] [151]
36Marcello Lajolo [26] [40] [53]
37Ganesh Lakshminarayana [13] [22] [23] [25] [31] [35] [36] [37] [41] [42] [47] [48] [49] [50] [51] [52] [56] [67] [85] [87] [88] [100] [117]
38Luciano Lavagno [26] [40] [53]
39Ruby B. Lee [97] [122] [125] [137] [139]
40Chunxiao Li [158]
41Loganathan Lingappan [102] [114]
42Jiong Luo [80]
43Sharad Malik [2] [3]
44M. Maniatakos [150]
45Diana Marculescu [132] [149]
46Gary McGraw [97]
47Jiayuan Meng [156]
48Akira Mukaiyama [24]
49Anish Muttreja [96] [110] [124] [133] [135]
50Wolfgang Nebel [132]
51Debashis Panigrahi [45] [58]
52Antonis M. Paschalis [130] [150]
53Nachiketh R. Potlapally [47] [59] [63] [72] [120] [122] [125] [137] [139]
54Mihalis Psarakis [130] [150]
55Jean-Jacques Quisquater [78]
56Vijay Raghunathan [48] [57]
57Janusz Rajski [55]
58Ramesh R. Rao [45]
59Srivaths Ravi [48] [59] [61] [62] [63] [70] [71] [72] [73] [74] [76] [77] [78] [79] [84] [86] [89] [90] [92] [93] [94] [96] [97] [99] [102] [104] [105] [106] [107] [109] [110] [111] [112] [113] [114] [115] [116] [118] [119] [120] [121] [122] [124] [125] [126] [129] [130] [131] [133] [134] [135] [136] [137] [138] [139] [140] [141] [143] [144] [146] [150]
60Kaushik Roy [32] [155]
61Rabindra K. Roy [27]
62Alberto L. Sangiovanni-Vincentelli [26]
63Murugan Sankaradass [63] [129] [136]
64Patrick Schaumont [142]
65Krishna Sekar [108] [127] [151]
66Li Shang [80]
67Jim Sproch [55]
68Mani B. Srivastava [57]
69Mircea R. Stan [132]
70Phillip Stanley-Marbell [128]
71Fei Sun [61] [74] [86] [104] [113] [119] [121] [134]
72Narayanan Sundaram [157]
73Tat Kee Tan [50] [52] [60] [66] [75] [80] [95] [101]
74Janar Thoguluva [154]
75Keith S. Vallerio [80]
76Narayanan Vijaykrishnan (Vijaykrishnan Narayanan) [149]
77Kenneth D. Wagner [20]
78Kazutoshi Wakabayashi [10] [19] [30]
79Weidong Wang [49] [56] [69] [80] [81] [88] [91] [100]
80Lin Zhong [80] [94] [115]

Colors in the list of coauthors

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)