| |
| 2007 | ||
|---|---|---|
| 4 | EE | Bill Pontikakis, Hung Tien Bui, François R. Boyer, Yvon Savaria: A Low-Complexity High-Speed Clock Generator for Dynamic Frequency Scaling of FPGA and Standard-Cell Based Designs. ISCAS 2007: 633-636 |
| 2006 | ||
| 3 | EE | Bill Pontikakis, François R. Boyer, Yvon Savaria: A 0.8V algorithmically defined buffer and ring oscillator low-energy design for nanometer SoCs. ISCAS 2006 |
| 2005 | ||
| 2 | EE | Bill Pontikakis, François R. Boyer, Yvon Savaria: Performance Improvement of Configurable Processor Architectures Using a Variable Clock Period. IWSOC 2005: 454-458 |
| 2002 | ||
| 1 | EE | Bill Pontikakis, Mohamed Nekili: A novel double edge-triggered pulse-clocked TSPC D flip-flop for high-performance and low-power VLSI design applications. ISCAS (5) 2002: 101-104 |
| 1 | François R. Boyer | [2] [3] [4] |
| 2 | Hung Tien Bui | [4] |
| 3 | Mohamed Nekili | [1] |
| 4 | Yvon Savaria | [2] [3] [4] |