Vijay Pitchumani

2007
26	EE	Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Shan Zeng, Jinian Bian, Wenjian Yu, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng: Efficient Thermal via Planning Approach and Its Application in 3-D Floorplanning. IEEE Trans. on CAD of Integrated Circuits and Systems 26(4): 645-658 (2007)
2006
25	EE	Vijay Pitchumani: A Hitchhiker's Guide to the DFM Universe. APCCAS 2006: 1103-1106
24	EE	Sani R. Nassif, Vijay Pitchumani, N. Rodriguez, Dennis Sylvester, Clive Bittlestone, Riko Radojcic: Variation-aware analysis: savior of the nanometer era? DAC 2006: 411-412
23	EE	Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Shan Zeng, Jinian Bian, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng: Integrating dynamic thermal via planning with 3D floorplanning algorithm. ISPD 2006: 178-185
22	EE	Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Jinian Bian, Hannah Honghua Yang, Vijay Pitchumani: Efficient thermal-oriented 3D floorplanning and thermal via planning for two-stacked-die integration. ACM Trans. Design Autom. Electr. Syst. 11(2): 325-345 (2006)
2005
21	EE	Vijay Pitchumani: Embedded tutorial I: design for manufacturability. ASP-DAC 2005
20	EE	C. K. Cheng, Steve Lin, Andrew B. Kahng, Keh-Jeng Chang, Vijay Pitchumani, Toshiyuki Shibuya, Roberto Suaya, Zhiping Yu, Fook-Luen Heng, Don MacMillen: Panel I: who is responsible for the design for manufacturability issues in the era of nano-technologies? ASP-DAC 2005
19	EE	Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Yici Cai, Jinian Bian, Hannal Yang, Prashant Saxena, Vijay Pitchumani: A divide-and-conquer 2.5-D floorplanning algorithm based on statistical wirelength estimation. ISCAS (6) 2005: 6230-6233
1999
18	EE	Mehmet Emin Dalkiliç, Vijay Pitchumani: Multi-schedule design space exploration: an alternative synthesis framework. Integration 27(2): 87-112 (1999)
1995
17		M. Kemal Unaltuna, Vijay Pitchumani: ANSA: A New Neural Net Based Scheduling Algorithm for High Level Synthesis. ISCAS 1995: 385-388
1994
16		Mehmet Emin Dalkiliç, Vijay Pitchumani: Optimal Operation Scheduling Using Resource Lower Bound Estimations. EDAC-ETC-EUROASIC 1994: 319-324
15		Mehmet Emin Dalkiliç, Vijay Pitchumani: A Multi-Schedule Approach to High-Level Synthesis. ICCD 1994: 572-575
14		M. Kemal Unaltuna, Vijay Pitchumani: A Stochastic Reward & Punishment Neural Network Algorithm for Circuit Bipartitioning. ISCAS 1994: 181-184
13		Neeta Ganguly, Vijay Pitchumani: HSIM1 and HSIM2: Object Oriented Algorithms for VHDL Simulation. VLSI Design 1994: 175-178
1993
12		M. Kemal Unaltuna, Vijay Pitchumani: Quadrisectioning Based Placement with a Normalized Mean Field Neural Network. ISCAS 1993: 2047-2050
1992
11	EE	Vijay Pitchumani, Pankaj Mayor, Nimish Radia: A VHDL Fault Diagnosis Tool Using Functional Fault Models. IEEE Design & Test of Computers 9(2): 33-41 (1992)
1991
10	EE	Vijay Pitchumani, Pankaj Mayor, Nimish Radia: A System for Fault Diagnosis and Simulation of VHDL Descriptions. DAC 1991: 144-150
9		Vijay Pitchumani, Pankaj Mayor, Nimish Radia: Fault Diagnosis using Functional Fault Models for VHDL descriptions. ITC 1991: 327-337
1989
8	EE	Vinod Narayanan, Vijay Pitchumani: A Massively Parallel Algorithm for Fault Simulation on the Connection Machine. DAC 1989: 734-737
7	EE	S. Ganguly, Vijay Pitchumani: Compaction of a Routed Channel on the Connection Machine. DAC 1989: 779-782
1988
6		Vinod Narayanan, Vijay Pitchumani: : A Parallel Algorithm for Fault Simulation on the Connection Machine. ITC 1988: 89-93
5		Vijay Pitchumani, Satish S. Soman: Functional Test Generation Based on Unate Function Theory. IEEE Trans. Computers 37(6): 756-760 (1988)
1987
4	EE	Vijay Pitchumani, Qisui Zhang: A Mixed HVH-VHV Algorithm for Three-Layer Channel Routing. IEEE Trans. on CAD of Integrated Circuits and Systems 6(4): 497-502 (1987)
1985
3		Zerksis D. Umrigar, Vijay Pitchumani: An Experiment in Programming with Full First-Order Logic. SLP 1985: 40-47
2		Vijay Pitchumani, Edward P. Stabler: Verification of Register Transfer Level Parallel Control Sequences. IEEE Trans. Computers 34(8): 761-765 (1985)
1983
1		Vijay Pitchumani, Edward P. Stabler: An Inductive Assertion Method for Register Transfer Level Design Verification. IEEE Trans. Computers 32(12): 1073-1080 (1983)

Coauthor Index

1	Jinian Bian	[19] [22] [23] [26]
2	Clive Bittlestone	[24]
3	Yici Cai	[19]
4	Keh-Jeng Chang	[20]
5	C. K. Cheng	[20]
6	Chung-Kuan Cheng	[23] [26]
7	Mehmet Emin Dalkiliç	[15] [16] [18]
8	Neeta Ganguly	[13]
9	S. Ganguly	[7]
10	Fook-Luen Heng	[20]
11	Xianlong Hong	[19] [22] [23] [26]
12	Andrew B. Kahng	[20]
13	Zhuoyuan Li	[19] [22] [23] [26]
14	Steve Lin	[20]
15	Don MacMillen	[20]
16	Pankaj Mayor	[9] [10] [11]
17	Vinod Narayanan	[6] [8]
18	Sani R. Nassif	[24]
19	Nimish Radia	[9] [10] [11]
20	Riko Radojcic	[24]
21	N. Rodriguez	[24]
22	Prashant Saxena	[19]
23	Toshiyuki Shibuya	[20]
24	Satish S. Soman	[5]
25	Edward P. Stabler (Edward P. Stabler Jr.)	[1] [2]
26	Roberto Suaya	[20]
27	Dennis Sylvester	[24]
28	Zerksis D. Umrigar	[3]
29	M. Kemal Unaltuna	[12] [14] [17]
30	Hannah Honghua Yang	[22] [23] [26]
31	Hannal Yang	[19]
32	Wenjian Yu	[26]
33	Zhiping Yu	[20]
34	Shan Zeng	[23] [26]
35	Qisui Zhang	[4]
36	Qiang Zhou	[19] [22] [23] [26]

Colors in the list of coauthors