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Janak H. Patel Vis

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*2005
166EELiyang Lai, Janak H. Patel, Thomas Rinderknecht, Wu-Tung Cheng: Hardware Ef.cient LBISTWith Complementary Weights. ICCD 2005: 479-484
2004
165 Ravishankar K. Iyer, William H. Sanders, Janak H. Patel, Zbigniew Kalbarczyk: The evolution of dependable computing at the University of Illinois. IFIP Congress Topical Sessions 2004: 135-164
164EEMihir A. Shah, Janak H. Patel: Enhancement of the Illinois Scan Architecture for Use with Multiple Scan Inputs. ISVLSI 2004: 167-172
163EELiyang Lai, Janak H. Patel, Thomas Rinderknecht, Wu-Tung Cheng: Logic BIST with Scan Chain Segmentation. ITC 2004: 57-66
162EELiyang Lai, Thomas Rinderknecht, Wu-Tung Cheng, Janak H. Patel: Logic BIST Using Constrained Scan Cells. VTS 2004: 199-205
161EEManish Sharma, Janak H. Patel: What Does Robust Testing a Subset of Paths, Tell us about the Untested Paths in the Circuit? VTS 2004: 31-36
160EEDong Xiang, Janak H. Patel: Partial Scan Design Based on Circuit State Information and Functional Analysis. IEEE Trans. Computers 53(3): 276-287 (2004)
2003
159EEJanak H. Patel, Steven S. Lumetta, Sudhakar M. Reddy: Application of Saluja-Karpovsky Compactors to Test Responses with Many Unknowns. VTS 2003: 107-112
158EEManish Sharma, Janak H. Patel, Jeff Rearick: Test Data Compression and Test Time Reduction of Longest-Path-Per-Gate Tests based on Illinois Scan Architecture. VTS 2003: 15-21
2002
157EEAmit R. Pandey, Janak H. Patel: An Incremental Algorithm for Test Generation in Illinois Scan Architecture Based Designs. DATE 2002: 368-375
156EEManish Sharma, Janak H. Patel: Finding a Small Set of Longest Testable Paths that Cover Every Gate. ITC 2002: 974-982
155EEAmit R. Pandey, Janak H. Patel: Reconfiguration Technique for Reducing Test Time and Test Data Volume in Illinois Scan Architecture Based Designs . VTS 2002: 9-15
2001
154 Frank F. Hsu, Kenneth M. Butler, Janak H. Patel: A case study on the implementation of the Illinois Scan Architecture. ITC 2001: 538-547
153 Manish Sharma, Janak H. Patel: Testing of critical paths for delay faults. ITC 2001: 634-641
152EEJian-Kun Zhao, Jeffrey A. Newquist, Janak H. Patel: A Graph Traversal Based Framework For Sequential Logic Implication With An Application To C-Cycle Redundancy Identification. VLSI Design 2001: 163-
151EEIsmed Hartanto, Srikanth Venkataraman, W. Kent Fuchs, Elizabeth M. Rudnick, Janak H. Patel, Sreejit Chakravarty: Diagnostic simulation of stuck-at faults in sequential circuits using compact lists. ACM Trans. Design Autom. Electr. Syst. 6(4): 471-489 (2001)
2000
150 Ilker Hamzaoglu, Janak H. Patel: Deterministic Test Pattern Generation Techniques for Sequential Circuits. ICCAD 2000: 538-543
149 Manish Sharma, Janak H. Patel: Enhanced delay defect coverage with path-segments. ITC 2000: 385-392
148EEManish Sharma, Janak H. Patel: Bounding Circuit Delay by Testing a Very Small Subset of Paths. VTS 2000: 333-342
147EEIlker Hamzaoglu, Janak H. Patel: Reducing Test Application Time for Built-in-Self-Test Test Pattern Generators. VTS 2000: 369-376
146EEMichael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel: Dynamic state traversal for sequential circuit test generation. ACM Trans. Design Autom. Electr. Syst. 5(3): 548-565 (2000)
145EEMichael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel: Peak power estimation of VLSI circuits: new peak power measures. IEEE Trans. VLSI Syst. 8(4): 435-439 (2000)
144EEIlker Hamzaoglu, Janak H. Patel: Test set compaction algorithms for combinational circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 19(8): 957-963 (2000)
1999
143EEIlker Hamzaoglu, Janak H. Patel: Reducing Test Application Time for Full Scan Embedded Cores. FTCS 1999: 260-267
142 Zbigniew Kalbarczyk, Janak H. Patel, Myeong S. Lee, Ravishankar K. Iyer: An Approach to Evaluating the Effects of Realistic Faults in Digital Circuits. VLSI Design 1999: 260-265
141EEKeerthi Heragu, Janak H. Patel, Vishwani D. Agrawal: A Test Generator for Segment Delay Faults. VLSI Design 1999: 484-491
140 Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel: Fast Static Compaction Algorithms for Sequential Circuit Test Vectors. IEEE Trans. Computers 48(3): 311-322 (1999)
139 Elizabeth M. Rudnick, Janak H. Patel: Efficient Techniques for Dynamic Test Sequence Compaction. IEEE Trans. Computers 48(3): 323-330 (1999)
138EEIlker Hamzaoglu, Janak H. Patel: New Techniques for Deterministic Test Pattern Generation. J. Electronic Testing 15(1-2): 63-73 (1999)
1998
137EEJanak H. Patel, Edward S. Davidson: Improving the Throughput of a Pipeline by Insertion of Delays. 25 Years ISCA: Retrospectives and Reprints 1998: 132-137
136EEMark S. Papamarcos, Janak H. Patel: A Low-Overhead Coherence Solution for Multiprocessors with Private Cache Memories. 25 Years ISCA: Retrospectives and Reprints 1998: 284-290
135EEJanak H. Patel: Retrospective: A Low-Overhead Coherence Solution for Multiprocessors with Private Cache Memories. 25 Years ISCA: Retrospectives and Reprints 1998: 39-41
134EEJanak H. Patel: Retrospective: Improving the Throughput of a Pipeline by Insertion of Delays. 25 Years ISCA: Retrospectives and Reprints 1998: 5
133EEIlker Hamzaoglu, Janak H. Patel: Test set compaction algorithms for combinational circuits. ICCAD 1998: 283-289
132EEFrank F. Hsu, Janak H. Patel: High-level variable selection for partial-scan implementation. ICCAD 1998: 79-84
131EEIlker Hamzaoglu, Janak H. Patel: Compact two-pattern test set generation for combinational and full scan circuits. ITC 1998: 944-953
130EEMichael S. Hsiao, Gurjeet S. Saund, Elizabeth M. Rudnick, Janak H. Patel: Partial Scan Selection Based on Dynamic Reachability and Observability Information. VLSI Design 1998: 174-180
129EESrikanth Venkataraman, W. Kent Fuchs, Janak H. Patel: Diagnostic Simulation of Sequential Circuits Using Fault Sampling. VLSI Design 1998: 476-481
128EEIlker Hamzaoglu, Janak H. Patel: New Techniques for Deterministic Test Pattern Generation. VTS 1998: 446-452
127EEMichael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel: Application of genetically engineered finite-state-machine sequences to sequential circuit ATPG. IEEE Trans. on CAD of Integrated Circuits and Systems 17(3): 239-254 (1998)
126EEFrank F. Hsu, Janak H. Patel: High-Level Controllability and Observability Analysis for Test Synthesis. J. Electronic Testing 13(2): 93-103 (1998)
1997
125EEMichael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel: Sequential circuit test generation using dynamic state traversal. ED&TC 1997: 22-28
124 Gurjeet S. Saund, Michael S. Hsiao, Janak H. Patel: Partial Scan beyond Cycle Cutting. FTCS 1997: 320-328
123EEMichael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel: Effects of delay models on peak power estimation of VLSI sequential circuits. ICCAD 1997: 45-51
122EEKeerthi Heragu, Janak H. Patel, Vishwani D. Agrawal: Fast identification of untestable delay faults using implications. ICCAD 1997: 642-647
121EEMichael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel: K2: an estimator for peak sustainable power of VLSI circuits. ISLPED 1997: 178-183
120 Elizabeth M. Rudnick, Janak H. Patel: Putting the Squeeze on Test Sequences. ITC 1997: 723-732
119 James P. Cusey, Janak H. Patel: BART: A Bridging Fault Test Generation for Sequential Circuits. ITC 1997: 838-847
118EEDilip Krishnaswamy, Michael S. Hsiao, Vikram Saxena, Elizabeth M. Rudnick, Janak H. Patel, Prithviraj Banerjee: Parallel Genetic Algorithms for Simulation-Based Sequential Circuit Test Generation. VLSI Design 1997: 475-481
117EEElizabeth M. Rudnick, Janak H. Patel: Overcoming the Serial Logic Simulation Bottleneck in Parallel Fault Simulation. VLSI Design 1997: 495-503
116EECharles R. Graham, Elizabeth M. Rudnick, Janak H. Patel: Dynamic Fault Grouping for PROOFS: A Win for Large Sequential Circuits. VLSI Design 1997: 542-544
115EEMichael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel: Fast Algorithms for Static Compaction of Sequential Circuit Test Vectors. VTS 1997: 188-195
114EEIsmed Hartanto, Vamsi Boppana, Janak H. Patel, W. Kent Fuchs: Diagnostic Test Pattern Generation for Sequential Circuits. VTS 1997: 196-202
113EEDilip Krishnaswamy, Elizabeth M. Rudnick, Janak H. Patel, Prithviraj Banerjee: SPITFIRE: scalable parallel algorithms for test set partitioned fault simulation. VTS 1997: 274-281
112EEJian-Kun Zhao, Elizabeth M. Rudnick, Janak H. Patel: Static logic implication with application to redundancy identification. VTS 1997: 288-295
111EEDilip Krishnaswamy, Prithviraj Banerjee, Elizabeth M. Rudnick, Janak H. Patel: Asynchronous Parallel Algorithms for Test Set Partitioned Fault Simulation. Workshop on Parallel and Distributed Simulation 1997: 30-37
110EEPaul J. Thadikaran, Sreejit Chakravarty, Janak H. Patel: Algorithms to compute bridging fault coverage of IDDQ test sets. ACM Trans. Design Autom. Electr. Syst. 2(3): 281-305 (1997)
109EEKeerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell, Janak H. Patel: Improving a nonenumerative method to estimate path delay fault coverage. IEEE Trans. on CAD of Integrated Circuits and Systems 16(7): 759-762 (1997)
108EEElizabeth M. Rudnick, Janak H. Patel, Gary S. Greenstein, Thomas M. Niermann: A genetic algorithm framework for test generation. IEEE Trans. on CAD of Integrated Circuits and Systems 16(9): 1034-1044 (1997)
107EEFrank F. Hsu, Janak H. Patel: Design for Testability Using State Distances. J. Electronic Testing 11(1): 93-100 (1997)
1996
106EEDong Xiang, Srikanth Venkataraman, W. Kent Fuchs, Janak H. Patel: Partial Scan Design Based on Circuit State Information. DAC 1996: 807-812
105EEIrith Pomeranz, Sudhakar M. Reddy, Janak H. Patel: On Double Transition Faults as a Delay Fault Model. Great Lakes Symposium on VLSI 1996: 282-287
104EEFrank F. Hsu, Elizabeth M. Rudnick, Janak H. Patel: Enhancing high-level control-flow for improved testability. ICCAD 1996: 322-328
103EEKeerthi Heragu, Janak H. Patel, Vishwani D. Agrawal: SIGMA: a simulator for segment delay faults. ICCAD 1996: 502-508
102EEElizabeth M. Rudnick, Janak H. Patel: Simulation-based techniques for dynamic test sequence compaction. ICCAD 1996: 67-73
101EEFrank F. Hsu, Elizabeth M. Rudnick, Janak H. Patel: Testability Insertion in Behavioral Descriptions. ISSS 1996: 139-144
100 Elizabeth M. Rudnick, Janak H. Patel, Irith Pomeranz: On Potential Fault Detection in Sequential Circuits. ITC 1996: 142-149
99 Dong Xiang, Janak H. Patel: A Global Algorithm for the Partial Scan Design Problem Using Circuit State Information. ITC 1996: 548-557
98EEKeerthi Heragu, Janak H. Patel, Vishwani D. Agrawal: Improving accuracy in path delay fault coverage estimation. VLSI Design 1996: 422-425
97EEMichael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel: Automatic test generation using genetically-engineered distinguishing sequences. VTS 1996: 216-223
96EEKeerthi Heragu, Janak H. Patel, Vishwani D. Agrawal: Segment delay faults: a new fault model. VTS 1996: 32-41
95EETerry Lee, Ibrahim N. Hajj, Elizabeth M. Rudnick, Janak H. Patel: Genetic-algorithm-based test generation for current testing of bridging faults in CMOS VLSI circuits. VTS 1996: 456-462
94 Hungse Cha, Elizabeth M. Rudnick, Janak H. Patel, Ravishankar K. Iyer, Gwan S. Choi: A Gate-Level Simulation Environment for Alpha-Particle-Induced Transient Faults. IEEE Trans. Computers 45(11): 1248-1256 (1996)
93EEJaushin Lee, Janak H. Patel: Hierarchical test generation under architectural level functional constraints. IEEE Trans. on CAD of Integrated Circuits and Systems 15(9): 1144-1151 (1996)
1995
92EEEiji Harada, Janak H. Patel: Overhead reduction techniques for hierarchical fault simulation. Asian Test Symposium 1995: 79-85
91EESrikanth Venkataraman, Ismed Hartanto, W. Kent Fuchs, Elizabeth M. Rudnick, Sreejit Chakravarty, Janak H. Patel: Rapid Diagnostic Fault Simulation of Stuck-at Faults in Sequential Circuits Using Compact Lists. DAC 1995: 133-138
90EEElizabeth M. Rudnick, Janak H. Patel: Combining Deterministic and Genetic Approaches for Sequential Circuit Test Generation. DAC 1995: 183-188
89 Paul J. Thadikaran, Sreejit Chakravarty, Janak H. Patel: Fault Simulation ofIDDQ Tests for Bridging Faults in Sequential Circuits. FTCS 1995: 340-349
88EESteven Parkes, Prithviraj Banerjee, Janak H. Patel: A parallel algorithm for fault simulation based on PROOFS . ICCD 1995: 616-
87EEMichael S. Hsiao, Janak H. Patel: A new architectural-level fault simulation using propagation prediction of grouped fault-effects. ICCD 1995: 628-
86EEElizabeth M. Rudnick, Janak H. Patel: A genetic approach to test application time reduction for full scan and partial scan circuits. VLSI Design 1995: 288-293
85EEFrank F. Hsu, Janak H. Patel: A distance reduction approach to design for testability. VTS 1995: 158-163
84EEVinay Dabholkar, Sreejit Chakravarty, J. Najm, Janak H. Patel: Cyclic stress tests for full scan circuits. VTS 1995: 89-94
83EEElizabeth M. Rudnick, Vivek Chickermane, Prithviraj Banerjee, Janak H. Patel: Sequential circuit testability enhancement using a nonscan approach. IEEE Trans. VLSI Syst. 3(2): 333-338 (1995)
1994
82EEJacob A. Abraham, Sandip Kundu, Janak H. Patel, Manuel A. d'Abreu, Bulent I. Dervisoglu, Marc E. Levitt, Hector R. Sucar, Ron G. Walther: Microprocessor Testing: Which Technique is Best? (Panel). DAC 1994: 294
81EEElizabeth M. Rudnick, Janak H. Patel, Gary S. Greenstein, Thomas M. Niermann: Sequential Circuit Test Generation in a Genetic Algorithm Framework. DAC 1994: 698-704
80EESteven Parkes, Prithviraj Banerjee, Janak H. Patel: ProperHITEC: A Portable, Parallel, Object-Oriented Approach to Sequential Test Generation. DAC 1994: 717-721
79 Elizabeth M. Rudnick, John G. Holm, Daniel G. Saab, Janak H. Patel: Application of Simple Genetic Algorithms to Sequential Circuit Test Generation. EDAC-ETC-EUROASIC 1994: 40-45
78 John W. C. Fu, Janak H. Patel: Trace Driven Simulation using Sampled Traces. HICSS (1) 1994: 211-220
77EEAbhijit Dharchoudhury, Sung-Mo Kang, Hungse Cha, Janak H. Patel: Fast timing simulation of transient faults in digital circuits. ICCAD 1994: 719-722
76 Hungse Cha, Janak H. Patel: Latch Design for Transient Pulse Tolerance. ICCD 1994: 385-388
75 Jeff Baxter, John W. C. Fu, Balkrishna Ramkumar, Janak H. Patel: Hybrid Resource Management Algorithms for Multicomputer Systems. IPPS 1994: 482-489
74EEJaushin Lee, Janak H. Patel: Architectural level test generation for microprocessors. IEEE Trans. on CAD of Integrated Circuits and Systems 13(10): 1288-1300 (1994)
73EEVivek Chickermane, Jaushin Lee, Janak H. Patel: Addressing design for testability at the architectural level. IEEE Trans. on CAD of Integrated Circuits and Systems 13(7): 920-934 (1994)
72EEElizabeth M. Rudnick, Vivek Chickermane, Janak H. Patel: An observability enhancement approach for improved testability and at-speed test. IEEE Trans. on CAD of Integrated Circuits and Systems 13(8): 1051-1056 (1994)
1993
71EEVivek Chickermane, Elizabeth M. Rudnick, Prithviraj Banerjee, Janak H. Patel: Non-Scan Design-for-Testability Techniques for Sequential Circuits. DAC 1993: 236-241
70 Hungse Cha, Elizabeth M. Rudnick, Gwan S. Choi, Janak H. Patel, Ravishankar K. Iyer: A Fast and Accurate Gate-Level Transient Fault Simulation Environment. FTCS 1993: 310-319
69 Irith Pomeranz, Sudhakar M. Reddy, Janak H. Patel: Theory and Practice of Sequential Machine Testing and Testability. FTCS 1993: 330-337
68 Hungse Cha, Janak H. Patel: A Logic-Level Model for alpha-Paricle Hits in CMOS Circuits. ICCD 1993: 538-542
67 John W. C. Fu, Janak H. Patel: Memory Reference Behavior of Compiler Optimized Programs on High Speed. ICPP 1993: 87-94
66 Pi-Yu Chung, Ibrahim N. Hajj, Janak H. Patel: Efficient Variable Ordering Heuristics for Shared ROBDD. ISCAS 1993: 1690-1693
65 Jeff Rearick, Janak H. Patel: Fast and Accurate CMOS Bridging Fault Simulation. ITC 1993: 54-62
64EEAlok N. Choudhary, Janak H. Patel, Narendra Ahuja: NETRA: A Hierarchical and Partitionable Architecture for Computer Vision Systems. IEEE Trans. Parallel Distrib. Syst. 4(10): 1092-1104 (1993)
63EEJaushin Lee, Janak H. Patel: An architectural level test generator based on nonlinear equation solving. J. Electronic Testing 4(2): 137-150 (1993)
1992
62EESungho Kim, Prithviraj Banerjee, Vivek Chickermane, Janak H. Patel: APT: An Area-Performance-Testability Driven Placement Algorithm. DAC 1992: 141-146
61EEJaushin Lee, Janak H. Patel: Hierarchical Test Generation under Intensive Global Functional Constraints. DAC 1992: 261-266
60EERabindra K. Roy, Abhijit Chatterjee, Janak H. Patel, Jacob A. Abraham, Manuel A. d'Abreu: Automatic test generation for linear digital systems with bi-level search using matrix transform methods. ICCAD 1992: 224-228
59EEGary S. Greenstein, Janak H. Patel: E-PROOFS: a CMOS bridging fault simulator. ICCAD 1992: 268-271
58EEVivek Chickermane, Jaushin Lee, Janak H. Patel: A comparative study of design for testability methods using high-level and gate-level descriptions. ICCAD 1992: 620-624
57 Jeff Baxter, Balkrishna Ramkumar, Janak H. Patel: Compile Time Parallel Resource Allocation for Unbounded Tree Structure Task Graphs. ICPP (1) 1992: 202-209
56 Jeff Baxter, Janak H. Patel: Profiling Based Task Migration. IPPS 1992: 192-195
55 Elizabeth M. Rudnick, W. Kent Fuchs, Janak H. Patel: Diagnostic Fault Simulation of Sequential Circuits. ITC 1992: 178-186
54 Jaushin Lee, Janak H. Patel: An Instruction Sequence Assembling Methodology for Testing Microprocessors. ITC 1992: 49-58
53 Vivek Chickermane, Jaushin Lee, Janak H. Patel: Design for Testability Using Architectural Descriptions. ITC 1992: 752-761
52EEJohn W. C. Fu, Janak H. Patel, Bob L. Janssens: Stride directed prefetching in scalar processors. MICRO 1992: 102-110
51EEThomas M. Niermann, Wu-Tung Cheng, Janak H. Patel: PROOFS: a fast, memory-efficient sequential circuit fault simulator. IEEE Trans. on CAD of Integrated Circuits and Systems 11(2): 198-207 (1992)
50EEThomas M. Niermann, Rabindra K. Roy, Janak H. Patel, Jacob A. Abraham: Test compaction for sequential circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 11(2): 260-267 (1992)
49EEPinaki Mazumder, Janak H. Patel: An efficient design of embedded memories and their testability analysis using Markov chains. J. Electronic Testing 3(3): 235-250 (1992)
1991
48EESrinivas Patil, Prithviraj Banerjee, Janak H. Patel: Parallel Test Generation for Sequential Circuits on General-Purpose Multiprocessors. DAC 1991: 155-159
47 Jaushin Lee, Janak H. Patel: An Architectural Level Test Generator for a Hierarchical Design Environment. FTCS 1991: 44-51
46 Vivek Chickermane, Janak H. Patel: A Fault Oriented Partial Scan Design Approach. ICCAD 1991: 400-403
45 Jaushin Lee, Janak H. Patel: A Signal-Driven Discrete Relaxation Technique for Architectural Level Test Generation. ICCAD 1991: 458-461
44 Elizabeth M. Rudnick, Thomas M. Niermann, Janak H. Patel: Methods for Reducing Events in Sequential Circuit Fault Simulation. ICCAD 1991: 546-549
43 John W. C. Fu, Janak H. Patel: Data Prefetching Strategies for Vector Cache Memories. IPPS 1991: 555-560
42 Alfred Brenner, Richard F. Freund, R. Stockton Gaines, Rob Kelly, Louis Lome, Richard McAndrew, Alexandru Nicolau, Janak H. Patel, Thomas Probert, John H. Reif, Jorge L. C. Sanz, Howard Jay Siegel, Jon A. Webb: How Do We Make Parallel Processing a Reality? Bridging the Gap Between Theory and Practice. IPPS 1991: 648-653
41EEJohn W. C. Fu, Janak H. Patel: Data Prefetching in Multiprocessor Vector Cache Memories. ISCA 1991: 54-63
40 Jaushin Lee, Janak H. Patel: ARTEST: An Architectural Level Test Generator for Data Path Faults and Control Faults. ITC 1991: 729-738
1990
39EEThomas M. Niermann, Wu-Tung Cheng, Janak H. Patel: Proofs: A Fast, Memory Efficient Sequential Circuit Fault Simulator. DAC 1990: 535-540
38EEWu-Tung Cheng, Janak H. Patel: PROOFS: a super fast fault simulator for sequential circuits. EURO-DAC 1990: 475-479
37 Alok N. Choudhary, Janak H. Patel: Performance Evaluation of Clusters of NETRA: An Architecture for Computer Vision Systems. ICPP (1) 1990: 494-497
36EEKun-Lung Wu, W. Kent Fuchs, Janak H. Patel: Error Recovery in Shared Memory Multiprocessors Using Private Caches. IEEE Trans. Parallel Distrib. Syst. 1(2): 231-240 (1990)
1989
35EEU. J. Davé, Janak H. Patel: A Functional-Level Test Generation Methodology Using Two-level Representations. DAC 1989: 722-725
34 Kun-Lung Wu, W. Kent Fuchs, Janak H. Patel: Cache-Based Error Recovery for Shared Memory Multiprocessor Systems. ICPP (1) 1989: 159-166
33 Jeff Baxter, Janak H. Patel: The LAST Algorithm: A Heuristic-Based Static Task Allocation Algorithm. ICPP (2) 1989: 217-222
32 Pinaki Mazumder, Janak H. Patel: Parallel Testing for Pattern-Sensitive Faults in Semiconductor Random-Access Memories. IEEE Trans. Computers 38(3): 394-407 (1989)
31 Ming-Feng Chang, W. Kent Fuchs, Janak H. Patel: Diagnosis and Repair of Memory with Coupling Faults. IEEE Trans. Computers 38(4): 493-500 (1989)
30EESusheel J. Chandra, Janak H. Patel: Experimental evaluation of testability measures for test generation (logic circuits). IEEE Trans. on CAD of Integrated Circuits and Systems 8(1): 93-97 (1989)
1988
29 Alok N. Choudhary, Janak H. Patel: A Parallel Processing Architecture for an Integrated Vision System. ICPP (1) 1988: 383-387
28 Richard J. Eickemeyer, Janak H. Patel: Performance Evaluation of On-Chip Register and Cache Organizations. ISCA 1988: 64-72
27 Subhasis Laha, Janak H. Patel, Ravishankar K. Iyer: Accurate Low-Cost Methods for Performance Evaluation of Cache Memory Systems. IEEE Trans. Computers 37(11): 1325-1336 (1988)
26EEPinaki Mazumder, Janak H. Patel, W. Kent Fuchs: Methodologies for testing embedded content addressable memories. IEEE Trans. on CAD of Integrated Circuits and Systems 7(1): 11-20 (1988)
1987
25EESusheel J. Chandra, Janak H. Patel: A Hierarchical Approach Test Vector Generation. DAC 1987: 495-501
24EEPinaki Mazumder, Janak H. Patel, W. Kent Fuchs: Design and Algorithms for Parallel Testing of Random Access and Content Addressable Memories. DAC 1987: 689-694
23 Santosh G. Abraham, Janak H. Patel: Parallel Garbage Collection on a Virtual Memory System. ICPP 1987: 243-246
22 Richard J. Eickemeyer, Janak H. Patel: Performance Evaluation of Multiple Register Sets. ISCA 1987: 264-271
21 Wu-Tung Cheng, Janak H. Patel: A Minimum Test Set for Multiple Fault Detection in Ripple Carry Adders. IEEE Trans. Computers 36(7): 891-895 (1987)
1986
20EESanjay J. Patel, Janak H. Patel: Effectiveness of heuristics measures for automatic test pattern generation. DAC 1986: 547-552
19 Mohammad Malkawi, Janak H. Patel: Performance Measurement of Paging Behavior in Multiprogramming Systems. ISCA 1986: 111-118
1985
18 Ashwin Ram, Janak H. Patel: Parallel Garbage Collection Without Synchronization Overhead. ISCA 1985: 84-90
17 Gurindar S. Sohi, Edward S. Davidson, Janak H. Patel: An Efficient LISP-Execution Architecture with a New Representation for List Structures. ISCA 1985: 91-98
16 Wu-Tung Cheng, Janak H. Patel: Multiple-Fault Detection in Iterative Logic Arrays. ITC 1985: 493-499
15 Mohammad Malkawi, Janak H. Patel: Compiler Directed Memory Management Policy For Numerical Programs. SOSP 1985: 97-106
1984
14 Mark S. Papamarcos, Janak H. Patel: A Low-Overhead Coherence Solution for Multiprocessors with Private Cache Memories. ISCA 1984: 348-354
13 Ramaswami Dandapani, Janak H. Patel, Jacob A. Abraham: Design of Test Pattern Generators for Built-In Test. ITC 1984: 315-319
1983
12 Phil C. C. Yeh, Janak H. Patel, Edward S. Davidson: Performance of Shared Cache for Parallel-Pipelined Computer Systems ISCA 1983: 117-123
11 Phil C. C. Yeh, Janak H. Patel, Edward S. Davidson: Shared Cache for Multiple-Stream Computer Systems. IEEE Trans. Computers 32(1): 38-47 (1983)
10 Janak H. Patel, Leona Y. Fung: Concurrent Error Detection in Multiply and Divide Arrays. IEEE Trans. Computers 32(4): 417-422 (1983)
1982
9 Gregory F. Grohoski, Janak H. Patel: A performance model for instruction prefetch in pipelined instruction units. ICPP 1982: 248-252
8 David W. L. Yen, Janak H. Patel, Edward S. Davidson: Memory Interference in Synchronous Multiprocessor Systems. IEEE Trans. Computers 31(11): 1116-1121 (1982)
7 Janak H. Patel: Analysis of Multiprocessors with Private Cache Memories. IEEE Trans. Computers 31(4): 296-304 (1982)
6 Janak H. Patel, Leona Y. Fung: Concurrent Error Detection in ALU's by Recomputing with Shifted Operands. IEEE Trans. Computers 31(7): 589-595 (1982)
1981
5 Janak H. Patel: Performance of Processor-Memory Interconnections for Multiprocessors. IEEE Trans. Computers 30(10): 771-780 (1981)
1980
4 Janak H. Patel: An Alternative to the Distributed Pipeline. IEEE Trans. Computers 29(8): 736-737 (1980)
1979
3 Janak H. Patel: Processor-Memory Interconnections for Multiprocessors. ISCA 1979: 168-177
1978
2 Janak H. Patel: Pipelines wth Internal Buffers. ISCA 1978: 249-255
1976
1 Janak H. Patel, Edward S. Davidson: Improving the Throughput of a Pipeline by Insertion of Delays. ISCA 1976: 159-164

Coauthor Index

1Jacob A. Abraham [13] [50] [60] [82]
2Santosh G. Abraham [23]
3Vishwani D. Agrawal [96] [98] [103] [109] [122] [141]
4Narendra Ahuja [64]
5Prithviraj Banerjee (Prith Banerjee) [48] [62] [71] [80] [83] [88] [111] [113] [118]
6Jeff Baxter [33] [56] [57] [75]
7Vamsi Boppana [114]
8Alfred Brenner [42]
9Michael L. Bushnell [109]
10Kenneth M. Butler [154]
11Hungse Cha [68] [70] [76] [77] [94]
12Sreejit Chakravarty [84] [89] [91] [110] [151]
13Susheel J. Chandra [25] [30]
14Ming-Feng Chang [31]
15Abhijit Chatterjee [60]
16Wu-Tung Cheng [16] [21] [38] [39] [51] [162] [163] [166]
17Vivek Chickermane [46] [53] [58] [62] [71] [72] [73] [83]
18Gwan S. Choi (Gwan Choi) [70] [94]
19Alok N. Choudhary [29] [37] [64]
20Pi-Yu Chung [66]
21James P. Cusey [119]
22Vinay Dabholkar [84]
23Ramaswami Dandapani [13]
24U. J. Davé [35]
25Edward S. Davidson [1] [8] [11] [12] [17] [137]
26Bulent I. Dervisoglu [82]
27Abhijit Dharchoudhury [77]
28Richard J. Eickemeyer [22] [28]
29Richard F. Freund [42]
30John W. C. Fu [41] [43] [52] [67] [75] [78]
31W. Kent Fuchs [24] [26] [31] [34] [36] [55] [91] [106] [114] [129] [151]
32Leona Y. Fung [6] [10]
33R. Stockton Gaines [42]
34Charles R. Graham [116]
35Gary S. Greenstein [59] [81] [108]
36Gregory F. Grohoski [9]
37Ibrahim N. Hajj [66] [95]
38Ilker Hamzaoglu [128] [131] [133] [138] [143] [144] [147] [150]
39Eiji Harada [92]
40Ismed Hartanto [91] [114] [151]
41Keerthi Heragu [96] [98] [103] [109] [122] [141]
42John G. Holm [79]
43Michael S. Hsiao [87] [97] [115] [118] [121] [123] [124] [125] [127] [130] [140] [145] [146]
44Frank F. Hsu [85] [101] [104] [107] [126] [132] [154]
45Ravishankar K. Iyer (Ravi K. Iyer) [27] [70] [94] [142] [165]
46Bob L. Janssens [52]
47Zbigniew Kalbarczyk [142] [165]
48Sung-Mo Kang [77]
49Rob Kelly [42]
50Sungho Kim [62]
51Dilip Krishnaswamy [111] [113] [118]
52Sandip Kundu [82]
53Subhasis Laha [27]
54Liyang Lai [162] [163] [166]
55Jaushin Lee [40] [45] [47] [53] [54] [58] [61] [63] [73] [74] [93]
56Myeong S. Lee [142]
57Terry Lee [95]
58Marc E. Levitt [82]
59Louis Lome [42]
60Steven S. Lumetta (Steven Lumetta) [159]
61Mohammad Malkawi [15] [19]
62Pinaki Mazumder [24] [26] [32] [49]
63Richard McAndrew [42]
64J. Najm [84]
65Jeffrey A. Newquist [152]
66Alexandru Nicolau (Alex Nicolau) [42]
67Thomas M. Niermann [39] [44] [50] [51] [81] [108]
68Amit R. Pandey [155] [157]
69Mark S. Papamarcos [14] [136]
70Steven Parkes [80] [88]
71Sanjay J. Patel [20]
72Srinivas Patil [48]
73Irith Pomeranz [69] [100] [105]
74Thomas Probert [42]
75Ashwin Ram [18]
76Balkrishna Ramkumar [57] [75]
77Jeff Rearick [65] [158]
78Sudhakar M. Reddy [69] [105] [159]
79John H. Reif [42]
80Thomas Rinderknecht [162] [163] [166]
81Rabindra K. Roy [50] [60]
82Elizabeth M. Rudnick [44] [55] [70] [71] [72] [79] [81] [83] [86] [90] [91] [94] [95] [97] [100] [101] [102] [104] [108] [111] [112] [113] [115] [116] [117] [118] [120] [121] [123] [125] [127] [130] [139] [140] [145] [146] [151]
83Daniel G. Saab [79]
84William H. Sanders [165]
85Jorge L. C. Sanz [42]
86Gurjeet S. Saund [124] [130]
87Vikram Saxena [118]
88Mihir A. Shah [164]
89Manish Sharma [148] [149] [153] [156] [158] [161]
90Howard Jay Siegel [42]
91Gurindar S. Sohi [17]
92Hector R. Sucar [82]
93Paul J. Thadikaran [89] [110]
94Srikanth Venkataraman [91] [106] [129] [151]
95Ron G. Walther [82]
96Jon A. Webb [42]
97Kun-Lung Wu [34] [36]
98Dong Xiang [99] [106] [160]
99Phil C. C. Yeh [11] [12]
100David W. L. Yen [8]
101Jian-Kun Zhao [112] [152]
102Manuel A. d'Abreu [60] [82]

Colors in the list of coauthors

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)