| 2005 |
|---|
| 9 | EE | Ishwar Parulkar,
Robert Cypher:
Trends and Trade-Offs in Designing Highly Robust Throughput Computing Oriented Chips and Systems.
IOLTS 2005: 74-77 |
| 2003 |
|---|
| 8 | EE | Peter Dahlgren,
Paul Dickinson,
Ishwar Parulkar:
Latch Divergency In Microprocessor Failure Analysis.
ITC 2003: 755-763 |
| 2002 |
|---|
| 7 | EE | Ishwar Parulkar,
Thomas A. Ziaja,
Rajesh Pendurkar,
Anand D'Souza,
Amitava Majumdar:
A Scalable, Low Cost Design-for-Test Architecture for UltraSPARC? Chip Multi-Processors.
ITC 2002: 726-735 |
| 2001 |
|---|
| 6 | EE | Ishwar Parulkar,
Sandeep K. Gupta,
Melvin A. Breuer:
Introducing redundant computations in RTL data paths for reducing BIST resources.
ACM Trans. Design Autom. Electr. Syst. 6(3): 423-445 (2001) |
| 1998 |
|---|
| 5 | EE | Ishwar Parulkar,
Sandeep K. Gupta,
Melvin A. Breuer:
Introducing Redundant Computations in a Behavior for Reducing BIST Resources.
DAC 1998: 548-553 |
| 4 | EE | Ishwar Parulkar,
Sandeep K. Gupta,
Melvin A. Breuer:
Scheduling and Module Assignment for Reducing Bist Resources.
DATE 1998: 66-73 |
| 1996 |
|---|
| 3 | EE | Ishwar Parulkar,
Sandeep K. Gupta,
Melvin A. Breuer:
Lower Bounds on Test Resources for Scheduled Data Flow Graphs.
DAC 1996: 143-148 |
| 1995 |
|---|
| 2 | EE | Ishwar Parulkar,
Sandeep K. Gupta,
Melvin A. Breuer:
Data Path Allocation for Synthesizing RTL Designs with Low BIST Area Overhead.
DAC 1995: 395-401 |
| 1994 |
|---|
| 1 | EE | Ishwar Parulkar,
Melvin A. Breuer,
Charles Njinda:
Extraction of a High-level structural Representation from Circuit Descriptions with Applications to DFT/BIST.
DAC 1994: 345-356 |
