| 2005 |
|---|
| 5 | EE | C. K. Tang,
Parag K. Lala,
James Patrick Parkerson:
A Technique for Designing Totally Self-Checking Domino Logic Circuits.
ISQED 2005: 128-132 |
| 4 | EE | D. P. Vasudevan,
Parag K. Lala,
James Patrick Parkerson:
CMOS Realization of Online Testable Reversible Logic Gates.
ISVLSI 2005: 309-310 |
| 2004 |
|---|
| 3 | EE | D. P. Vasudevan,
Parag K. Lala,
James Patrick Parkerson:
A Novel Approach for On-line Testable Reversible Logic Circuit Desig.
Asian Test Symposium 2004: 325-330 |
| 2 | | D. P. Vasudevan,
James Patrick Parkerson,
Parag K. Lala:
Logic implementation using a reversible gate.
Circuits, Signals, and Systems 2004: 452-456 |
| 1 | EE | D. P. Vasudevan,
Parag K. Lala,
James Patrick Parkerson:
Online Testable Reversible Logic Circuit Design using NAND Blocks.
DFT 2004: 324-331 |
