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Joonseok Park Vis

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*2009
17EEJaeyoung Yi, Karam Park, Joonseok Park, Won Woo Ro: Fully Pipelined Hardware Implementation of 128-Bit SEED Block Cipher Algorithm. ARC 2009: 181-192
2008
16EEJoon-Sang Park, Uichin Lee, Soon-Young Oh, Mario Gerla, Desmond S. Lun, Won Woo Ro, Joonseok Park: Delay Analysis of Car-to-Car Reliable Data Delivery Strategies Based on Data Mulling with Network Coding. IEICE Transactions 91-D(10): 2524-2527 (2008)
2007
15EEJoonseok Park, Pedro C. Diniz: Partial Data Reuse for Windowing Computations: Performance Modeling for FPGA Implementations. ARC 2007: 97-109
2005
14EEPedro C. Diniz, Mary W. Hall, Joonseok Park, Byoungro So, Heidi E. Ziegler: Automatic mapping of C to FPGAs with the DEFACTO compilation and synthesis system. Microprocessors and Microsystems 29(2-3): 51-62 (2005)
2004
13EENastaran Baradaran, Joonseok Park, Pedro C. Diniz: Data Reuse in Configurable Architectures with RAM Blocks: Extended Abstract. FPL 2004: 1113-1115
12EENastaran Baradaran, Pedro C. Diniz, Joonseok Park: Extending the Applicability of Scalar Replacement to Multiple Induction Variables. LCPC 2004: 455-469
11EEJoonseok Park, Pedro C. Diniz, K. R. Shesha Shayee: Performance and Area Modeling of Complete FPGA Designs in the Presence of Loop Transformations. IEEE Trans. Computers 53(11): 1420-1435 (2004)
2003
10EEPedro C. Diniz, Joonseok Park: Data Search and Reorganization Using FPGAs: Application to Spatial Pointer-based Data Structures. FCCM 2003: 207-217
9EEK. R. Shesha Shayee, Joonseok Park, Pedro C. Diniz: Performance and Area Modeling of Complete FPGA Designs in the presence of Loop Transformations. FCCM 2003: 296
8EEJoonseok Park, Pedro C. Diniz: Synthesis and Estimation of Memory Interfaces for FPGA-based Reconfigurable Computing Engines. FCCM 2003: 297-299
7EEPedro C. Diniz, Joonseok Park: Using FPGAs for data and reorganization engines: preliminary results for spatial pointer-based data structures. FPGA 2003: 242
6EEK. R. Shesha Shayee, Joonseok Park, Pedro C. Diniz: Performance and Area Modeling of Cmplete FPGA Designs in the Presence of Loop Transformations. FPL 2003: 313-323
2002
5EEPedro C. Diniz, Joonseok Park: Data reorganization engines for the next generation of system-on-a-chip FPGAs. FPGA 2002: 237-244
2001
4EEPablo Moisset, Pedro C. Diniz, Joonseok Park: Matching and searching analysis for parallel hardware implementation on FPGAs. FPGA 2001: 125-133
3 Joonseok Park, Pedro C. Diniz: Synthesis of pipelined memory access controllers for streamed data applications on FPGA-based computing engines. ISSS 2001: 221-226
2EEPedro C. Diniz, Mary W. Hall, Joonseok Park, Byoungro So, Heidi E. Ziegler: Bridging the Gap between Compilation and Synthesis in the DEFACTO System. LCPC 2001: 52-70
2000
1EEPedro C. Diniz, Joonseok Park: Automatic Synthesis of Data Storage and Control Structures for FPGA-Based Computing Engines. FCCM 2000: 91-100

Coauthor Index

1Nastaran Baradaran [12] [13]
2Pedro C. Diniz [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15]
3Mario Gerla [16]
4Mary W. Hall [2] [14]
5Uichin Lee [16]
6Desmond S. Lun [16]
7Pablo Moisset [4]
8Soon-Young Oh [16]
9Joon-Sang Park [16]
10Karam Park [17]
11Won Woo Ro [16] [17]
12K. R. Shesha Shayee [6] [9] [11]
13Byoungro So [2] [14]
14Jaeyoung Yi [17]
15Heidi E. Ziegler [2] [14]

Colors in the list of coauthors

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)