Ajit Pal

2008
19	EE	Tanmay De, Ajit Pal, Indranil Sengupta: Routing and Wavelength Assignment in All Optical Networks Based on Clique Partitioning. ICDCN 2008: 452-463
2007
18	EE	Akepati Sravan, Sujan Kundu, Ajit Pal: Low Power Sensor Node for a Wireless Sensor Network. VLSI Design 2007: 445-450
2006
17	EE	Gopal Paul, Ajit Pal, Bhargab B. Bhattacharya: On finding the minimum test set of a BDD-based circuit. ACM Great Lakes Symposium on VLSI 2006: 169-172
2005
16		Ajit Pal, Ajay D. Kshemkalyani, Rajeev Kumar, Arobinda Gupta: Distributed Computing - IWDC 2005, 7th International Workshop, Kharagpur, India, December 27-30, 2005, Proceedings Springer 2005
2004
15	EE	Ajit Pal, Umesh Patel: Routing and Wavelength Assignment in Wavelength Division Multiplexing Networks. IWDC 2004: 391-396
14	EE	Maitrali Marik, Ajit Pal: Energy-aware Logic Synthesis and Technology Mapping for MUX-based FPGAs. VLSI Design 2004: 73-78
13	EE	Debasis Samanta, Ajit Pal: Synthesis of Low Power High Performance Dual-VT PTL Circuits. VLSI Design 2004: 85-
2003
12	EE	Debasis Samanta, Ajit Pal: Synthesis of Dual-VT Dynamic CMOS Circuits. VLSI Design 2003: 303-308
2002
11	EE	Debasis Samanta, Ajit Pal: Optimal Dual -VT Assignment for Low-Voltage Energy-Constrained CMOS Circuits. ASP-DAC 2002: 193-198
10	EE	Debasis Samanta, Ajit Pal, Nishant Sinha: Synthesis of High Performance Low Power Dynamic CMOS Circuits. ASP-DAC 2002: 99-104
9	EE	Debasis Samanta, Ajit Pal: Optimal Dual -VT Assignment for Low-Voltage Energy-Constrained CMOS Circuits. VLSI Design 2002: 193-198
8	EE	Debasis Samanta, Nishant Sinha, Ajit Pal: Synthesis of High Performance Low Power Dynamic CMOS Circuits. VLSI Design 2002: 99-104
2001
7	EE	Nikhil Tripathi, Amit M. Bhosle, Debasis Samanta, Ajit Pal: Optimal Assignment of High Threshold Voltage for Synthesizing Dual Threshold CMOS Circuits. VLSI Design 2001: 227-
1998
6	EE	Rajat K. Pal, Sudebkumar Prasant Pal, Ajit Pal: An algorithm for finding a non-trivial lower bound for channel routing1. Integration 25(1): 71-84 (1998)
1997
5	EE	Rajat K. Pal, Sudebkumar Prasant Pal, Ajit Pal: An Algorithm for Finding a Non-Trivial Lower Bound for Channel Routing. VLSI Design 1997: 531-533
1995
4	EE	Rajat K. Pal, Sudebkumar Prasant Pal, M. M. Das, Ajit Pal: Computing area and wire length efficient routes for channels. VLSI Design 1995: 196-201
3	EE	Rajat K. Pal, A. K. Datta, Sudebkumar Prasant Pal, M. M. Das, Ajit Pal: A general graph theoretic framework for multi-layer channel routing. VLSI Design 1995: 202-207
1993
2		Rajat K. Pal, Sudebkumar Prasant Pal, Ajit Pal, Alak K. Dutta: NP-Completeness of Multi-Layer No-Dogleg Channel Routing and an Efficient Heuristic. VLSI Design 1993: 80-83
1986
1		Ajit Pal: An Algorithm for Optimal Logic Design Using Multiplexers. IEEE Trans. Computers 35(8): 755-757 (1986)

Coauthor Index

1	Bhargab B. Bhattacharya	[17]
2	Amit M. Bhosle	[7]
3	M. M. Das	[3] [4]
4	A. K. Datta	[3]
5	Tanmay De	[19]
6	Alak K. Dutta	[2]
7	Arobinda Gupta	[16]
8	Ajay D. Kshemkalyani	[16]
9	Rajeev Kumar	[16]
10	Sujan Kundu	[18]
11	Maitrali Marik	[14]
12	Rajat K. Pal	[2] [3] [4] [5] [6]
13	Sudebkumar Prasant Pal	[2] [3] [4] [5] [6]
14	Umesh Patel	[15]
15	Gopal Paul	[17]
16	Debasis Samanta	[7] [8] [9] [10] [11] [12] [13]
17	Indranil Sengupta	[19]
18	Nishant Sinha	[8] [10]
19	Akepati Sravan	[18]
20	Nikhil Tripathi	[7]

Colors in the list of coauthors