| |
| * | 2009 | |
|---|---|---|
| 3 | EE | Jin Ouyang, Raghuveer Raghavendra, Sibin Mohan, Tao Zhang, Yuan Xie, Frank Mueller: CheckerCore: enhancing an FPGA soft core to capture worst-case execution times. CASES 2009: 175-184 |
| 2008 | ||
| 2 | EE | Jin Ouyang, Yuan Xie: Power optimization for FinFET-based circuits using genetic algorithms. SoCC 2008: 211-214 |
| 1 | EE | Yibo Chen, Jin Ouyang, Yuan Xie: ILP-based scheme for timing variation-aware scheduling and resource binding. SoCC 2008: 27-30 |
| 1 | Yibo Chen | [1] |
| 2 | Sibin Mohan | [3] |
| 3 | Frank Mueller | [3] |
| 4 | Raghuveer Raghavendra | [3] |
| 5 | Yuan Xie | [1] [2] [3] |
| 6 | Tao Zhang | [3] |