| 2007 |
|---|
| 86 | EE | Xrysovalantis Kavousianos,
Emmanouil Kalligeros,
Dimitris Nikolos:
Optimal Selective Huffman Coding for Test-Data Compression.
IEEE Trans. Computers 56(8): 1146-1152 (2007) |
| 85 | EE | Themistoklis Haniotakis,
Y. Tsiatouhas,
Dimitris Nikolos,
Costas Efstathiou:
Testable Designs of Multiple Precharged Domino Circuits.
IEEE Trans. VLSI Syst. 15(4): 461-465 (2007) |
| 84 | EE | Giorgos Dimitrakopoulos,
Christos Mavrokefalidis,
K. Galanopoulos,
Dimitris Nikolos:
Sorter Based Permutation Units for Media-Enhanced Microprocessors.
IEEE Trans. VLSI Syst. 15(6): 711-715 (2007) |
| 83 | EE | Xrysovalantis Kavousianos,
Emmanouil Kalligeros,
Dimitris Nikolos:
Multilevel Huffman Coding: An Efficient Test-Data Compression Method for IP Cores.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(6): 1070-1083 (2007) |
| 2006 |
|---|
| 82 | EE | Giorgos Dimitrakopoulos,
Christos Mavrokefalidis,
Costas Galanopoulos,
Dimitris Nikolos:
An Energy-Delay Efficient Subword Permutation Unit.
ASAP 2006: 245-252 |
| 81 | EE | Xrysovalantis Kavousianos,
Emmanouil Kalligeros,
Dimitris Nikolos:
Efficient test-data compression for IP cores using multilevel Huffman coding.
DATE 2006: 1033-1038 |
| 80 | EE | Dimitris Nikolos,
Dimitrios Kagaris,
S. Gidaros:
Diophantine-Equation Based Arithmetic Test Set Embedding.
IOLTS 2006: 193-194 |
| 79 | EE | Giorgos Dimitrakopoulos,
Christos Mavrokefalidis,
Costas Galanopoulos,
Dimitris Nikolos:
Fast bit permutation unit for media enhanced microprocessors.
ISCAS 2006 |
| 78 | EE | Emmanouil Kalligeros,
Xrysovalantis Kavousianos,
Dimitris Nikolos:
Efficient Multiphase Test Set Embedding for Scan-based Testing.
ISQED 2006: 433-438 |
| 77 | EE | Dimitrios Kagaris,
P. Karpodinis,
Dimitris Nikolos:
On Obtaining Maximum-Length Sequences for Accumulator-Based Serial TPG.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(11): 2578-2586 (2006) |
| 76 | EE | Dimitris Bakalis,
K. Adaos,
D. Lymperopoulos,
Maciej Bellos,
Haridimos T. Vergos,
George Alexiou,
Dimitris Nikolos:
A core generator for arithmetic cores and testing structures with a network interface.
Journal of Systems Architecture 52(1): 1-12 (2006) |
| 2005 |
|---|
| 75 | EE | Maciej Bellos,
Dimitris Nikolos:
Deterministic Test Vector Compression / Decompression Using an Embedded Processor.
EDCC 2005: 318-331 |
| 74 | EE | Emmanouil Kalligeros,
D. Kaseridis,
Xrysovalantis Kavousianos,
Dimitris Nikolos:
Reseeding-Based Test Set Embedding with Reduced Test Sequences.
ISQED 2005: 226-231 |
| 73 | EE | Giorgos Dimitrakopoulos,
Dimitris Nikolos:
Closed-Form Bounds for Interconnect-Aware Minimum-Delay Gate Sizing.
PATMOS 2005: 308-317 |
| 72 | EE | Giorgos Dimitrakopoulos,
Dimitris Nikolos:
High-Speed Parallel-Prefix VLSI Ling Adders.
IEEE Trans. Computers 54(2): 225-231 (2005) |
| 71 | EE | Costas Efstathiou,
Haridimos T. Vergos,
Giorgos Dimitrakopoulos,
Dimitris Nikolos:
Efficient Diminished-1 Modulo 2^n+1 Multipliers.
IEEE Trans. Computers 54(4): 491-496 (2005) |
| 2004 |
|---|
| 70 | EE | C. Laoudias,
Dimitris Nikolos:
A new test pattern generator for high defect coverage in a BIST environment.
ACM Great Lakes Symposium on VLSI 2004: 417-420 |
| 69 | EE | P. Karpodinis,
Dimitri Kagaris,
Dimitris Nikolos:
Accumulator based Test-per-Scan BIST.
IOLTS 2004: 193-198 |
| 68 | EE | Maciej Bellos,
Dimitris Bakalis,
Dimitris Nikolos,
Xrysovalantis Kavousianos:
Low Power Testing by Test Vector Ordering with Vector Repetition.
ISQED 2004: 205-210 |
| 67 | EE | Maciej Bellos,
Dimitris Bakalis,
Dimitris Nikolos:
Scan Cell Ordering for Low Power BIST.
ISVLSI 2004: 281-284 |
| 66 | EE | Xrysovalantis Kavousianos,
Dimitris Bakalis,
Maciej Bellos,
Dimitris Nikolos:
An Efficient Test Vector Ordering Method for Low Power Testing.
ISVLSI 2004: 285-288 |
| 65 | EE | Giorgos Dimitrakopoulos,
P. Kolovos,
P. Kalogerakis,
Dimitris Nikolos:
Design of High-Speed Low-Power Parallel-Prefix VLSI Adders.
PATMOS 2004: 248-257 |
| 64 | EE | Costas Efstathiou,
Haridimos T. Vergos,
Dimitris Nikolos:
Modified Booth Modulo 2n-1 Multipliers.
IEEE Trans. Computers 53(3): 370-374 (2004) |
| 63 | EE | Costas Efstathiou,
Haridimos T. Vergos,
Dimitris Nikolos:
Fast Parallel-Prefix Modulo 2^n+1 Adders.
IEEE Trans. Computers 53(9): 1211-1216 (2004) |
| 62 | EE | Emmanouil Kalligeros,
Xrysovalantis Kavousianos,
Dimitris Nikolos:
Multiphase BIST: a new reseeding technique for high test-data compression.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(10): 1429-1446 (2004) |
| 2003 |
|---|
| 61 | EE | Emmanouil Kalligeros,
Xrysovalantis Kavousianos,
Dimitris Nikolos:
A highly regular multi-phase reseeding technique for scan-based BIST.
ACM Great Lakes Symposium on VLSI 2003: 295-298 |
| 60 | EE | Giorgos Dimitrakopoulos,
Haridimos T. Vergos,
Dimitris Nikolos,
Costas Efstathiou:
A Family of Parallel-Pre.x Modulo 2n - 1 Adders.
ASAP 2003: 326-336 |
| 59 | EE | D. G. Nikolos,
Dimitris Nikolos,
Haridimos T. Vergos,
Costas Efstathiou:
An Efficient BIST scheme for High-Speed Adders.
IOLTS 2003: 89-93 |
| 58 | EE | Giorgos Dimitrakopoulos,
Haridimos T. Vergos,
Dimitris Nikolos,
Costas Efstathiou:
A systematic methodology for designing area-time efficient parallel-prefix modulo 2/sup n/ - 1 adders.
ISCAS (5) 2003: 225-228 |
| 57 | EE | Giorgos Dimitrakopoulos,
Xrysovalantis Kavousianos,
Dimitris Nikolos:
Virtual-scan: a novel approach for software-based self-testing of microprocessors.
ISCAS (5) 2003: 237-240 |
| 56 | EE | D. G. Nikolos,
Dimitris Nikolos,
Haridimos T. Vergos,
Costas Efstathiou:
Efficient BIST schemes for RNS datapaths.
ISCAS (5) 2003: 573-576 |
| 55 | EE | Maciej Bellos,
Dimitri Kagaris,
Dimitris Nikolos:
Low Power Test Set Embedding Based on Phase Shifters.
ISVLSI 2003: 155-160 |
| 54 | | Maciej Bellos,
Xrysovalantis Kavousianos,
Dimitris Nikolos,
Dimitri Kagaris:
DV-TSE: Difference Vector Based Test Set Embedding.
VLSI-SOC 2003: 343- |
| 53 | EE | Costas Efstathiou,
Haridimos T. Vergos,
Dimitris Nikolos:
Modulo 2n±1 Adder Design Using Select-Prefix Blocks.
IEEE Trans. Computers 52(11): 1399-1406 (2003) |
| 52 | EE | Haridimos T. Vergos,
Dimitris Nikolos,
Maciej Bellos,
Costas Efstathiou:
Deterministic BIST for RNS Adders.
IEEE Trans. Computers 52(7): 896-906 (2003) |
| 2002 |
|---|
| 51 | EE | Emmanouil Kalligeros,
Xrysovalantis Kavousianos,
Dimitris Nikolos:
A ROMless LFSR Reseeding Scheme for Scan-based BIST.
Asian Test Symposium 2002: 206- |
| 50 | EE | Maciej Bellos,
Dimitrios Kagaris,
Dimitris Nikolos:
Test Set Embedding Based on Phase Shifters.
EDCC 2002: 90-101 |
| 49 | EE | Giorgos Dimitrakopoulos,
Dimitris Nikolos,
Dimitris Bakalis:
Bit-Serial Test Pattern Generation by an Accumulator Behaving as a Non-Linear Feedback Shift Register.
IOLTW 2002: 152-157 |
| 48 | EE | Y. Tsiatouhas,
Angela Arapoyanni,
Dimitris Nikolos,
Th. Haniotakis:
A Hierarchical Architecture for Concurrent Soft Error Detection Based on Current Sensing.
IOLTW 2002: 56-60 |
| 47 | EE | Y. Tsiatouhas,
Th. Haniotakis,
Dimitris Nikolos,
Angela Arapoyanni:
Extending the Viability of IDDQ Testing in the Deep Submicron Era.
ISQED 2002: 100-105 |
| 46 | EE | Emmanouil Kalligeros,
Xrysovalantis Kavousianos,
Dimitris Bakalis,
Dimitris Nikolos:
An Efficient Seeds Selection Method for LFSR-Based Test-per-Clock BIST.
ISQED 2002: 261-266 |
| 45 | EE | Haridimos T. Vergos,
Costas Efstathiou,
Dimitris Nikolos:
Diminished-One Modulo 2n+1 Adder Design.
IEEE Trans. Computers 51(12): 1389-1399 (2002) |
| 44 | EE | Xrysovalantis Kavousianos,
Dimitris Bakalis,
Dimitris Nikolos,
Spyros Tragoudas:
A new built-in TPG method for circuits with random patternresistant faults.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(7): 859-866 (2002) |
| 43 | EE | Y. Tsiatouhas,
Yiannis Moisiadis,
Th. Haniotakis,
Dimitris Nikolos,
Angela Arapoyanni:
A new technique for IDDQ testing in nanometer technologies.
Integration 31(2): 183-194 (2002) |
| 42 | EE | Dimitris Bakalis,
Emmanouil Kalligeros,
Dimitris Nikolos,
Haridimos T. Vergos,
George Alexiou:
On the design of low power BIST for multipliers with Booth encoding and Wallace tree summation.
Journal of Systems Architecture 48(4-5): 125-135 (2002) |
| 2001 |
|---|
| 41 | EE | Xrysovalantis Kavousianos,
Dimitris Bakalis,
Dimitris Nikolos:
A novel reseeding technique for accumulator-based test pattern generation.
ACM Great Lakes Symposium on VLSI 2001: 7-12 |
| 40 | EE | Dimitris Bakalis,
K. Adaos,
George Alexiou,
Dimitris Nikolos,
D. Lymperopoulos:
EUDOXUS: A WWW-based Generator of Reusable Arithmetic Cores.
IEEE International Workshop on Rapid System Prototyping 2001: 182-187 |
| 39 | EE | Haridimos T. Vergos,
Dimitris Nikolos,
Costas Efstathiou:
High Speed Parallel-Prefix Modulo 2n+1 Adders for Diminished-One Operands.
IEEE Symposium on Computer Arithmetic 2001: 211-217 |
| 38 | EE | Y. Tsiatouhas,
Th. Haniotakis,
Dimitris Nikolos,
Costas Efstathiou:
Concurrent Detection of Soft Errors Based on Current Monitoring.
IOLTW 2001: 106-110 |
| 37 | EE | Emmanouil Kalligeros,
Xrysovalantis Kavousianos,
Dimitris Bakalis,
Dimitris Nikolos:
A New Reseeding Technique for LFSR-Based Test Pattern Generation.
IOLTW 2001: 80-86 |
| 36 | EE | Dimitris Bakalis,
Dimitris Nikolos,
Haridimos T. Vergos,
Xrysovalantis Kavousianos:
On Accumulator-Based Bit-Serial Test Response Compaction Schemes.
ISQED 2001: 350- |
| 2000 |
|---|
| 35 | EE | Y. Tsiatouhas,
Th. Haniotakis,
Angela Arapoyanni,
Dimitris Nikolos:
A Versatile Built-In Self-Test Scheme for Delay Fault Testing.
DATE 2000: 756 |
| 34 | EE | Y. Tsiatouhas,
Th. Haniotakis,
Dimitris Nikolos:
A Compact Built-In Current Sensor for IDDQ Testing.
IOLTW 2000: 95-99 |
| 33 | EE | Th. Haniotakis,
Y. Tsiatouhas,
Dimitris Nikolos,
Costas Efstathiou:
On Testability of Multiple Precharged Domino Logic.
ISQED 2000: 299-304 |
| 32 | EE | Dimitris Bakalis,
Dimitris Nikolos,
George Alexiou,
Emmanouil Kalligeros,
Haridimos T. Vergos:
Low Power BIST for Wallace Tree-Based Fast Multipliers.
ISQED 2000: 433-438 |
| 31 | | Xrysovalantis Kavousianos,
Dimitris Bakalis,
Dimitris Nikolos:
Test response compaction by an accumulator behaving as a multiple input non-linear feedback shift register.
ITC 2000: 804-811 |
| 30 | EE | Lampros Kalampoukas,
Dimitris Nikolos,
Costas Efstathiou,
Haridimos T. Vergos,
John Kalamatianos:
High-Speed Parallel-Prefix Modulo 2n-1 Adders.
IEEE Trans. Computers 49(7): 673-680 (2000) |
| 1999 |
|---|
| 29 | EE | G. Sidiropoulos,
Haridimos T. Vergos,
Dimitris Nikolos:
Easily Path Delay Fault Testable Non-Restoring Cellular Array Dividers.
Asian Test Symposium 1999: 47-52 |
| 28 | EE | Dimitris Nikolos,
Haridimos T. Vergos,
Th. Haniotakis,
Y. Tsiatouhas:
Path Delay Fault Testing of ICs with Embedded Intellectual Property Blocks.
DATE 1999: 112-116 |
| 27 | EE | Xrysovalantis Kavousianos,
Dimitris Bakalis,
Haridimos T. Vergos,
Dimitris Nikolos,
George Alexiou:
Low Power Dissipation in BIST Schemes for Modified Booth Multipliers.
DFT 1999: 121-129 |
| 26 | EE | Maciej Bellos,
Dimitris Nikolos,
Haridimos T. Vergos:
Path Delay Fault Testing of a Class of Circuit-Switched Multistage Interconnection Networks.
EDCC 1999: 267-282 |
| 25 | EE | Haridimos T. Vergos,
Dimitris Nikolos,
Y. Tsiatouhas,
Th. Haniotakis,
Michael Nicolaidis:
On Path Delay Fault Testing of Multiplexer - Based Shifters.
Great Lakes Symposium on VLSI 1999: 20-23 |
| 24 | EE | A. Vasilliou,
K. Gounaris,
K. Adaos,
D. Mitsainas,
George Alexiou,
Dimitris Nikolos:
Development of a Reusable E1 Transceiver Suitable for Rapid Prototyping.
IEEE International Workshop on Rapid System Prototyping 1999: 21- |
| 23 | | C. Ninos,
Haridimos T. Vergos,
Dimitris Nikolos:
Design and Analysis of On-Chip CPU Pipelined Caches.
VLSI 1999: 161-172 |
| 22 | EE | Xrysovalantis Kavousianos,
Dimitris Nikolos:
Modular TSC Checkers for Bose-Lin and Bose Codes.
VTS 1999: 354-360 |
| 21 | | Dimitris Nikolos,
Haridimos T. Vergos:
On the Yield of VLSI Processors with On-Chip CPU Cache.
IEEE Trans. Computers 48(10): 1138-1144 (1999) |
| 20 | EE | Xrysovalantis Kavousianos,
Dimitris Nikolos,
G. Foukarakis,
T. Gnardellis:
New efficient totally self-checking Berger code checkers.
Integration 28(1): 101-118 (1999) |
| 1998 |
|---|
| 19 | EE | Th. Haniotakis,
Dimitris Nikolos,
Y. Tsiatouhas:
C-Testable One-Dimensional ILAs with Respect to Path Delay Faults: Theory and Applications.
DFT 1998: 155-163 |
| 18 | EE | Ioannis Voyiatzis,
Antonis M. Paschalis,
Dimitris Nikolos,
Constantinos Halatsis:
R-CBIST: an effective RAM-based input vector monitoring concurrent BIST technique.
ITC 1998: 918-925 |
| 17 | EE | Xrysovalantis Kavousianos,
Dimitris Nikolos:
Novel Single and Double Output TSC Berger Code Checkers.
VTS 1998: 348-353 |
| 16 | | Dimitris Nikolos:
Optimal Self-Testing Embedded Parity Checkers.
IEEE Trans. Computers 47(3): 313-321 (1998) |
| 1997 |
|---|
| 15 | EE | Xrysovalantis Kavousianos,
Dimitris Nikolos,
G. Sidiropoulos:
Design of Compact and High speed, Totally Self Checking CMOS Checkers for m-out-of-n Codes.
DFT 1997: 128-136 |
| 14 | EE | Xrysovalantis Kavousianos,
Dimitris Nikolos:
Self-exercising self testing k-order comparators.
VTS 1997: 216-221 |
| 1996 |
|---|
| 13 | | Dimitris Nikolos,
Haridimos T. Vergos:
On the Yield of VLSI Processors with on-chip CPU Cache.
EDCC 1996: 214-230 |
| 12 | EE | Dimitris Gizopoulos,
Dimitris Nikolos,
Antonis M. Paschalis:
Testing CMOS combinational iterative logic arrays for realistic faults.
Integration 21(3): 209-228 (1996) |
| 1995 |
|---|
| 11 | EE | Ioannis Voyiatzis,
Dimitris Nikolos,
Antonis M. Paschalis,
Constantinos Halatsis,
Th. Haniotakis:
An efficient comparative concurrent Built-In Self-Test technique.
Asian Test Symposium 1995: 309-315 |
| 10 | EE | Dimitris Gizopoulos,
Dimitris Nikolos,
Antonis M. Paschalis:
Testing combinational iterative logic arrays for realistic faults.
VTS 1995: 35-41 |
| 9 | | Th. Haniotakis,
Antonis M. Paschalis,
Dimitris Nikolos:
Efficient Totally Self-Checking Checkers for a Class of Borden Codes.
IEEE Trans. Computers 44(11): 1318-1322 (1995) |
| 8 | | Vassilios V. Dimakopoulos,
G. Sourtziotis,
Antonis M. Paschalis,
Dimitris Nikolos:
On TSC Checkers for m-out-n Codes.
IEEE Trans. Computers 44(8): 1055-1059 (1995) |
| 1992 |
|---|
| 7 | | Dimitris Nikolos,
Alexandros Krokos:
Theory and Design of t-Error Correcting, k-Error Detecting and d-Unidirectional Error Detecting Codes with d > k > t.
IEEE Trans. Computers 41(4): 411-419 (1992) |
| 1991 |
|---|
| 6 | | Dimitris Nikolos:
Theory and Design of t-Error Correcting/d-Error Detecting (d>t) and All Unidirectional Error Detecting Codes.
IEEE Trans. Computers 40(2): 132-142 (1991) |
| 1988 |
|---|
| 5 | | Antonis M. Paschalis,
Dimitris Nikolos,
Constantine Halatsis:
Efficient Modular Design of TSC Checkers for M-out-of-2M Codes.
IEEE Trans. Computers 37(3): 301-309 (1988) |
| 4 | | Dimitris Nikolos,
Antonis M. Paschalis,
George Philokyprou:
Efficient Design of Totally Self-Checking Checkers for all Low-Cost Arithmetic Codes.
IEEE Trans. Computers 37(7): 807-814 (1988) |
| 1986 |
|---|
| 3 | | Antonis M. Paschalis,
Dimitris Nikolos,
Constantine Halatsis:
Efficient Modular Design of TSC Checkers for M-out-of-2M Codes.
Aegean Workshop on Computing 1986: 144-155 |
| 2 | | Dimitris Nikolos,
Nikolaos Gaitanis,
George Philokyprou:
Systematic t-Error Correcting/All Unidirectional Error Detecting Codes.
IEEE Trans. Computers 35(5): 394-402 (1986) |
| 1984 |
|---|
| 1 | | Dimitris Nikolos,
Nikolaos Gaitanis,
George Philokyprou:
Systematic t-error correcting all unidirectional error detecting codes.
Fehlertolerierende Rechensysteme 1984: 177-188 |
