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Takashi Nanya Vis

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*2008
62 Takashi Nanya, Fumihiro Maruyama, András Pataricza, Miroslaw Malek: Service Availability, 5th International Service Availability Symposium, ISAS 2008, Tokyo, Japan, May 19-21, 2008, Proceedings Springer 2008
61EEMasashi Imai, Takashi Nanya: A design method for 1-out-of-4 encoded low-power self-timed circuits using standard cell libraries. ACSD 2008: 21-26
60EENaohiro Hamada, Yuuki Shiga, Hiroshi Saito, Tomohiro Yoneda, Chris J. Myers, Takashi Nanya: A behavioral synthesis method for asynchronous circuits with bundled-data implementation (Tool paper). ACSD 2008: 50-55
59EEBogdan Tomoyuki Nassu, Kiyonobu Uehara, Takashi Nanya: Injecting Inconsistent Values Caused by Interaction Faults for Experimental Dependability Evaluation. EDCC 2008: 3-12
58EEBogdan Tomoyuki Nassu, Takashi Nanya, Hiroshi Nakamura: Discovering Implicit Redundancies in Network Communications for Detecting Inconsistent Values. ICDM Workshops 2008: 144-153
57EEBogdan Tomoyuki Nassu, Takashi Nanya: Interaction Faults Caused by Third-Party External Systems - A Case Study and Challenges. ISAS 2008: 59-74
56EEBogdan Tomoyuki Nassu, Takashi Nanya, Hiroshi Nakamura: Detecting Inconsistent Values Caused by Interaction Faults Using Automatically Located Implicit Redundancies. PRDC 2008: 138-145
55EERoberto Jung Drebes, Takashi Nanya: Limitations of the Linux Fault Injection Framework to Test Direct Memory Access Address Errors. PRDC 2008: 146-152
2007
54EERyo Watanabe, Masaaki Kondo, Masashi Imai, Hiroshi Nakamura, Takashi Nanya: Interactive presentation: Task scheduling under performance constraints for reducing the energy consumption of the GALS multi-processor SoC. DATE 2007: 797-802
53EEWenyu Qu, Keqiu Li, Masaru Kitsuregawa, Takashi Nanya: An Efficient Method for Improving Data Collection Precision in Lifetime-adaptive Wireless Sensor Networks. ICC 2007: 3161-3166
52EERyo Watanabe, Masaaki Kondo, Hiroshi Nakamura, Takashi Nanya: Power reduction of chip multi-processors using shared resource control cooperating with DVFS. ICCD 2007: 615-622
51EEKeqiu Li, Takashi Nanya, Wenyu Qu: A Minimal Access Cost-Based Multimedia Object Replacement Algorithm. IPDPS 2007: 1-7
50EETakashi Nanya: Challenges in Dependability of Networked Systems for Information Society. NPC 2007: 542
49EEWenyu Qu, Keqiu Li, Masaru Kitsuregawa, Takashi Nanya: An optimal solution for caching multimedia objects in transcoding proxies. Computer Communications 30(8): 1802-1810 (2007)
48EEHiroshi Saito, Naohiro Hamada, Nattha Jindapetch, Tomohiro Yoneda, Chris J. Myers, Takashi Nanya: Scheduling Methods for Asynchronous Circuits with Bundled-Data Implementations Based on the Approximation of Start Times. IEICE Transactions 90-A(12): 2790-2799 (2007)
2006
47EEMasashi Imai, Takashi Nanya: A Novel Design Method for Asynchronous Bundled-data Transfer Circuits Considering Characteristics of Delay Variations. ASYNC 2006: 68-77
46EEHiroshi Saito, Nattha Jindapetch, Tomohiro Yoneda, Chris J. Myers, Takashi Nanya: ILP-based Scheduling for Asynchronous Circuits in Bundled-Data Implementation. CIT 2006: 172
45EEKeqiu Li, Takashi Nanya, Bo Jiang, Wenyu Qu: State-of-Art Techniques for Object Caching over the Internet. IMSCCS (2) 2006: 199-206
44EEBogdan Tomoyuki Nassu, Takashi Nanya: A Scenario of Tolerating Interaction Faults Between Otherwise Correct Systems. PRDC 2006: 371-372
43EEKouichi Watanabe, Masashi Imai, Masaaki Kondo, Hiroshi Nakamura, Takashi Nanya: Design Method of High Performance and Low Power Functional Units Considering Delay Variations. IEICE Transactions 89-A(12): 3519-3528 (2006)
2005
42EEWenyu Qu, Keqiu Li, Hong Shen, Yingwei Jin, Takashi Nanya: The Cache Replacement Problem for Multimedia Object Caching. SKG 2005: 26
41EEKeqiu Li, Wenyu Qu, Hong Shen, Di Wu, Takashi Nanya: Two Cache Replacement Algorithms Based on Association Rules and Markov Models. SKG 2005: 28
2004
40EEMasashi Imai, Metehan Özcan, Takashi Nanya: Evaluation of Delay Variation in Asynchronous Circuits Based on the Scalable-Delay-Insensitive Model. ASYNC 2004: 62-71
39EEMasayuki Tsukisaka, Masashi Imai, Takashi Nanya: Asynchronous Scan-Latch controller for Low Area Overhead DFT. ICCD 2004: 66-71
38EEHiroshi Nakamura, Takuro Hayashida, Masaaki Kondo, Yuya Tajima, Masashi Imai, Takashi Nanya: Skewed Checkpointing for Tolerating Multi-Node Failures. SRDS 2004: 116-125
2003
37EEHiroshi Saito, Euiseok Kim, Nattha Sretasereekul, Masashi Imai, Hiroshi Nakamura, Takashi Nanya: Control Signal Sharing Using Data-Path Delay Information at Control Data Flow Graph Descriptions. ASYNC 2003: 184-195
36EEEuiseok Kim, Hiroshi Saito, Jeong-Gun Lee, Dong-Ik Lee, Hiroshi Nakamura, Takashi Nanya: Distributed Synchronous Control Units for Dataflow Graphs under Allocation of Telescopic Arithmetic Units. DATE 2003: 10276-10281
35EEWen Gao, Xinyu Liu, Lei Wang, Takashi Nanya: A Reconfigurable High Availability Infrastructure in Cluster for Grid. GCC (1) 2003: 576-583
34EENattha Sretasereekul, Hiroshi Saito, Masashi Imai, Euiseok Kim, Metehan Özcan, K. Thongnoo, Hiroshi Nakamura, Takashi Nanya: A zero-time-overhead asynchronous four-phase controller. ISCAS (5) 2003: 205-208
33EEHiroshi Saito, Euiseok Kim, Masashi Imai, Nattha Sretasereekul, Hiroshi Nakamura, Takashi Nanya: Control signal sharing of asynchronous circuits using datapath delay information. ISCAS (5) 2003: 617-620
2002
32EEMetehan Özcan, Masashi Imai, Takashi Nanya: Generation and Verification of Timing Constraints for Fine-Grain Pipelined Asynchronous Data-Path Circuits. ASYNC 2002: 109-114
31 Hiroshi Saito, Hiroshi Nakamura, Masahiro Fujita, Takashi Nanya: Logic Optimization for Asynchronous SI Controllers using Transduction Method. IWLS 2002: 245-250
30 Masayuki Tsukisaka, Masashi Imai, Takashi Nanya: High Throughput Asynchronous Domino Using Dual output Buffer. IWLS 2002: 279-282
29EEHiroshi Saito, Alex Kondratyev, Takashi Nanya: Design of Asynchronous Controllers with Delay Insensitive Interface. VLSI Design 2002: 93-98
2001
28EEHiroto Kagotani, Takuji Okamoto, Takashi Nanya: Synthesis of four-phase asynchronous control circuits from pipeline dependency graphs. ASP-DAC 2001: 425-430
27EENattha Sretasereekul, Takashi Nanya: Eliminating isochronic-fork constraints in quasi-delay-insensitive circuits. ASP-DAC 2001: 437-442
26EEMotokazu Ozawa, Masashi Imai, Hiroshi Nakamura, Takashi Nanya, Yoichiro Ueno: Performance Evaluation of Cascade ALU Architecture for Asynchronous Super-Scalar Processors. ASYNC 2001: 162-172
2000
25EEMasayuki Tsukisaka, Takashi Nanya: A testable design for asynchronous fine-grain pipeline circuits. PRDC 2000: 148-155
1999
24EEAndreas Savva, Takashi Nanya: A Gracefully Degrading Massively Parallel System Using the BSP Model, and Its Evaluation. IEEE Trans. Computers 48(1): 38-52 (1999)
1998
23 Mohit Sahni, Takashi Nanya: On the CSC Property of Signal Transition Graph Specifications for Asynchronous Circuit Design. ASP-DAC 1998: 183-189
22 Akihiro Takamura, Motokazu Ozawa, Izumi Fukasaku, Taro Fujii, Yoichiro Ueno, Masashi Imai, Masashi Kuwako, Takashi Nanya: TITAC-2: An Asynchronous 32-bit Microprocessor. ASP-DAC 1998: 319-320
21EEYoshio Kameda, Stanislav Polonsky, Masaaki Maezawa, Takashi Nanya: Primitive-Level Pipelining Method on Delay-Insensitive Model for RSFQ Pulse-Driven Logic. ASYNC 1998: 262-273
20 Elias Procópio Duarte Jr., Takashi Nanya: A Hierarachical Adaptive Distributed System-Level Diagnosis Algorithm. IEEE Trans. Computers 47(1): 34-45 (1998)
19EEElias Procópio Duarte Jr., Glenn Mansfield, Takashi Nanya, Shoichi Noguchi: Improving the dependability of network management systems. Int. Journal of Network Management 8(4): 244-253 (1998)
18EEArthit Thongtak, Takashi Nanya: Stuck-at-fault testing for quasi-delay-insensitive logic circuits. Systems and Computers in Japan 29(2): 19-27 (1998)
1997
17 Akihiro Takamura, Masashi Kuwako, Masashi Imai, Taro Fujii, Motokazu Ozawa, Izumi Fukasaku, Yoichiro Ueno, Takashi Nanya: TITAC-2: An asynchronous 32-bit microprocessor based on Scalable-Delay-Insensitive model. ICCD 1997: 288-294
16 Elias Procópio Duarte Jr., Glenn Mansfield, Takashi Nanya, Shoichi Noguchi: Non-Broadcast Network Fault-Monitoring Based on System-Level Diagnosis. Integrated Network Management 1997: 597-609
15EETomohiro Yoneda, Atsufumi Shibayama, Takashi Nanya: Verification of asynchronous logic circuit design using process algebra. Systems and Computers in Japan 28(8-9): 33-43 (1997)
1996
14 Elias Procópio Duarte Jr., Takashi Nanya: Hierarchical Adaptive Distributed System-Level Diagnosis Applied for SNMP-based Network Fault Management. SRDS 1996: 98-107
13EESung-Bum Park, Takashi Nanya: Automatic Synthesis of Speed-Independent Circuits from Signal Transition Graph Specifications. VLSI Design 1996: 389-392
1995
12 Stanislaw J. Piestrak, Takashi Nanya: Towards Totally Self-Checking Delay-Insensitive Systems. FTCS 1995: 228-237
11 Andreas Savva, Takashi Nanya: Gracefully Degrading Systems Using the Bulk-Synchronous Parallel Model with Randomised Shared Memory. FTCS 1995: 299-308
1994
10EETakashi Nanya, Yoichiro Ueno, Hiroto Kagotani, Masashi Kuwako, Akihiro Takamura: TITAC: Design of A Quasi-Delay-Insensitive Microprocessor. IEEE Design & Test of Computers 11(2): 50-63 (1994)
1992
9 Takashi Nanya, Shin'ichi Hatakenaka, Ryuichi Onoo: Design of Fully Exercised SFS/SCD Logic Networks. FTCS 1992: 96-103
1989
8EETakashi Nanya, Hendrik A. Goosen: The Byzantine hardware fault model. IEEE Trans. on CAD of Integrated Circuits and Systems 8(11): 1226-1231 (1989)
1988
7 Takashi Nanya, Toshiaki Kawamura: Error/Secure/Propagating Concept and its Application to the Design of Strongly Fault-Secure Processors. IEEE Trans. Computers 37(1): 14-24 (1988)
1987
6 Takashi Nanya, Toshiaki Kawamura: On Error Indication for Totally Self-Checking Systems. IEEE Trans. Computers 36(11): 1389-1392 (1987)
5 Takashi Nanya, Toshiaki Kawamura: A Note on Strongly Fault-Secure Sequential Circuits. IEEE Trans. Computers 36(9): 1121-1123 (1987)
1984
4 Teruhiko Yamada, Takashi Nanya: Stuck-At Fault Tests in the Presence of Undetectable Bridging Faults. IEEE Trans. Computers 33(8): 758-761 (1984)
1983
3 Teruhiko Yamada, Takashi Nanya: Comments on "Detection Location of Input and Feedback Bridging Faults Among Input Output Lines". IEEE Trans. Computers 32(5): 511-512 (1983)
1979
2 Takashi Nanya, Yoshihiro Tohma: Universal Multicode STT State Assignments for Asynchronous Sequential Machines. IEEE Trans. Computers 28(11): 811-818 (1979)
1978
1 Takashi Nanya, Yoshihiro Tohma: On Universal Single Transition Time Asynchronous State Assignments. IEEE Trans. Computers 27(8): 781-782 (1978)

Coauthor Index

1Roberto Jung Drebes [55]
2Elias Procópio Duarte Jr. [14] [16] [19] [20]
3Taro Fujii [17] [22]
4Masahiro Fujita [31]
5Izumi Fukasaku [17] [22]
6Wen Gao [35]
7Hendrik A. Goosen [8]
8Naohiro Hamada [48] [60]
9Shin'ichi Hatakenaka [9]
10Takuro Hayashida [38]
11Masashi Imai [17] [22] [26] [30] [32] [33] [34] [37] [38] [39] [40] [43] [47] [54] [61]
12Bo Jiang [45]
13Yingwei Jin [42]
14Nattha Jindapetch [46] [48]
15Hiroto Kagotani [10] [28]
16Yoshio Kameda [21]
17Toshiaki Kawamura [5] [6] [7]
18Glenn Mansfield Keeni (Glenn Mansfield) [16] [19]
19Euiseok Kim [33] [34] [36] [37]
20Masaru Kitsuregawa [49] [53]
21Masaaki Kondo [38] [43] [52] [54]
22Alex Kondratyev [29]
23Masashi Kuwako [10] [17] [22]
24Dong-Ik Lee [36]
25Jeong-Gun Lee [36]
26Keqiu Li [41] [42] [45] [49] [51] [53]
27Xinyu Liu [35]
28Masaaki Maezawa [21]
29Miroslaw Malek [62]
30Fumihiro Maruyama [62]
31Chris J. Myers [46] [48] [60]
32Hiroshi Nakamura [26] [31] [33] [34] [36] [37] [38] [43] [52] [54] [56] [58]
33Bogdan Tomoyuki Nassu [44] [56] [57] [58] [59]
34Shoichi Noguchi [16] [19]
35Takuji Okamoto [28]
36Ryuichi Onoo [9]
37Motokazu Ozawa [17] [22] [26]
38Metehan Özcan [32] [34] [40]
39Sung-Bum Park [13]
40András Pataricza [62]
41Stanislaw J. Piestrak [12]
42Stanislav Polonsky [21]
43Wenyu Qu [41] [42] [45] [49] [51] [53]
44Mohit Sahni [23]
45Hiroshi Saito [29] [31] [33] [34] [36] [37] [46] [48] [60]
46Andreas Savva [11] [24]
47Hong Shen [41] [42]
48Atsufumi Shibayama [15]
49Yuuki Shiga [60]
50Nattha Sretasereekul [27] [33] [34] [37]
51Yuya Tajima [38]
52Akihiro Takamura [10] [17] [22]
53K. Thongnoo [34]
54Arthit Thongtak [18]
55Yoshihiro Tohma [1] [2]
56Masayuki Tsukisaka [25] [30] [39]
57Kiyonobu Uehara [59]
58Yoichiro Ueno [10] [17] [22] [26]
59Lei Wang [35]
60Kouichi Watanabe [43]
61Ryo Watanabe [52] [54]
62Di Wu [41]
63Teruhiko Yamada [3] [4]
64Tomohiro Yoneda [15] [46] [48] [60]

Colors in the list of coauthors

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)