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Michinobu Nakao Vis

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*2002
6EEKazumi Hatayama, Michinobu Nakao, Yasuo Sato: At-Speed Built-in Test for Logic Circuits with Multiple Clocks. Asian Test Symposium 2002: 292-297
5EEKazumi Hatayama, Michinobu Nakao, Yoshikazu Kiyoshige, Koichiro Natsume, Yasuo Sato, Takaharu Nagumo: Application of High-Quality Built-In Test to Industrial Designs. ITC 2002: 1003-1012
2001
4EEMichinobu Nakao, Yoshikazu Kiyoshige, Kazumi Hatayama, Yasuo Sato, Takaharu Nagumo: Test Generation for Multiple-Threshold Gate-Delay Fault Model. Asian Test Symposium 2001: 244-
1999
3 Michinobu Nakao, Seiji Kobayashi, Kazumi Hatayama, Kazuhiko Iijima, Seiji Terada: Low overhead test point insertion for scan-based BIST. ITC 1999: 348-357
1997
2EEMichinobu Nakao, Kazumi Hatayama, Isao Higashi: Accelerated Test Points Selection Method for Scan-Based BIST. Asian Test Symposium 1997: 359-
1995
1EEHiroshi Date, Michinobu Nakao, Kazumi Hatayama: A parallel sequential test generation system DESCARTES based on real-valued logic simulation. Asian Test Symposium 1995: 252-258

Coauthor Index

1Hiroshi Date [1]
2Kazumi Hatayama [1] [2] [3] [4] [5] [6]
3Isao Higashi [2]
4Kazuhiko Iijima [3]
5Yoshikazu Kiyoshige [4] [5]
6Seiji Kobayashi [3]
7Takaharu Nagumo [4] [5]
8Koichiro Natsume [5]
9Yasuo Sato [4] [5] [6]
10Seiji Terada [3]

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)