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Nilanjan Mukherjee Vis

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*2009
34EENilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer: Defect Aware to Power Conscious Tests - The New DFT Landscape. VLSI Design 2009: 23-25
33EENilanjan Mukherjee, Artur Pogiel, Janusz Rajski, Jerzy Tyszer: High-Speed On-Chip Event Counters for Embedded Systems. VLSI Design 2009: 275-280
2008
32EENilanjan Mukherjee: Targeting "Zero DPPM" - Can we ever get there? DFT 2008: 163-163
2007
31EERadhika Vurputoor, Nilanjan Mukherjee, Jean Cabello, Michael J. Hancock: A Mesh Morphing Technique For Geometrically Dissimilar Tessellated Surfaces. IMR 2007: 315-334
30EEJerzy Tyszer, Janusz Rajski, Grzegorz Mrugalski, Nilanjan Mukherjee, Mark Kassab, Wu-Tung Cheng, Manish Sharma, Liyang Lai: X-Tolerant Compactor with On-Chip Registration and Signature-Based Diagnosis. IEEE Design & Test of Computers 24(5): 476-485 (2007)
2006
29EENilanjan Mukherjee: High Quality Bi-Linear Transfinite Meshing with Interior Point Constraints. IMR 2006: 309-323
28EEGrzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer: High Performance Dense Ring Generators. IEEE Trans. Computers 55(1): 83-87 (2006)
2005
27EEJay Jahangiri, Nilanjan Mukherjee, Wu-Tung Cheng, Subramanian Mahadevan, Ron Press: Achieving High Test Quality with Reduced Pin Count Testing. Asian Test Symposium 2005: 312-317
26EENilanjan Mukherjee: Improving Test Quality Using Test Data Compression. Asian Test Symposium 2005: 463
2004
25EENilanjan Mukherjee: Cost of Test - Taking Control. ITC 2004: 1431
24EEJanusz Rajski, Nilanjan Mukherjee, Jerzy Tyszer, Thomas Rinderknecht: Embedded Test for Low Cost Manufacturing. VLSI Design 2004: 21-23
23EEXiaogang Du, Sudhakar M. Reddy, Wu-Tung Cheng, Joseph Rayhawk, Nilanjan Mukherjee: At-Speed Built-in Self-Repair Analyzer for Embedded Word-Oriented Memories. VLSI Design 2004: 895-900
22EEGrzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer: Planar High Performance Ring Generators. VTS 2004: 193-198
21EEJanusz Rajski, Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee: Embedded deterministic test. IEEE Trans. on CAD of Integrated Circuits and Systems 23(5): 776-792 (2004)
2003
20EEYu Huang, Wu-Tung Cheng, Chien-Chung Tsai, Nilanjan Mukherjee, Sudhakar M. Reddy: Static Pin Mapping and SOC Test Scheduling for Cores with Multiple Test Sets. ISQED 2003: 99-104
19EEFrank Poehl, Matthias Beck, Ralf Arnold, Peter Muhmenthaler, Nagesh Tamarapalli, Mark Kassab, Nilanjan Mukherjee, Janusz Rajski: Industrial Experience with Adoption of EDT for Low-Cost Test without Concessions. ITC 2003: 1211-1220
18EEJanusz Rajski, Mark Kassab, Nilanjan Mukherjee, Nagesh Tamarapalli, Jerzy Tyszer, Jun Qian: Embedded Deterministic Test for Low-Cost Manufacturing. IEEE Design & Test of Computers 20(5): 58-66 (2003)
2002
17EENilanjan Mukherjee: A Hybrid, Variational 3D Smoother For Orphaned Shell Meshes. IMR 2002: 379-390
16EEJanusz Rajski, Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee, Rob Thompson, Kun-Han Tsai, Andre Hertwig, Nagesh Tamarapalli, Grzegorz Mrugalski, Geir Eide, Jun Qian: Embedded Deterministic Test for Low-Cost Manufacturing Test. ITC 2002: 301-310
15EEYu Huang, Sudhakar M. Reddy, Wu-Tung Cheng, Paul Reuter, Nilanjan Mukherjee, Chien-Chung Tsai, Omer Samman, Yahya Zaidan: Optimal Core Wrapper Width Selection and SOC Test Scheduling Based on 3-D Bin Packing Algorithm. ITC 2002: 74-82
14EEYu Huang, Nilanjan Mukherjee, Chien-Chung Tsai, Omer Samman, Yahya Zaidan, Yanping Zhang, Wu-Tung Cheng, Sudhakar M. Reddy: Constraint Driven Pin Mapping for Concurrent SOC Testing. VLSI Design 2002: 511-516
13EEYu Huang, Chien-Chung Tsai, Nilanjan Mukherjee, Omer Samman, Wu-Tung Cheng, Sudhakar M. Reddy: Synthesis of Scan Chains for Netlist Descriptions at RT-Level. J. Electronic Testing 18(2): 189-201 (2002)
12EEYu Huang, Wu-Tung Cheng, Chien-Chung Tsai, Nilanjan Mukherjee, Omer Samman, Yahya Zaidan, Sudhakar M. Reddy: On Concurrent Test of Core-Based SOC Design. J. Electronic Testing 18(4-5): 401-414 (2002)
2001
11EEYu Huang, Wu-Tung Cheng, Chien-Chung Tsai, Nilanjan Mukherjee, Omer Samman, Yahya Zaidan, Sudhakar M. Reddy: Resource Allocation and Test Scheduling for Concurrent Test of Core-Based SoC D. Asian Test Symposium 2001: 265-
10EENilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer: Testing Schemes for FIR Filter Structures. IEEE Trans. Computers 50(7): 674-688 (2001)
1998
9EENilanjan Mukherjee, Tapan J. Chakraborty, Sudipta Bhawmik: A BIST scheme for the detection of path-delay faults. ITC 1998: 422-
8EERamesh Karri, Nilanjan Mukherjee: Versatile BIST: an integrated approach to on-line/off-line BIST. ITC 1998: 910-917
7EENilanjan Mukherjee, Ramesh Karri: Versatile BIST: An Integrated Approach to On-line/Off-line BIST for Data-Dominated Architectures. J. Electronic Testing 13(2): 189-200 (1998)
1997
6 Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer: Parameterizable Testing Scheme for FIR Filters. ITC 1997: 694-703
5 Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer: Design of Testable Multipliers for Fixed-Width Data Paths. IEEE Trans. Computers 46(7): 795-810 (1997)
1995
4EEMark Kassab, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer: Software Accelerated Functional Fault Simulation for Data-Path Architectures. DAC 1995: 333-338
3EENilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer: On testable multipliers for fixed-width data path architectures. ICCAD 1995: 541-547
2EENilanjan Mukherjee, H. Kassab, Janusz Rajski, Jerzy Tyszer: Arithmetic built-in self test for high-level synthesis. VTS 1995: 132-139
1993
1 Thomas Charles Wilson, Nilanjan Mukherjee, M. K. Garg, Dilip K. Banerji: An Integrated and Accelerated ILP Solution for Scheduling, Module Allocation, and Binding in Datapath Synthesis. VLSI Design 1993: 192-197

Coauthor Index

1Ralf Arnold [19]
2Dilip K. Banerji [1]
3Matthias Beck [19]
4Sudipta Bhawmik [9]
5Jean Cabello [31]
6Tapan J. Chakraborty [9]
7Wu-Tung Cheng [11] [12] [13] [14] [15] [20] [23] [27] [30]
8Xiaogang Du [23]
9Geir Eide [16]
10M. K. Garg [1]
11Michael J. Hancock [31]
12Andre Hertwig [16]
13Yu Huang [11] [12] [13] [14] [15] [20]
14Jay Jahangiri [27]
15Ramesh Karri [7] [8]
16H. Kassab [2]
17Mark Kassab [4] [16] [18] [19] [21] [30]
18Liyang Lai [30]
19Subramanian Mahadevan [27]
20Grzegorz Mrugalski [16] [22] [28] [30]
21Peter Muhmenthaler [19]
22Frank Poehl [19]
23Artur Pogiel [33]
24Ron Press [27]
25Jun Qian [16] [18]
26Janusz Rajski [2] [3] [4] [5] [6] [10] [16] [18] [19] [21] [22] [24] [28] [30] [33] [34]
27Joseph Rayhawk [23]
28Sudhakar M. Reddy [11] [12] [13] [14] [15] [20] [23]
29Paul Reuter [15]
30Thomas Rinderknecht [24]
31Omer Samman [11] [12] [13] [14] [15]
32Manish Sharma [30]
33Nagesh Tamarapalli [16] [18] [19]
34Rob Thompson [16]
35Chien-Chung Tsai [11] [12] [13] [14] [15] [20]
36Kun-Han Tsai [16]
37Jerzy Tyszer [2] [3] [4] [5] [6] [10] [16] [18] [21] [22] [24] [28] [30] [33] [34]
38Radhika Vurputoor [31]
39Thomas Charles Wilson [1]
40Yahya Zaidan [11] [12] [14] [15]
41Yanping Zhang [14]

Colors in the list of coauthors

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)