Daniel Mozos Vis

*	2009
33	EE	Jose Antonio Valero, Julio Septién, Daniel Mozos, Hortensia Mecha: 3D FPGA resource management and fragmentation metric for hardware multitasking. IPDPS 2009: 1-7
	2008
32		Angel Luis González Bravo, Hortensia Mecha, Julio Septién, Sara Román Navarro, Daniel Mozos: Synthesis of relocatable tasks and implementation of a task communication bus in a general purpose Hw system. ERSA 2008: 307-308
31		Laura Sanchez, Julio Septién, Daniel Mozos, Hortensia Mecha, Angel Luis González Bravo: FPGA Resource Management Using Internal RAM as Aata Cache. ERSA 2008: 317-318
30		Jose Antonio Valero, Julio Septién, Daniel Mozos, Hortensia Mecha, Angel Luis González Bravo: Resource Management for Hw Multitasking in Three Dimensional FPGAs. ERSA 2008: 319-320
29		Jesús Fernández-Conde, Daniel Mozos: Pull vs. Hybrid: Comparing Scheduling Algorithms for Asymmetric Time-Constrained Environments. ICWN 2008: 222-228
28	EE	Julio Septién, Daniel Mozos, Hortensia Mecha, Jesús Tabero, Miguel Angel García de Dios: Perimeter quadrature-based metric for estimating FPGA fragmentation in 2D HW multitasking. IPDPS 2008: 1-8
27	EE	Javier Resano, Juan Antonio Clemente, Carlos Gonzalez, Daniel Mozos, Francky Catthoor: Efficiently scheduling runtime reconfigurations. ACM Trans. Design Autom. Electr. Syst. 13(4): (2008)
26	EE	Jesús Tabero, Julio Septién, Hortensia Mecha, Daniel Mozos: Allocation heuristics and defragmentation measures for reconfigurable systems management. Integration 41(2): 281-296 (2008)
	2007
25		Elena Perez Ramo, Javier Resano, Daniel Mozos, Francky Catthoor: Reducing the reconfiguration overhead: a survey of techniques. ERSA 2007: 191-194
24		Javier Resano, Juan Antonio Clemente, Carlos Gonzalez, Jose Luis Garcia, Daniel Mozos: HW implementation of an execution manager for reconfigurable systems. ERSA 2007: 71-77
23	EE	Javier Resano, Daniel Mozos, Francky Catthoor: A Hybrid Prefetch Scheduling Heuristic to Minimize at Run-Time the Reconfiguration Overhead of Dynamically Reconfigurable Hardware CoRR abs/0710.4796: (2007)
	2006
22	EE	Sara Román Navarro, Julio Septién, Hortensia Mecha, Daniel Mozos: Constant Complexity Management of 2D HW Multitasking in Run-Time Reconfigurable FPGAs. ARC 2006: 187-192
21	EE	Jesús Tabero, Julio Septién, Hortensia Mecha, Daniel Mozos: Task placement heuristic based on 3D-adjacency and look-ahead in reconfigurable systems. ASP-DAC 2006: 396-401
20	EE	Sara Román Navarro, Hortensia Mecha, Daniel Mozos, Julio Septién: Partition Based Dynamic 2D HW Multitasking Management. DSD 2006: 61-70
19	EE	Jesús Fernández-Conde, Daniel Mozos: Adaptive Hybrid Broadcast for Data Dissemination in Time-Constrained Asymmetric Communication Environments. EUROMICRO-SEAA 2006: 438-447
18	EE	Julio Septién, Hortensia Mecha, Daniel Mozos, Jesús Tabero: 2D defragmentation heuristics for hardware multitasking on reconfigurable devices. IPDPS 2006
17	EE	Elena Perez Ramo, Javier Resano, Daniel Mozos, Francky Catthoor: A configuration memory hierarchy for fast reconfiguration with reduced energy consumption overhead. IPDPS 2006
	2005
16	EE	Javier Resano, Daniel Mozos, Francky Catthoor: A Hybrid Prefetch Scheduling Heuristic to Minimize at Run-Time the Reconfiguration Overhead of Dynamically Reconfigurable Hardware. DATE 2005: 106-111
15	EE	Javier Resano, Daniel Mozos, Diederik Verkest, Francky Catthoor: A Reconfiguration Manager for Dynamically Reconfigurable Hardware. IEEE Design & Test of Computers 22(5): 452-460 (2005)
	2004
14	EE	Javier Resano, Daniel Mozos: Specific scheduling support to minimize the reconfiguration overhead of dynamically reconfigurable hardware. DAC 2004: 119-124
13	EE	Jesús Tabero, Julio Septién, Hortensia Mecha, Daniel Mozos: A Low Fragmentation Heuristic for Task Placement in 2D RTR HW Management. FPL 2004: 241-250
12	EE	Javier Resano, Diederik Verkest, Daniel Mozos, Serge Vernalde, Francky Catthoor: A hybrid design-time/run-time scheduling flow to minimise the reconfiguration overhead of FPGAs. Microprocessors and Microsystems 28(5-6): 291-301 (2004)
	2003
11		Javier Resano, Diederik Verkest, Daniel Mozos, Serge Vernalde, Francky Catthoor: Run-Time Scheduling for Multimedia Applications on Dynamically Reconfigurable Systems. ESTImedia 2003: 156-162
10	EE	Javier Resano, Diederik Verkest, Daniel Mozos, Serge Vernalde, Francky Catthoor: Application of Task Concurrency Management on Dynamically Reconfigurable Hardware Platforms. FCCM 2003: 278-279
9	EE	Javier Resano, Daniel Mozos, Diederik Verkest, Serge Vernalde, Francky Catthoor: Run-Time Minimization of Reconfiguration Overhead in Dynamically Reconfigurable Systems. FPL 2003: 585-594
8	EE	Javier Resano, Daniel Mozos, Elena Pérez-Miñana, Hortensia Mecha, Julio Septién: A Hardware/Software Partitioning and Scheduling Approach for Embedded Systems with Low-Power and High Performance Requirements. PATMOS 2003: 580-589
7	EE	Javier Resano, M. Elena Pérez, Daniel Mozos, Hortensia Mecha, Julio Septién: Analyzing communication overheads during hardware/software partitioning. Microelectronics Journal 34(11): 1001-1007 (2003)
	1999
6	EE	J. A. Maestro, Daniel Mozos, Román Hermida: The Heterogeneous Structure Problem in Hardware/Software Codesign: A Macroscopic Approach. DATE 1999: 766-767
	1998
5	EE	J. A. Maestro, Daniel Mozos, Hortensia Mecha: A Macroscopic Time and Cost Estimation Model Allowing Task Parallelism and Hardware Sharing for the Codesign Partitioning Process. DATE 1998: 218-225
4	EE	J. A. Maestro, Daniel Mozos, Julio Septién: A Grouping Partitioning Technique with Automatic Criterion Selection for the Codesign Proces. EUROMICRO 1998: 10309-10312
	1994
3	EE	Hortensia Mecha, Milagros Fernández, Román Hermida, Daniel Mozos, Katzalin Olcoz: Clock cycle estimation based on dead time and control unit area minimization. Microprocessing and Microprogramming 40(10-12): 821-824 (1994)
	1993
2	EE	R. Moreno, Román Hermida, Daniel Mozos, Katzalin Olcoz: Global hardware synthesis guided by realistic probability computation. Microprocessing and Microprogramming 39(2-5): 233-236 (1993)
1	EE	Katzalin Olcoz, Francisco Tirado, Daniel Mozos, Julio Septién, R. Moreno: Data path structures and heuristics for testable allocation in high level synthesis. Microprocessing and Microprogramming 39(2-5): 263-266 (1993)

Coauthor Index

1	Angel Luis González Bravo	[30] [31] [32]
2	Francky Catthoor	[9] [10] [11] [12] [15] [16] [17] [23] [25] [27]
3	Juan Antonio Clemente	[24] [27]
4	Miguel Angel García de Dios	[28]
5	Milagros Fernández	[3]
6	Jesús Fernández-Conde	[19] [29]
7	Jose Luis Garcia	[24]
8	Carlos Gonzalez	[24] [27]
9	Román Hermida	[2] [3] [6]
10	J. A. Maestro	[4] [5] [6]
11	Hortensia Mecha	[3] [5] [7] [8] [13] [18] [20] [21] [22] [26] [28] [30] [31] [32] [33]
12	R. Moreno	[1] [2]
13	Sara Román Navarro	[20] [22] [32]
14	Katzalin Olcoz	[1] [2] [3]
15	M. Elena Pérez	[7]
16	Elena Pérez-Miñana	[8]
17	Elena Perez Ramo	[17] [25]
18	Javier Resano	[7] [8] [9] [10] [11] [12] [14] [15] [16] [17] [23] [24] [25] [27]
19	Laura Sanchez	[31]
20	Julio Septién	[1] [4] [7] [8] [13] [18] [20] [21] [22] [26] [28] [30] [31] [32] [33]
21	Jesús Tabero	[13] [18] [21] [26] [28]
22	Francisco Tirado	[1]
23	Jose Antonio Valero	[30] [33]
24	Diederik Verkest	[9] [10] [11] [12] [15]
25	Serge Vernalde	[9] [10] [11] [12]

Colors in the list of coauthors