| |
| * | 1992 | |
|---|---|---|
| 1 | Shoji Kawahito, Y. Mitsui, Makoto Ishida, Tetsuro Nakamura: Parallel Hardware Algorithms with Redundant Number Representations for Multiple-Valued Arithmetic VLSI. ISMVL 1992: 337-345 | |
| 1 | Makoto Ishida | [1] |
| 2 | Shoji Kawahito | [1] |
| 3 | Tetsuro Nakamura | [1] |