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Heinrich Meyr Vis

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*2009
102EEJianjiang Ceng, Weihua Sheng, Jerónimo Castrillón, Anastasia Stulova, Rainer Leupers, Gerd Ascheid, Heinrich Meyr: A high-level virtual platform for early MPSoC software development. CODES+ISSS 2009: 11-20
101EELei Gao, Jia Huang, Jianjiang Ceng, Rainer Leupers, Gerd Ascheid, Heinrich Meyr: TotalProf: a fast and accurate retargetable source code profiler. CODES+ISSS 2009: 305-314
100EEKingshuk Karuri, Rainer Leupers, Gerd Ascheid, Heinrich Meyr: A Generic Design Flow for Application Specific Processor Customization through Instruction-Set Extensions (ISEs). SAMOS 2009: 204-214
99EETorsten Kempf, Stefan Wallentowitz, Gerd Ascheid, Rainer Leupers, Heinrich Meyr: A Workbench for Analytical and Simulation Based Design Space Exploration of Software Defined Radios. VLSI Design 2009: 281-286
98EEAnupam Chattopadhyay, Harold Ishebabi, Xiaolin Chen, Z. Rakosi, Kingshuk Karuri, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr: Pre- and postfabrication architecture exploration for partially reconfigurable VLIW processors. ACM Trans. Embedded Comput. Syst. 8(2): (2009)
97EEVenkatesh Ramakrishnan, Ernst Martin Witte, Torsten Kempf, David Kammler, Gerd Ascheid, Heinrich Meyr, Marc Adrat, Markus Antweiler: Efficient And Portable SDR Waveform Development: The Nucleus Concept CoRR abs/0906.3313: (2009)
96EEErnst Martin Witte, Filippo Borlenghi, Gerd Ascheid, Rainer Leupers, Heinrich Meyr: A Scalable VLSI Architecture for Soft-Input Soft-Output Depth-First Sphere Decoding CoRR abs/0910.3427: (2009)
95EEManuel Hohenauer, Felix Engel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr: A SIMD optimization framework for retargetable compilers. TACO 6(1): (2009)
2008
94EELei Gao, Kingshuk Karuri, Stefan Kraemer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr: Multiprocessor performance estimation using hybrid simulation. DAC 2008: 325-330
93EEJianjiang Ceng, Jerónimo Castrillón, Weihua Sheng, Hanno Scharwächter, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Tsuyoshi Isshiki, Hiroaki Kunieda: MAPS: an integrated framework for MPSoC application parallelization. DAC 2008: 754-759
92EEAnupam Chattopadhyay, Xiaolin Chen, Harold Ishebabi, Rainer Leupers, Gerd Ascheid, Heinrich Meyr: High-level Modelling and Exploration of Coarse-grained Re-configurable Architectures. DATE 2008: 1334-1339
91EEManuel Hohenauer, Felix Engel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gerrit Bette, Balpreet Singh: Retargetable Code Optimization for Predicated Execution. DATE 2008: 1492-1497
90EEI-Wei Lai, Susanne Godtmann, Tzi-Dar Chiueh, Gerd Ascheid, Heinrich Meyr: Asymptotic BER Analysis for MIMO-BICM with Zero-Forcing Detectors Assuming Imperfect CSI. ICC 2008: 1238-1242
89EEMarkus Jordan, Martin Senst, Gerd Ascheid, Heinrich Meyr: Long-Term Beamforming in Single Frequency Networks using Semidefinite Relaxation. VTC Spring 2008: 275-279
88EEAnupam Chattopadhyay, Harold Ishebabi, Xiaolin Chen, Z. Rakosi, Kingshuk Karuri, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr: Prefabrication and postfabrication architecture exploration for partially reconfigurable VLIW processors. ACM Trans. Embedded Comput. Syst. 7(4): (2008)
87EEKingshuk Karuri, Anupam Chattopadhyay, Xiaolin Chen, David Kammler, Ling Hao, Rainer Leupers, Heinrich Meyr, Gerd Ascheid: A Design Flow for Architecture Exploration and Implementation of Partially Reconfigurable Processors. IEEE Trans. VLSI Syst. 16(10): 1281-1294 (2008)
86EEAndreas Wieferink, Tim Kogel, Olaf Zerres, Rainer Leupers, Heinrich Meyr: SoC multiprocessor debugging and synchronisation using generic dynamic-connect debugger frontends. IJES 3(3): 109-118 (2008)
85EETim Kogel, Malte Doerper, Torsten Kempf, Andreas Wieferink, Rainer Leupers, Heinrich Meyr: Virtual architecture mapping: a SystemC based methodology for architectural exploration of System-on-Chips. IJES 3(3): 150-159 (2008)
84EEDiandian Zhang, Anupam Chattopadhyay, David Kammler, Ernst Martin Witte, Gerd Ascheid, Rainer Leupers, Heinrich Meyr: Power-efficient Instruction Encoding Optimization for Various Architecture Classes. JCP 3(3): 25-38 (2008)
2007
83EELei Gao, Stefan Kraemer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr: A fast and generic hybrid simulation approach using C virtual machine. CASES 2007: 3-12
82EEHanno Scharwächter, Jonghee M. Yoon, Rainer Leupers, Yunheung Paek, Gerd Ascheid, Heinrich Meyr: A code-generator generator for multi-output instructions. CODES+ISSS 2007: 131-136
81EEStefan Kraemer, Lei Gao, Jan Weinstock, Rainer Leupers, Gerd Ascheid, Heinrich Meyr: HySim: a fast simulation framework for embedded software development. CODES+ISSS 2007: 75-80
80EEStefan Kraemer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr: Interactive presentation: SoftSIMD - exploiting subword parallelism using source code transformations. DATE 2007: 1349-1354
79EEAnupam Chattopadhyay, W. Ahmed, Kingshuk Karuri, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr: Design space exploration of partially re-configurable embedded processors. DATE 2007: 319-324
78EEMartin Senst, Markus Jordan, Meik Dorpinghaus, Michael Farber, Gerd Ascheid, Heinrich Meyr: Joint Reduction of Peak-to-Average Power Ratio and Out-of-Band Power in OFDM Systems. GLOBECOM 2007: 3812-3816
77EEKingshuk Karuri, Anupam Chattopadhyay, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr: Increasing data-bandwidth to instruction-set extensions through register clustering. ICCAD 2007: 166-171
76EEAnupam Chattopadhyay, Z. Rakosi, Kingshuk Karuri, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr: Pre- and Post-Fabrication Architecture Exploration for Partially Reconfigurable VLIW Processors. IEEE International Workshop on Rapid System Prototyping 2007: 189-194
75EEMarkus Jordan, Gerd Ascheid, Heinrich Meyr: Performance Evaluation of Opportunistic Beamforming with SINR Prediction for HSDPA. VTC Spring 2007: 1652-1656
74EESusanne Godtmann, André Pollok, Niels Hadaschik, Gerd Ascheid, Heinrich Meyr: On the Influence of Pilot Symbol and Data Symbol Positioning on Turbo Synchronization. VTC Spring 2007: 1723-1726
73EEHanno Scharwächter, David Kammler, Andreas Wieferink, Manuel Hohenauer, Kingshuk Karuri, Jianjiang Ceng, Rainer Leupers, Gerd Ascheid, Heinrich Meyr: ASIP architecture exploration for efficient IPSec encryption: A case study. ACM Trans. Embedded Comput. Syst. 6(2): (2007)
2006
72EEManuel Hohenauer, Christoph Schumacher, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Hans van Someren: Retargetable code optimization with SIMD instructions. CODES+ISSS 2006: 148-153
71EETorsten Kempf, Kingshuk Karuri, Stefan Wallentowitz, Gerd Ascheid, Rainer Leupers, Heinrich Meyr: A SW performance estimation framework for early system-level-design using fine-grained instrumentation. DATE 2006: 468-473
70EEAnupam Chattopadhyay, B. Geukes, David Kammler, Ernst Martin Witte, Oliver Schliebusch, Harold Ishebabi, Rainer Leupers, Gerd Ascheid, Heinrich Meyr: Automatic ADL-based operand isolation for embedded processors. DATE 2006: 600-605
69EEHanno Scharwächter, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr: An interprocedural code optimization technique for network processors using hardware multi-threading support. DATE 2006: 919-924
68EEKingshuk Karuri, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Monu Kedia: Design and implementation of a modular and portable IEEE 754 compliant floating-point unit. DATE Designers' Forum 2006: 221-226
67EELuca Fanucci, Michele Cassiano, Sergio Saponara, David Kammler, Ernst Martin Witte, Oliver Schliebusch, Gerd Ascheid, Rainer Leupers, Heinrich Meyr: ASIP design and synthesis for non linear filtering in image processing. DATE Designers' Forum 2006: 233-238
66EEKingshuk Karuri, Christian Huben, Rainer Leupers, Gerd Ascheid, Heinrich Meyr: Memory Access Micro-Profiling for ASIP Design. DELTA 2006: 255-262
65EEAnupam Chattopadhyay, Arnab Sinha, Diandian Zhang, Rainer Leupers, Gerd Ascheid, Heinrich Meyr: Integrated Verification Approach during ADL-Driven Processor Design. IEEE International Workshop on Rapid System Prototyping 2006: 110-118
64EEHarold Ishebabi, Gerd Ascheid, Heinrich Meyr, O. Atak, A. Atalar, E. Arikan: An efficient parallelization technique for high throughput FFT-ASIPs. ISCAS 2006
63EEPeter Wintermayr, Reiner W. Hartenstein, Heinrich Meyr, Steve Leibson: Flexibility and low power: a contradiction in terms? ISLPED 2006: 375
62EEJianjiang Ceng, Weihua Sheng, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun: Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting. VLSI Signal Processing 43(2-3): 235-246 (2006)
2005
61EEMohammad Mostafizur Rahman Mozumdar, Kingshuk Karuri, Anupam Chattopadhyay, Stefan Kraemer, Hanno Scharwächter, Heinrich Meyr, Gerd Ascheid, Rainer Leupers: Instruction Set Customization of Application Specific Processors for Network Processing: A Case Study. ASAP 2005: 154-160
60EEOliver Schliebusch, Anupam Chattopadhyay, David Kammler, Gerd Ascheid, Rainer Leupers, Heinrich Meyr, Tim Kogel: A framework for automated and optimized ASIP implementation supporting multiple hardware description languages. ASP-DAC 2005: 280-285
59EEAndreas Wieferink, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Tom Michiels, Achim Nohl, Tim Kogel: Retargetable generation of TLM bus interfaces for MP-SoC platforms. CODES+ISSS 2005: 249-254
58EEKingshuk Karuri, Mohammad Abdullah Al Faruque, Stefan Kraemer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr: Fine-grained application source code profiling for ASIP design. DAC 2005: 329-334
57EEJianjiang Ceng, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun: C Compiler Retargeting Based on Instruction Semantics Models. DATE 2005: 1150-1155
56EETorsten Kempf, Malte Doerper, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Tim Kogel, Bart Vanthournout: A Modular Simulation Framework for Spatial and Temporal Task Mapping onto Multi-Processor SoC Platforms. DATE 2005: 876-881
55EEOliver Schliebusch, Anupam Chattopadhyay, Ernst Martin Witte, David Kammler, Gerd Ascheid, Rainer Leupers, Heinrich Meyr: Optimization Techniques for ADL-Driven RTL Processor Synthesis. IEEE International Workshop on Rapid System Prototyping 2005: 165-171
2004
54EETim Kogel, Heinrich Meyr: Heterogeneous MP-SoC: the solution to energy-efficient signal processing. DAC 2004: 686-691
53EEGunnar Braun, Achim Nohl, Weihua Sheng, Jianjiang Ceng, Manuel Hohenauer, Hanno Scharwächter, Rainer Leupers, Heinrich Meyr: A novel approach for flexible and consistent ADL-driven ASIP design. DAC 2004: 717-722
52EEAndreas Wieferink, Tim Kogel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun, Achim Nohl: A System Level Processor/Communication Co-Exploration Methodology for Multi-Processor System-on-Chip Platform. DATE 2004: 1256-1263
51EEManuel Hohenauer, Hanno Scharwächter, Kingshuk Karuri, Oliver Wahlen, Tim Kogel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun, Hans van Someren: A Methodology and Tool Suite for C Compiler Generation from ADL Processor Models. DATE 2004: 1276-1283
50EEOliver Schliebusch, Anupam Chattopadhyay, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Mario Steinert, Gunnar Braun, Achim Nohl: RTL Processor Synthesis for Architecture Exploration and Implementation. DATE 2004: 156-160
49EETim Kogel, Malte Doerper, Torsten Kempf, Andreas Wieferink, Rainer Leupers, Gerd Ascheid, Heinrich Meyr: Virtual Architecture Mapping: A SystemC Based Methodology for Architectural Exploration of System-on-Chip Designs. SAMOS 2004: 138-148
48EEAndreas Wieferink, Malte Doerper, Tim Kogel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr: Early ISS Integration into Network-on-Chip Designs. SAMOS 2004: 443-452
47EEJianjiang Ceng, Weihua Sheng, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun: Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting. SAMOS 2004: 463-473
46EEHanno Scharwächter, David Kammler, Andreas Wieferink, Manuel Hohenauer, Kingshuk Karuri, Jianjiang Ceng, Rainer Leupers, Gerd Ascheid, Heinrich Meyr: ASIP Architecture Exploration for Efficient Ipsec Encryption: A Case Study. SCOPES 2004: 33-46
45EERudolf Mathar, Heinrich Meyr: Stochastic modeling of the convergence behavior of concatenated codes. VTC Fall (2) 2004: 1263-1265
44EEGunnar Braun, Achim Nohl, Andreas Hoffmann, Oliver Schliebusch, Rainer Leupers, Heinrich Meyr: A universal technique for fast and flexible instruction-set architecture simulation. IEEE Trans. on CAD of Integrated Circuits and Systems 23(12): 1625-1639 (2004)
2003
43EETim Kogel, Malte Doerper, Andreas Wieferink, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Serge Goossens: A modular simulation framework for architectural exploration of on-chip interconnection networks. CODES+ISSS 2003: 7-12
42EEAchim Nohl, Volker Greive, Gunnar Braun, Andreas Hoffmann, Rainer Leupers, Oliver Schliebusch, Heinrich Meyr: Instruction encoding synthesis for architecture exploration using hierarchical processor models. DAC 2003: 262-267
41EEGunnar Braun, Andreas Wieferink, Oliver Schliebusch, Rainer Leupers, Heinrich Meyr, Achim Nohl: Processor/Memory Co-Exploration on Multiple Abstraction Levels. DATE 2003: 10966-10973
40EEOliver Wahlen, Manuel Hohenauer, Gunnar Braun, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Xiaoning Nie: Extraction of Efficient Instruction Schedulers from Cycle-True Processor Models. SCOPES 2003: 167-181
39EEOliver Wahlen, Manuel Hohenauer, Rainer Leupers, Heinrich Meyr: Instruction Scheduler Generation for Retargetable Compilation. IEEE Design & Test of Computers 20(1): 34-41 (2003)
38EETilman Glökler, Andreas Hoffmann, Heinrich Meyr: Methodical Low-Power ASIP Design Space Exploration. VLSI Signal Processing 33(3): 229-246 (2003)
2002
37EEAchim Nohl, Gunnar Braun, Oliver Schliebusch, Rainer Leupers, Heinrich Meyr, Andreas Hoffmann: A universal technique for fast and flexible instruction-set architecture simulation. DAC 2002: 22-27
36EETobias Noll, Heinrich Meyr: Designing SoC's. ISLPED 2002: 283
35EEOliver Wahlen, Tilman Glökler, Achim Nohl, Andreas Hoffmann, Rainer Leupers, Heinrich Meyr: Application specific compiler/architecture codesign: a case study. LCTES-SCOPES 2002: 185-193
34EEOliver Schliebusch, Andreas Hoffmann, Achim Nohl, Gunnar Braun, Heinrich Meyr: Architecture Implementation Using the Machine Description Language LISA. VLSI Design 2002: 239-244
2001
33EEHolger Keding, Martin Coors, Olaf Lüthje, Heinrich Meyr: Fast Bit-True Simulation. DAC 2001: 708-713
32EEA. Lock, Raul Camposano, Heinrich Meyr: The programmable platform: does one size fit all? DATE 2001: 226-227
31EEAndreas Hoffmann, Achim Nohl, Stefan Pees, Gunnar Braun, Heinrich Meyr: Generating production quality software development tools using a machine description language. DATE 2001: 674-678
30EEAndreas Hoffmann, Tim Kogel, Heinrich Meyr: A framework for fast hardware-software co-simulation. DATE 2001: 760-765
29EEAndreas Hoffmann, Oliver Schliebusch, Achim Nohl, Gunnar Braun, Oliver Wahlen, Heinrich Meyr: A Methodology for the Design of Application Specific Instruction Set Processors (ASIP) using the Machine Description Language LISA. ICCAD 2001: 625-630
28 Gunnar Braun, Andreas Hoffmann, Achim Nohl, Heinrich Meyr: Using static scheduling techniques for the retargeting of high speed, compiled simulators for embedded processors from an abstract machine description. ISSS 2001: 57-62
27EEAndreas Hoffmann, Tim Kogel, Achim Nohl, Gunnar Braun, Oliver Schliebusch, Oliver Wahlen, Andreas Wieferink, Heinrich Meyr: A novel methodology for the design of application-specificinstruction-set processors (ASIPs) using a machine description language. IEEE Trans. on CAD of Integrated Circuits and Systems 20(11): 1338-1354 (2001)
2000
26EEJens Horstmannshoff, Heinrich Meyr: Efficient building block based RTL code generation from synchronous data flow graphs. DAC 2000: 552-555
25EEStefan Pees, Andreas Hoffmann, Heinrich Meyr: Retargeting of Compiled Simulators for Digital Signal Processors Using a Machine Description Language. DATE 2000: 669-673
24 Michael Speth, Alexander Jansen, Heinrich Meyr: Iterative Multiuser Detection for Bit Interleaved Coed Modulation. ICC (2) 2000: 894-898
23EEStefan Pees, Andreas Hoffmann, Heinrich Meyr: Retargetable compiled simulation of embedded processors using a machine description language. ACM Trans. Design Autom. Electr. Syst. 5(4): 815-834 (2000)
1999
22EEStefan Pees, Andreas Hoffmann, Vojin Zivojnovic, Heinrich Meyr: LISA - Machine Description Language for Cycle-Accurate Models of Programmable DSP Architectures. DAC 1999: 933-938
21EEJens Horstmannshoff, Heinrich Meyr: Optimized System Synthesis of Complex RT Level Building Blocks from Multirate Dataflow Graphs. ISSS 1999: 38-43
1998
20EEHolger Keding, Markus Willems, Martin Coors, Heinrich Meyr: FRIDGE: A Fixed-Point Design and Simulation Environment. DATE 1998: 429-435
1997
19EEJens Horstmannshoff, Thorsten Grötker, Heinrich Meyr: Mapping multirate dataflow to complex RT level hardware models. ASAP 1997: 283-
18EEStefan Pees, Martin Vaupel, Vojin Zivojnovic, Heinrich Meyr: On core and more: a design perspective for systems-on-a-chip. ASAP 1997: 448-457
17EEMarkus Willems, Volker Bürsgens, Holger Keding, Thorsten Grötker, Heinrich Meyr: System Level Fixed-Point Design Based on an Interpolative Approach. DAC 1997: 293-298
16EEThorsten Grötker, R. Schoenen, Heinrich Meyr: PCC: a modeling technique for mixed control/data flow systems. ED&TC 1997: 482-486
15EEVojin Zivojnovic, Steven W. K. Tjiang, Heinrich Meyr: Compiled Simulation of Programmable DSP Architectures. VLSI Signal Processing 16(1): 73-80 (1997)
1996
14EEVojin Zivojnovic, Heinrich Meyr: Compiled HW/SW Co-Simulation. DAC 1996: 690-695
13EEVojin Zivojnovic, Stefan Pees, C. Schälger, Markus Willems, R. Schoenen, Heinrich Meyr: DSP Processor/Compiler Co-Design: A Quantitative Approach. ISSS 1996: 108-
12 Herbert Dawid, Heinrich Meyr: The Differential CORDIC Algorithm: Constant Scale Factor Redundant Implementation without Correcting Iterations. IEEE Trans. Computers 45(3): 307-318 (1996)
11EEHerbert Dawid, Gerhard Fettweis, Heinrich Meyr: A CMOS IC for Gb/s Viterbi decoding: system design and VLSI implementation. IEEE Trans. VLSI Syst. 4(1): 17-31 (1996)
1995
10EEPeter Zepter, Thorsten Grötker, Heinrich Meyr: Digital Receiver Design Using VHDL Generation from Data Flow Graphs. DAC 1995: 228-233
9 Claus Schotten, Heinrich Meyr: Test Point Insertion for an Area Efficient BIST. ITC 1995: 515-523
1994
8 Martin Vaupel, Heinrich Meyr: High Speed FIR-Filter Architectures with Scalable Sample Rates. ISCAS 1994: 127-130
7 Francky Catthoor, Ed F. Deprettere, Yu Hen Hu, Jan M. Rabaey, Heinrich Meyr, Lothar Thiele: Is it Possible to achieve a Teraflop/s on a chip? From High Performance Algorithms to Architectures. ISCAS 1994: 129-136
6EEOlaf J. Joeressen, Martin Vaupel, Heinrich Meyr: High-speed VLSI architectures for soft-output viterbi decoding. VLSI Signal Processing 8(2): 169-181 (1994)
1993
5 K. ten Hagen, Heinrich Meyr: Partitioning and Surmounting the Software-Hardware Abstraction Gap in an ASIC Design Project. ICCD 1993: 462-465
4 Vojin Zivojnovic, Heinrich Meyr: Design of optimum interpolation filters for digital demodulators. ISCAS 1993: 140-143
3 Sebastian Ritz, Matthias Pankert, Vojin Zivojnovic, Heinrich Meyr: High-Level Software Synthesis for the Design of Communication Systems. IEEE Journal on Selected Areas in Communications 11(3): 348-358 (1993)
1991
2EEGerhard Fettweis, Heinrich Meyr: Feedforward architectures for parallel Viterbi decoding. VLSI Signal Processing 3(1-2): 105-119 (1991)
1990
1 Gerhard Fettweis, Heinrich Meyr: High-Rate Viterbi Processor: A Systolic Array Solution. IEEE Journal on Selected Areas in Communications 8(8): 1520-1534 (1990)

Coauthor Index

1Marc Adrat [97]
2W. Ahmed [79]
3Markus Antweiler [97]
4E. Arikan [64]
5Gerd Ascheid [40] [43] [46] [47] [48] [49] [50] [51] [52] [55] [56] [57] [58] [59] [60] [61] [62] [64] [65] [66] [67] [68] [69] [70] [71] [72] [73] [74] [75] [76] [77] [78] [79] [80] [81] [82] [83] [84] [87] [88] [89] [90] [91] [92] [93] [94] [95] [96] [97] [98] [99] [100] [101] [102]
6O. Atak [64]
7A. Atalar [64]
8Gerrit Bette [91]
9Filippo Borlenghi [96]
10Gunnar Braun [27] [28] [29] [31] [34] [37] [40] [41] [42] [44] [47] [50] [51] [52] [53] [57] [62]
11Volker Bürsgens [17]
12Raul Camposano [32]
13Michele Cassiano [67]
14Jerónimo Castrillón [93] [102]
15Francky Catthoor [7]
16Jianjiang Ceng [46] [47] [53] [57] [62] [73] [93] [101] [102]
17Anupam Chattopadhyay [50] [55] [60] [61] [65] [70] [76] [77] [79] [84] [87] [88] [92] [98]
18Xiaolin Chen [87] [88] [92] [98]
19Tzi-Dar Chiueh [90]
20Martin Coors [20] [33]
21Herbert Dawid [11] [12]
22Ed F. Deprettere [7]
23Malte Doerper [43] [48] [49] [56] [85]
24Meik Dorpinghaus [78]
25Felix Engel [91] [95]
26Luca Fanucci [67]
27Michael Farber [78]
28Mohammad Abdullah Al Faruque [58]
29Gerhard Fettweis [1] [2] [11]
30Lei Gao [81] [83] [94] [101]
31B. Geukes [70]
32Tilman Glökler [35] [38]
33Susanne Godtmann [74] [90]
34Serge Goossens [43]
35Volker Greive [42]
36Thorsten Grötker [10] [16] [17] [19]
37Niels Hadaschik [74]
38K. ten Hagen [5]
39Ling Hao [87]
40Reiner W. Hartenstein [63]
41Andreas Hoffmann [22] [23] [25] [27] [28] [29] [30] [31] [34] [35] [37] [38] [42] [44]
42Manuel Hohenauer [39] [40] [46] [47] [51] [53] [57] [62] [69] [72] [73] [77] [91] [95]
43Jens Horstmannshoff [19] [21] [26]
44Yu Hen Hu [7]
45Jia Huang [101]
46Christian Huben [66]
47Harold Ishebabi [64] [70] [88] [92] [98]
48Tsuyoshi Isshiki [93]
49Alexander Jansen [24]
50Olaf J. Joeressen [6]
51Markus Jordan [75] [78] [89]
52David Kammler [46] [55] [60] [67] [70] [73] [76] [79] [84] [87] [88] [97] [98]
53Kingshuk Karuri [46] [51] [58] [61] [66] [68] [71] [73] [76] [77] [79] [87] [88] [94] [98] [100]
54Monu Kedia [68]
55Holger Keding [17] [20] [33]
56Torsten Kempf [49] [56] [71] [85] [97] [99]
57Tim Kogel [27] [30] [43] [48] [49] [51] [52] [54] [56] [59] [60] [85] [86]
58Stefan Kraemer [58] [61] [80] [81] [83] [94]
59Hiroaki Kunieda [93]
60I-Wei Lai [90]
61Steve Leibson [63]
62Rainer Leupers [35] [37] [39] [40] [41] [42] [43] [44] [46] [47] [48] [49] [50] [51] [52] [53] [55] [56] [57] [58] [59] [60] [61] [62] [65] [66] [67] [68] [69] [70] [71] [72] [73] [76] [77] [79] [80] [81] [82] [83] [84] [85] [86] [87] [88] [91] [92] [93] [94] [95] [96] [98] [99] [100] [101] [102]
63A. Lock [32]
64Olaf Lüthje [33]
65Rudolf Mathar [45]
66Tom Michiels [59]
67Mohammad Mostafizur Rahman Mozumdar [61]
68Xiaoning Nie [40]
69Achim Nohl [27] [28] [29] [31] [34] [35] [37] [41] [42] [44] [50] [52] [53] [59]
70Tobias Noll [36]
71Yunheung Paek [82]
72Matthias Pankert [3]
73Stefan Pees [13] [18] [22] [23] [25] [31]
74André Pollok [74]
75Jan M. Rabaey [7]
76Z. Rakosi [76] [88] [98]
77Venkatesh Ramakrishnan [97]
78Sebastian Ritz [3]
79Sergio Saponara [67]
80C. Schälger [13]
81Hanno Scharwächter [46] [51] [53] [61] [69] [73] [82] [93]
82Oliver Schliebusch [27] [29] [34] [37] [41] [42] [44] [50] [55] [60] [67] [70]
83R. Schoenen [13] [16]
84Claus Schotten [9]
85Christoph Schumacher [72]
86Martin Senst [78] [89]
87Weihua Sheng [47] [53] [62] [93] [102]
88Balpreet Singh [91]
89Arnab Sinha [65]
90Hans van Someren [51] [72]
91Michael Speth [24]
92Mario Steinert [50]
93Anastasia Stulova [102]
94Lothar Thiele [7]
95Steven W. K. Tjiang [15]
96Bart Vanthournout [56]
97Martin Vaupel [6] [8] [18]
98Oliver Wahlen [27] [29] [35] [39] [40] [51]
99Stefan Wallentowitz [71] [99]
100Jan Weinstock [81]
101Andreas Wieferink [27] [41] [43] [46] [48] [49] [52] [59] [73] [85] [86]
102Markus Willems [13] [17] [20]
103Peter Wintermayr [63]
104Ernst Martin Witte [55] [67] [70] [84] [96] [97]
105Jonghee M. Yoon [82]
106Peter Zepter [10]
107Olaf Zerres [86]
108Diandian Zhang [65] [84]
109Vojin Zivojnovic [3] [4] [13] [14] [15] [18] [22]

Colors in the list of coauthors

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)