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Kishore N. Menezes Vis

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*2000
12EEJay Bharadwaj, William Y. Chen, Weihaw Chuang, Gerolf Hoflehner, Kishore N. Menezes, Kalyan Muthukumar, Jim Pierce: The Intel IA-64 Compiler Code Generator. IEEE Micro 20(5): 44-53 (2000)
11EEThomas M. Conte, Kishore N. Menezes, Sumedh W. Sathaye, Mark C. Toburen: System-level power consumption modeling and tradeoff analysis techniques for superscalar processor design. IEEE Trans. VLSI Syst. 8(2): 129-137 (2000)
10EEJay Bharadwaj, Kishore N. Menezes, Chris McKinsey: Wavefront Scheduling: Path Based Data Representation and Scheduling of Subgraphs. J. Instruction-Level Parallelism 2: (2000)
1999
9EEJay Bharadwaj, Kishore N. Menezes, Chris McKinsey: Wavefront Scheduling: Path based Data Representation and Scheduling of Subgraphs. MICRO 1999: 262-271
1998
8EEEmre Özer, Sumedh W. Sathaye, Kishore N. Menezes, Sanjeev Banerjia, Matthew D. Jennings, Thomas M. Conte: A Fast Interrupt Handling Scheme for VLIW Processors. IEEE PACT 1998: 136-141
7 Sanjeev Banerjia, Sumedh W. Sathaye, Kishore N. Menezes, Thomas M. Conte: MPS: Miss-Path Scheduling for Multiple-Issue Processors. IEEE Trans. Computers 47(12): 1382-1397 (1998)
1997
6EEKishore N. Menezes, Sumedh W. Sathaye, Thomas M. Conte: Path Prediction for High Issue-Rate Processors. IEEE PACT 1997: 178-188
1996
5EEThomas M. Conte, Mary Ann Hirsch, Kishore N. Menezes: Reducing State Loss For Effective Trace Sampling of Superscalar Processors. ICCD 1996: 468-477
4EEThomas M. Conte, Sanjeev Banerjia, Sergei Y. Larin, Kishore N. Menezes, Sumedh W. Sathaye: Instruction Fetch Mechanisms for VLIW Architectures with Compressed Encodings. MICRO 1996: 201-211
3EEThomas M. Conte, Kishore N. Menezes, Mary Ann Hirsch: Accurate and Practical Profile-driven Compilation Using the Profile Buffer. MICRO 1996: 36-45
1995
2EEThomas M. Conte, Kishore N. Menezes, Sumedh W. Sathaye: A technique to determine power-efficient, high-performance superscalar processors. HICSS (1) 1995: 324-333
1EEThomas M. Conte, Kishore N. Menezes, Patrick M. Mills, Burzin A. Patel: Optimization of Instruction Fetch Mechanisms for High Issue Rates. ISCA 1995: 333-344

Coauthor Index

1Sanjeev Banerjia [4] [7] [8]
2Jay Bharadwaj [9] [10] [12]
3William Y. Chen [12]
4Weihaw Chuang [12]
5Thomas M. Conte [1] [2] [3] [4] [5] [6] [7] [8] [11]
6Mary Ann Hirsch [3] [5]
7Gerolf Hoflehner [12]
8Matthew D. Jennings [8]
9Sergei Y. Larin [4]
10Chris McKinsey [9] [10]
11Patrick M. Mills [1]
12Kalyan Muthukumar [12]
13Emre Özer [8]
14Burzin A. Patel [1]
15Jim Pierce [12]
16Sumedh W. Sathaye [2] [4] [6] [7] [8] [11]
17Mark C. Toburen [11]

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)