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Malgorzata Marek-Sadowska Vis

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*2009
181EEAida Todri, Malgorzata Marek-Sadowska, Francois Maire, Christophe Matheron: A study of decoupling capacitor effectiveness in power and ground grid networks. ISQED 2009: 653-658
180EEVishal J. Mehta, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski: Timing-Aware Multiple-Delay-Fault Diagnosis. IEEE Trans. on CAD of Integrated Circuits and Systems 28(2): 245-258 (2009)
179EEYu-Min Kuo, Ya-Ting Chang, Shih-Chieh Chang, Malgorzata Marek-Sadowska: Spare Cells With Constant Insertion for Engineering Change. IEEE Trans. on CAD of Integrated Circuits and Systems 28(3): 456-460 (2009)
2008
178EEHailin Jiang, Malgorzata Marek-Sadowska: Power gating scheduling for power/ground noise reduction. DAC 2008: 980-985
177EEAida Todri, Malgorzata Marek-Sadowska, Joseph N. Kozhaya: Power supply noise aware workload assignment for multi-core systems. ICCAD 2008: 330-337
176EEAida Todri, Malgorzata Marek-Sadowska: A study of reliability issues in clock distribution networks. ICCD 2008: 101-106
175EEShih-Hung Weng, Yu-Min Kuo, Shih-Chieh Chang, Malgorzata Marek-Sadowska: Timing analysis considering IR drop waveforms in power gating designs. ICCD 2008: 532-537
174EEYi-Wei Lin, Malgorzata Marek-Sadowska, Wojciech Maly, Andrzej Pfitzner, Dominik Kasprowicz: Is there always performance overhead for regular fabric? ICCD 2008: 557-562
173EENilesh A. Modi, Malgorzata Marek-Sadowska: ECO-Map: Technology remapping for post-mask ECO using simulated annealing. ICCD 2008: 652-657
172EEVishal J. Mehta, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski: Timing-Aware Multiple-Delay-Fault Diagnosis. ISQED 2008: 246-253
171EEVishal J. Mehta, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski: Improving the Resolution of Single-Delay-Fault Diagnosis. IEEE Trans. on CAD of Integrated Circuits and Systems 27(5): 932-945 (2008)
2007
170EEWojciech Maly, Yi-Wei Lin, Malgorzata Marek-Sadowska: OPC-Free and Minimally Irregular IC Design Style. DAC 2007: 954-957
169EEYu-Shih Su, Da-Chung Wang, Shih-Chieh Chang, Malgorzata Marek-Sadowska: An Efficient Mechanism for Performance Optimization of Variable-Latency Designs. DAC 2007: 976-981
168EEYu-Min Kuo, Ya-Ting Chang, Shih-Chieh Chang, Malgorzata Marek-Sadowska: Engineering change using spare cells with constant insertion. ICCAD 2007: 544-547
167EEAida Todri, Malgorzata Marek-Sadowska, Shih-Chieh Chang: Analysis and optimization of power-gated ICs with multiple power gating configurations. ICCAD 2007: 783-790
166EEAida Todri, Shih-Chieh Chang, Malgorzata Marek-Sadowska: Electromigration and voltage drop aware power grid optimization for power gated ICs. ISLPED 2007: 391-394
165EEHailin Jiang, Malgorzata Marek-Sadowska: Power-Gating Aware Floorplanning. ISQED 2007: 853-860
164EEChao-Yang Yeh, Malgorzata Marek-Sadowska: Timing-Aware Power-Noise Reduction in Placement. IEEE Trans. on CAD of Integrated Circuits and Systems 26(3): 527-541 (2007)
2006
163EEHailin Jiang, Malgorzata Marek-Sadowska: Power/ground supply network optimization for power-gating. ICCD 2006
162EEVishal J. Mehta, Malgorzata Marek-Sadowska, Zhiyuan Wang, Kun-Han Tsai, Janusz Rajski: Delay Fault Diagnosis for Non-Robust Test. ISQED 2006: 463-472
161EEChung-Kuan Tsai, Malgorzata Marek-Sadowska: Analysis of Process Variation's Effect on SRAM's Read Stability. ISQED 2006: 603-610
160EEYajun Ran, Malgorzata Marek-Sadowska: Designing via-configurable logic blocks for regular fabric. IEEE Trans. VLSI Syst. 14(1): 1-14 (2006)
159EEYajun Ran, Malgorzata Marek-Sadowska: Via-Configurable Routing Architectures and Fast Design Mappability Estimation for Regular Fabrics. IEEE Trans. VLSI Syst. 14(9): 998-1009 (2006)
158EEZhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski: Analysis and methodology for multiple-fault diagnosis. IEEE Trans. on CAD of Integrated Circuits and Systems 25(3): 558-575 (2006)
157EEQinghua Liu, Malgorzata Marek-Sadowska: Semi-Individual Wire-Length Prediction With Application to Logic Synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 25(4): 611-624 (2006)
2005
156EEHailin Jiang, Kai Wang, Malgorzata Marek-Sadowska: Clock skew bounds estimation under power supply and process variations. ACM Great Lakes Symposium on VLSI 2005: 332-336
155EEQinghua Liu, Malgorzata Marek-Sadowska: A congestion-driven placement framework with local congestion prediction. ACM Great Lakes Symposium on VLSI 2005: 488-493
154EEChao-Yang Yeh, Malgorzata Marek-Sadowska: Skew-programmable clock design for FPGA and skew-aware placement. FPGA 2005: 33-40
153 Yajun Ran, Malgorzata Marek-Sadowska: Via-configurable routing architectures and fast design mappability estimation for regular fabrics. ICCAD 2005: 25-32
152 Chao-Yang Yeh, Malgorzata Marek-Sadowska: Timing-aware power noise reduction in layout. ICCAD 2005: 627-634
151EEQinghua Liu, Malgorzata Marek-Sadowska: Pre-layout Physical Connectivity Prediction with Application in Clustering-Based Placement. ICCD 2005: 31-37
150EEHailin Jiang, Malgorzata Marek-Sadowska, Sani R. Nassif: Benefits and Costs of Power-Gating Technique. ICCD 2005: 559-566
149EEQinghua Liu, Malgorzata Marek-Sadowska: Wire length prediction-based technology mapping and fanout optimization. ISPD 2005: 145-151
148EEBo Hu, Yue Zeng, Malgorzata Marek-Sadowska: mFAR: fixed-points-addition-based VLSI placement algorithm. ISPD 2005: 239-241
147EEChung-Kuan Tsai, Malgorzata Marek-Sadowska: An Interconnect Insensitive Linear Time-Varying Driver Model for Static Timing Analysis. ISQED 2005: 654-661
146EEKai Wang, Malgorzata Marek-Sadowska: On-chip power-supply network optimization using multigrid-based technique. IEEE Trans. on CAD of Integrated Circuits and Systems 24(3): 407-417 (2005)
145EEQinghua Liu, Malgorzata Marek-Sadowska: A study of netlist structure and placement efficiency. IEEE Trans. on CAD of Integrated Circuits and Systems 24(5): 762-772 (2005)
144EEKai Wang, Yajun Ran, Hailin Jiang, Malgorzata Marek-Sadowska: General skew constrained clock network sizing based on sequential linear programming. IEEE Trans. on CAD of Integrated Circuits and Systems 24(5): 773-782 (2005)
143EEBo Hu, Malgorzata Marek-Sadowska: Multilevel fixed-point-addition-based VLSI placement. IEEE Trans. on CAD of Integrated Circuits and Systems 24(8): 1188-1203 (2005)
142EEZhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski: Delay-fault diagnosis using timing information. IEEE Trans. on CAD of Integrated Circuits and Systems 24(9): 1315-1325 (2005)
141EEYajun Ran, Alex Kondratyev, Kenneth H. Tseng, Yosinori Watanabe, Malgorzata Marek-Sadowska: Eliminating false positives in crosstalk noise analysis. IEEE Trans. on CAD of Integrated Circuits and Systems 24(9): 1406-1419 (2005)
2004
140EEKai Wang, Malgorzata Marek-Sadowska: Buffer sizing for clock power minimization subject to general skew constraints. DAC 2004: 159-164
139EEYajun Ran, Malgorzata Marek-Sadowska: On designing via-configurable cell blocks for regular fabrics. DAC 2004: 198-203
138EEQinghua Liu, Malgorzata Marek-Sadowska: Pre-layout wire length and congestion estimation. DAC 2004: 582-587
137EEYajun Ran, Alex Kondratyev, Yosinori Watanabe, Malgorzata Marek-Sadowska: Eliminating False Positives in Crosstalk Noise Analysis. DATE 2004: 1192-1197
136EEBo Hu, Malgorzata Marek-Sadowska: Multilevel expansion-based VLSI placement with blockages. ICCAD 2004: 558-564
135EEYajun Ran, Malgorzata Marek-Sadowska: An integrated design flow for a via-configurable gate array. ICCAD 2004: 582-589
134EEZhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski: Diagnosis of Hold Time Defects. ICCD 2004: 192-199
133EEKai Wang, Malgorzata Marek-Sadowska: Potential Slack Budgeting with Clock Skew Optimization. ICCD 2004: 265-271
132EEYajun Ran, Malgorzata Marek-Sadowska: The Magic of a Via-Configurable Regular Fabric. ICCD 2004: 338-343
131EEKai Wang, Malgorzata Marek-Sadowska: Clock network sizing via sequential linear programming with time-domain analysis. ISPD 2004: 182-189
130EEQinghua Liu, Malgorzata Marek-Sadowska: A study of netlist structure and placement efficiency. ISPD 2004: 198-203
129EEZhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski: Delay Fault Diagnosis Using Timing Information. ISQED 2004: 485-490
128EELuca Macchiarulo, Shih-Min Shu, Malgorzata Marek-Sadowska: Pipelining Sequential Circuits with Wave Steering. IEEE Trans. Computers 53(9): 1205-1210 (2004)
127EEQinghua Liu, Bo Hu, Malgorzata Marek-Sadowska: Individual wire-length prediction with application to timing-driven placement. IEEE Trans. VLSI Syst. 12(10): 1004-1014 (2004)
126EEChao-Yang Yeh, Malgorzata Marek-Sadowska: Sequential delay budgeting with interconnect prediction. IEEE Trans. VLSI Syst. 12(10): 1028-1037 (2004)
125EEChih-Wei Jim Chang, Ming-Fu Hsiao, Bo Hu, Kai Wang, Malgorzata Marek-Sadowska, Chung-Kuan Cheng, Sao-Jie Chen: Fast postplacement optimization using functional symmetries. IEEE Trans. on CAD of Integrated Circuits and Systems 23(1): 102-118 (2004)
124EEBo Hu, Malgorzata Marek-Sadowska: Fine granularity clustering-based placement. IEEE Trans. on CAD of Integrated Circuits and Systems 23(4): 527-536 (2004)
2003
123EEKai Wang, Malgorzata Marek-Sadowska: On-chip power supply network optimization using multigrid-based technique. DAC 2003: 113-118
122EEChao-Yang Yeh, Malgorzata Marek-Sadowska: Delay budgeting in sequential circuit with application on FPGA placement. DAC 2003: 202-207
121EEBo Hu, Yosinori Watanabe, Alex Kondratyev, Malgorzata Marek-Sadowska: Gain-based technology mapping for discrete-size cell libraries. DAC 2003: 574-579
120EEBo Hu, Malgorzata Marek-Sadowska: Wire length prediction based clustering and its application in placement. DAC 2003: 800-805
119EEDonald Chai, Alex Kondratyev, Yajun Ran, Kenneth H. Tseng, Yosinori Watanabe, Malgorzata Marek-Sadowska: Temporofunctional crosstalk noise analysis. DAC 2003: 860-863
118EEYajun Ran, Malgorzata Marek-Sadowska: Crosstalk noise in FPGAs. DAC 2003: 944-949
117EEKai Wang, Malgorzata Marek-Sadowska: Power/Ground Mesh Area Optimization Using Multigrid-Based Technique. DATE 2003: 10850-10855
116EEChao-Yang Yeh, Malgorzata Marek-Sadowska: Minimum-Area Sequential Budgeting for FPGA. ICCAD 2003: 813-817
115EEZhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski: Multiple Fault Diagnosis Using n-Detection Tests. ICCD 2003: 198-
114EEMing-Fu Hsiao, Malgorzata Marek-Sadowska, Sao-Jie Chen: A crosstalk aware two-pin net router. ISCAS (5) 2003: 485-488
113EEMing-Fu Hsiao, Malgorzata Marek-Sadowska, Sao-Jie Chen: Minimizing coupling jitter by buffer resizing for coupled clock networks. ISCAS (5) 2003: 509-512
112EEBo Hu, Hailin Jiang, Qinghua Liu, Malgorzata Marek-Sadowska: Synthesis and placement flow for gain-based programmable regular fabrics. ISPD 2003: 197-203
111EEBo Hu, Malgorzata Marek-Sadowska: Fine granularity clustering for large scale placement problems. ISPD 2003: 67-74
110EEChung-Kuan Tsai, Malgorzata Marek-Sadowska: Modeling Crosstalk Induced Delay. ISQED 2003: 189-194
109EEMing-Fu Hsiao, Malgorzata Marek-Sadowska, Sao-Jie Chen: Minimizing Inter-Clock Coupling Jitter. ISQED 2003: 333-338
108EEZhiyuan Wang, Kun-Han Tsai, Malgorzata Marek-Sadowska, Janusz Rajski: An Efficient and Effective Methodology on the Multiple Fault Diagnosis. ITC 2003: 329-338
107EEChao-Yang Yeh, Malgorzata Marek-Sadowska: Sequential delay budgeting with interconnect prediction. SLIP 2003: 23-30
106EEQinghua Liu, Bo Hu, Malgorzata Marek-Sadowska: Wire length prediction in constraint driven placement. SLIP 2003: 99-105
105EEArindam Mukherjee, Malgorzata Marek-Sadowska: Clock and Power Gating with Timing Closure. IEEE Design & Test of Computers 20(3): 32-39 (2003)
104EEArindam Mukherjee, Malgorzata Marek-Sadowska: Wave steering to integrate logic and physical syntheses. IEEE Trans. VLSI Syst. 11(1): 105-120 (2003)
103EEAmit Singh, Arindam Mukherjee, Luca Macchiarulo, Malgorzata Marek-Sadowska: PITIA: an FPGA for throughput-intensive applications. IEEE Trans. VLSI Syst. 11(3): 354-363 (2003)
102EELauren Hui Chen, Malgorzata Marek-Sadowska, Forrest Brewer: Buffer delay change in the presence of power and ground noise. IEEE Trans. VLSI Syst. 11(3): 461-473 (2003)
101EEChih-Wei Jim Chang, Ming-Fu Hsiao, Malgorzata Marek-Sadowska: A new reasoning scheme for efficient redundancy addition and removal. IEEE Trans. on CAD of Integrated Circuits and Systems 22(7): 945-951 (2003)
2002
100EELauren Hui Chen, Malgorzata Marek-Sadowska, Forrest Brewer: Coping with buffer delay change due to power and ground noise. DAC 2002: 860-865
99EEArindam Mukherjee, Kai Wang, Lauren Hui Chen, Malgorzata Marek-Sadowska: Sizing Power/Ground Meshes for Clocking and Computing Circuit Components. DATE 2002: 176-185
98EELauren Hui Chen, Malgorzata Marek-Sadowska: Closed-Form Crosstalk Noise Metrics for Physical Design Applications. DATE 2002: 812-819
97EEAmit Singh, Malgorzata Marek-Sadowska: Efficient circuit clustering for area and power reduction in FPGAs. FPGA 2002: 59-66
96EEBo Hu, Malgorzata Marek-Sadowska: Congestion minimization during placement without estimation. ICCAD 2002: 739-745
95EEChih-Wei Jim Chang, Malgorzata Marek-Sadowska: ATPG-based logic synthesis: an overview. ICCAD 2002: 786-789
94EELauren Hui Chen, Malgorzata Marek-Sadowska: Incremental delay change due to crosstalk noise. ISPD 2002: 120-125
93EEBo Hu, Malgorzata Marek-Sadowska: FAR: fixed-points addition & relaxation based placement. ISPD 2002: 161-166
92EELauren Hui Chen, Malgorzata Marek-Sadowska: Efficient Closed-Form Crosstalk Delay Metrics. ISQED 2002: 431-436
91EEAmit Singh, Malgorzata Marek-Sadowska: FPGA interconnect planning. SLIP 2002: 23-30
90EEAmit Singh, Ganapathy Parthasarathy, Malgorzata Marek-Sadowska: Efficient circuit clustering for area and power reduction in FPGAs. ACM Trans. Design Autom. Electr. Syst. 7(4): 643-663 (2002)
2001
89EEChih-Wei Jim Chang, Malgorzata Marek-Sadowska: Who are the alternative wires in your neighborhood? (alternative wires identification without search). ACM Great Lakes Symposium on VLSI 2001: 103-108
88EEAmit Singh, Arindam Mukherjee, Malgorzata Marek-Sadowska: Latency and Latch Count Minimization in Wave Steered Circuits. DAC 2001: 383-388
87EETong Xiao, Malgorzata Marek-Sadowska: Functional Correlation Analysis in Crosstalk Induced Critical Paths Identification. DAC 2001: 653-656
86EEChih-Wei Jim Chang, Kai Wang, Malgorzata Marek-Sadowska: Layout-Driven Hot-Carrier Degradation Minimization Using Logic Restructuring Techniques. DAC 2001: 97-102
85EEChih-Wei Jim Chang, Bo Hu, Malgorzata Marek-Sadowska: In-place delay constrained power optimization using functional symmetries. DATE 2001: 377-382
84EENobuo Funabiki, Amit Singh, Arindam Mukherjee, Malgorzata Marek-Sadowska: A Global Routing Technique for Wave-Steering Design Methodology. DSD 2001: 430-437
83EEAmit Singh, Arindam Mukherjee, Malgorzata Marek-Sadowska: Interconnect pipelining in a throughput-intensive FPGA architecture. FPGA 2001: 153-160
82EEAmit Singh, Ganapathy Parthasarathy, Malgorzata Marek-Sadowska: Interconnect Resource-Aware Placement for Hierarchical FPGAs. ICCAD 2001: 132-136
81EEChih-Wei Jim Chang, Malgorzata Marek-Sadowska: Single-Pass Redundancy Addition and Removal. ICCAD 2001: 606-609
80 Tong Xiao, Malgorzata Marek-Sadowska: Gate Sizing to Eliminate Crosstalk Induced Timing Violation. ICCD 2001: 186-191
79EEGanapathy Parthasarathy, Malgorzata Marek-Sadowska, Arindam Mukherjee, Amit Singh: Interconnect complexity-aware FPGA placement using Rent's rule. SLIP 2001: 115-121
78EELauren Hui Chen, Malgorzata Marek-Sadowska: Aggressor alignment for worst-case crosstalk noise. IEEE Trans. on CAD of Integrated Circuits and Systems 20(5): 612-621 (2001)
2000
77EEChih-Wei Jim Chang, Chung-Kuan Cheng, Peter Suaris, Malgorzata Marek-Sadowska: Fast post-placement rewiring using easily detectable functional symmetries. DAC 2000: 286-289
76EELuca Macchiarulo, Malgorzata Marek-Sadowska: Wave-steering one-hot encoded FSMs. DAC 2000: 357-360
75EELuca Macchiarulo, Shih-Ming Shu, Malgorzata Marek-Sadowska: Wave Steered FSMs. DATE 2000: 270-276
74EEAmit Singh, Luca Macchiarulo, Arindam Mukherjee, Malgorzata Marek-Sadowska: A novel high throughput reconfigurable FPGA architecture. FPGA 2000: 22-29
73EETong Xiao, Malgorzata Marek-Sadowska: Worst Delay Estimation in Crosstalk Aware Static Timing Analysis. ICCD 2000: 115-120
72EELauren Hui Chen, Malgorzata Marek-Sadowska: Aggressor alignment for worst-case coupling noise. ISPD 2000: 48-54
71EETong Xiao, Malgorzata Marek-Sadowska: Efficient Delay Calculation in Presence of Crosstalk. ISQED 2000: 491-498
70EEYu-Liang Wu, Hongbing Fan, Malgorzata Marek-Sadowska, C. K. Wong: OBDD Minimization Based on Two-Level Representation of Boolean Functions. IEEE Trans. Computers 49(12): 1371-1379 (2000)
69EEKun-Han Tsai, Janusz Rajski, Malgorzata Marek-Sadowska: Star test: the theory and its applications. IEEE Trans. on CAD of Integrated Circuits and Systems 19(9): 1052-1064 (2000)
1999
68EETong Xiao, Malgorzata Marek-Sadowska: Crosstalk Reduction by Transistor Sizing. ASP-DAC 1999: 137-140
67EEArindam Mukherjee, Ranganathan Sudhakar, Malgorzata Marek-Sadowska, Stephen I. Long: Wave Steering in YADDs: A Novel Non-Iterative Synthesis and Layout Technique. DAC 1999: 466-471
66EEAmit Singh, Malgorzata Marek-Sadowska: Circuit clustering using graph coloring. ISPD 1999: 164-169
65 Kuo-Hui Tsai, Tompson, Janusz Rajski, Malgorzata Marek-Sadowska: STAR-ATPG: a high speed test pattern generator for large scan designs. ITC 1999: 1021-1030
64EEAshok Vittal, Lauren Hui Chen, Malgorzata Marek-Sadowska, Kai-Ping Wang, Sherry Yang: Modeling Crosstalk in Resistive VLSI Interconnections. VLSI Design 1999: 470-475
63 Douglas Chang, Malgorzata Marek-Sadowska: Partitioning Sequential Circuits on Dynamically Reconfigurable FPGAs. IEEE Trans. Computers 48(6): 565-578 (1999)
62 Shih-Chieh Chang, Lukas P. P. P. van Ginneken, Malgorzata Marek-Sadowska: Circuit Optimization by Rewiring. IEEE Trans. Computers 48(9): 962-970 (1999)
61EEAshok Vittal, Lauren Hui Chen, Malgorzata Marek-Sadowska, Kai-Ping Wang, Sherry Yang: Crosstalk in VLSI interconnections. IEEE Trans. on CAD of Integrated Circuits and Systems 18(12): 1817-1824 (1999)
60EEChih-Chang Lin, Kuang-Chien Chen, Malgorzata Marek-Sadowska: Logic synthesis for engineering change. IEEE Trans. on CAD of Integrated Circuits and Systems 18(3): 282-292 (1999)
1998
59EEDouglas Chang, Kwang-Ting Cheng, Malgorzata Marek-Sadowska, Mike Tien-Chien Lee: Functional Scan Chain Testing. DATE 1998: 278-
58EEDouglas Chang, Malgorzata Marek-Sadowska: Partitioning Sequential Circuits on Dynamically Reconfiguable FPGAs. FPGA 1998: 161-167
57EEDavid Ihsin Cheng, Kwang-Ting Cheng, Deborah C. Wang, Malgorzata Marek-Sadowska: A hybrid methodology for switching activities estimation. IEEE Trans. on CAD of Integrated Circuits and Systems 17(4): 357-366 (1998)
56EEChih-Chang Lin, Malgorzata Marek-Sadowska, Kwang-Ting Cheng, Mike Tien-Chien Lee: Test-point insertion: scan paths through functional logic. IEEE Trans. on CAD of Integrated Circuits and Systems 17(9): 838-851 (1998)
55EEChih-Chang Lin, Malgorzata Marek-Sadowska, Mike Tien-Chien Lee, Kuang-Chien Chen: Cost-free scan: a low-overhead scan path design. IEEE Trans. on CAD of Integrated Circuits and Systems 17(9): 852-861 (1998)
1997
54EEDouglas Chang, Mike Tien-Chien Lee, Malgorzata Marek-Sadowska, Takashi Aikyo, Kwang-Ting Cheng: A Test Synthesis Approach to Reducing BALLAST DFT Overhead. DAC 1997: 466-471
53EEKun-Han Tsai, Sybille Hellebrand, Janusz Rajski, Malgorzata Marek-Sadowska: STARBIST: Scan Autocorrelated Random Pattern Generation. DAC 1997: 472-477
52EEYi-Min Jiang, Angela Krstic, Kwang-Ting Cheng, Malgorzata Marek-Sadowska: Post-Layout Logic Restructuring for Performance Optimization. DAC 1997: 662-665
51EEDouglas Chang, Malgorzata Marek-Sadowska: Buffer Minimization and Time-Multiplexed I/O on Dynamically Reconfigurable FPGAs. FPGA 1997: 142-148
50EEMarek A. Perkowski, Malgorzata Marek-Sadowska, Lech Józwiak, Tadeusz Luba, Stan Grygiel, Miroslawa Nowicka, Rahul Malvi, Zhi Wang, Jin S. Zhang: Decomposition of Multiple-Valued Relations . ISMVL 1997: 13-18
49EEStan Grygiel, Marek A. Perkowski, Malgorzata Marek-Sadowska, Tadeusz Luba, Lech Józwiak: Cube Diagram Bundles: A New Representation of Strongly Unspecified Multiple-Valued Functions and Relations. ISMVL 1997: 287-292
48 Kun-Han Tsai, Malgorzata Marek-Sadowska, Janusz Rajski: Scan-Encoded Test Pattern Generation for BIST. ITC 1997: 548-556
47 Chien-Chung Tsai, Malgorzata Marek-Sadowska: Boolean Functions Classification via Fixed Polarity Reed-Muller Forms. IEEE Trans. Computers 46(2): 173-186 (1997)
46EEAshok Vittal, Malgorzata Marek-Sadowska: Crosstalk reduction for VLSI. IEEE Trans. on CAD of Integrated Circuits and Systems 16(3): 290-298 (1997)
45EEYu-Liang Wu, Malgorzata Marek-Sadowska: Routing for array-type FPGA's. IEEE Trans. on CAD of Integrated Circuits and Systems 16(5): 506-518 (1997)
44EEChih-Chang Lin, Malgorzata Marek-Sadowska: On designing universal logic blocks and their application to FPGA design. IEEE Trans. on CAD of Integrated Circuits and Systems 16(5): 519-527 (1997)
43EEShih-Chieh Chang, Kwang-Ting Cheng, Nam Sung Woo, Malgorzata Marek-Sadowska: Postlayout logic restructuring using alternative wires. IEEE Trans. on CAD of Integrated Circuits and Systems 16(6): 587-596 (1997)
42EEAshok Vittal, Malgorzata Marek-Sadowska: Low-power buffered clock tree design. IEEE Trans. on CAD of Integrated Circuits and Systems 16(9): 965-975 (1997)
1996
41EEChien-Chung Tsai, Malgorzata Marek-Sadowska: Multilevel Logic Synthesis for Arithmetic Functions. DAC 1996: 242-247
40EEChih-Chang Lin, Malgorzata Marek-Sadowska, Kwang-Ting Cheng, Mike Tien-Chien Lee: Test Point Insertion: Scan Paths through Combinational Logic. DAC 1996: 268-273
39EEDavid Ihsin Cheng, Kwang-Ting Cheng, Deborah C. Wang, Malgorzata Marek-Sadowska: A New Hybrid Methodology for Power Estimation. DAC 1996: 439-444
38EEChien-Chung Tsai, Malgorzata Marek-Sadowska: Logic Synthesis for Testability. Great Lakes Symposium on VLSI 1996: 118-121
37EEShih-Chieh Chang, Lukas P. P. P. van Ginneken, Malgorzata Marek-Sadowska: Fast Boolean optimization by rewiring. ICCAD 1996: 262-269
36EEAshok Vittal, Hein Ha, Forrest Brewer, Malgorzata Marek-Sadowska: Clock skew optimization for ground bounce control. ICCAD 1996: 395-399
35 Chien-Chung Tsai, Malgorzata Marek-Sadowska: Generalized Reed-Muller Forms as a Tool to Detect Symmetries. IEEE Trans. Computers 45(1): 33-40 (1996)
34EEYu-Liang Wu, Shuji Tsukiyama, Malgorzata Marek-Sadowska: Graph based analysis of 2-D FPGA routing. IEEE Trans. on CAD of Integrated Circuits and Systems 15(1): 33-44 (1996)
33EEShih-Chieh Chang, Malgorzata Marek-Sadowska, TingTing Hwang: Technology mapping for TLU FPGAs based on decomposition of binary decision diagrams. IEEE Trans. on CAD of Integrated Circuits and Systems 15(10): 1226-1236 (1996)
32EEShih-Chieh Chang, Malgorzata Marek-Sadowska, Kwang-Ting Cheng: Perturb and simplify: multilevel Boolean network optimizer. IEEE Trans. on CAD of Integrated Circuits and Systems 15(12): 1494-1504 (1996)
1995
31EEChih-Chang Lin, David Ihsin Cheng, Malgorzata Marek-Sadowska, Kuang-Chien Chen: Logic rectification and synthesis for engineering change. ASP-DAC 1995
30EEYu-Liang Wu, Malgorzata Marek-Sadowska: Routing on regular segmented 2-D FPGAs. ASP-DAC 1995
29EEAshok Vittal, Malgorzata Marek-Sadowska: Power Optimal Buffered Clock Tree Design. DAC 1995: 497-502
28EEAshok Vittal, Malgorzata Marek-Sadowska: Power Distribution Topology Design. DAC 1995: 503-507
27EEYu-Liang Wu, Malgorzata Marek-Sadowska: Orthogonal Greedy Coupling - A New Optimization Approach to 2-D FPGA Routing. DAC 1995: 568-573
26EEChih-Chang Lin, Kuang-Chien Chen, Shih-Chieh Chang, Malgorzata Marek-Sadowska, Kwang-Ting Cheng: Logic Synthesis for Engineering Change. DAC 1995: 647-652
25EEShih-Chieh Chang, Malgorzata Marek-Sadowska, Kwang-Ting Cheng: An Efficient Algorithm for Local Don't Care Sets Calculation. DAC 1995: 663-667
24EEChih-Chang Lin, Mike Tien-Chien Lee, Malgorzata Marek-Sadowska, Kuang-Chien Chen: Cost-free scan: a low-overhead scan path design methodology. ICCAD 1995: 528-533
23EEDavid Ihsin Cheng, Chih-Chang Lin, Malgorzata Marek-Sadowska: Circuit partitioning with logic perturbation. ICCAD 1995: 650-655
22EEMalgorzata Marek-Sadowska, Majid Sarrafzadeh: The crossing distribution problem [IC layout]. IEEE Trans. on CAD of Integrated Circuits and Systems 14(4): 423-433 (1995)
1994
21EEShih-Chieh Chang, Kwang-Ting Cheng, Nam Sung Woo, Malgorzata Marek-Sadowska: Layout Driven Logic Synthesis for FPGAs. DAC 1994: 308-313
20EEChien-Chung Tsai, Malgorzata Marek-Sadowska: Boolean Matching Using Generalized Reed-Muller Forms. DAC 1994: 339-344
19EEAshok Vittal, Malgorzata Marek-Sadowska: Minimal Delay Interconnect Design Using Alphabetic Trees. DAC 1994: 392-396
18 Yu-Liang Wu, Malgorzata Marek-Sadowska: An Efficient Router for 2-D Field Programmable Gate Arrays. EDAC-ETC-EUROASIC 1994: 412-416
17 Shih-Chieh Chang, David Ihsin Cheng, Malgorzata Marek-Sadowska: Minimizing ROBDD Size of Incompletely Specified Multiple Output Functions. EDAC-ETC-EUROASIC 1994: 620-624
16EEChih-Chang Lin, Malgorzata Marek-Sadowska, Duane Gatlin: Universal logic gate for FPGA design. ICCAD 1994: 164-168
15EEShih-Chieh Chang, Malgorzata Marek-Sadowska: Perturb and simplify: multi-level boolean network optimizer. ICCAD 1994: 2-5
14 Chien-Chung Tsai, Malgorzata Marek-Sadowska: Detecting Symmetric Variables in Boolean Functions using Generalized Reel-Muller Forms. ISCAS 1994: 287-290
1993
13EEShen Lin, Ernest S. Kuh, Malgorzata Marek-Sadowska: Stepwise equivalent conductance circuit simulation technique. IEEE Trans. on CAD of Integrated Circuits and Systems 12(5): 672-683 (1993)
1992
12 Shih-Chieh Chang, Malgorzata Marek-Sadowska: Technology Mapping via Transformations of Function Graphs. ICCD 1992: 159-162
1991
11 Malgorzata Marek-Sadowska, Majid Sarrafzadeh: The Crossing Distribution Problem. ICCAD 1991: 528-531
1990
10EEShen Lin, Malgorzata Marek-Sadowska, Ernest S. Kuh: Delay and Area Optimization in Standard-Cell Design. DAC 1990: 349-352
9 Massoud Pedram, Malgorzata Marek-Sadowska, Ernest S. Kuh: Floorplanning with Pin Assignment. ICCAD 1990: 98-101
1989
8EERajiv Dutta, Malgorzata Marek-Sadowska: Automatic Sizing of Power/Ground (P/G) Networks in VLSI. DAC 1989: 783-786
7EEFillia Makedon, Malgorzata Marek-Sadowska: Analysis of Heuristic Reasoning for the Visualization of CAD Quadratic. ICCAL 1989: 359-378
1987
6EEMalgorzata Marek-Sadowska: Pad Assignment for Power Nets in VLSI Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 6(4): 550-560 (1987)
1985
5EEMalgorzata Marek-Sadowska: Two-dimensional router for double layer layout. DAC 1985: 117-123
1984
4EETom Tsan-Kuo Tarng, Malgorzata Marek-Sadowska, Ernest S. Kuh: An Efficient Single-Row Routing Algorithm. IEEE Trans. on CAD of Integrated Circuits and Systems 3(3): 178-183 (1984)
3EEMalgorzata Marek-Sadowska: An Unconstrained Topological Via Minimization Problem for Two-Layer Routing. IEEE Trans. on CAD of Integrated Circuits and Systems 3(3): 184-190 (1984)
2EEJeong-Tyng Li, Malgorzata Marek-Sadowska: Global Routing for Gate Array. IEEE Trans. on CAD of Integrated Circuits and Systems 3(4): 298-307 (1984)
1983
1EEMalgorzata Marek-Sadowska, Tom Tsan-Kuo Tarng: Single-Layer Routing for VLSI: Analysis and Algorithms. IEEE Trans. on CAD of Integrated Circuits and Systems 2(4): 246-259 (1983)

Coauthor Index

1Takashi Aikyo [54]
2Forrest Brewer [36] [100] [102]
3Donald Chai [119]
4Chih-Wei Jim Chang [77] [81] [85] [86] [89] [95] [101] [125]
5Douglas Chang [51] [54] [58] [59] [63]
6Shih-Chieh Chang [12] [15] [17] [21] [25] [26] [32] [33] [37] [43] [62] [166] [167] [168] [169] [175] [179]
7Ya-Ting Chang [168] [179]
8Kuang-Chien Chen [24] [26] [31] [55] [60]
9Lauren Hui Chen [61] [64] [72] [78] [92] [94] [98] [99] [100] [102]
10Sao-Jie Chen [109] [113] [114] [125]
11Chung-Kuan Cheng [77] [125]
12David Ihsin Cheng [17] [23] [31] [39] [57]
13Kwang-Ting Cheng (Kwang-Ting (Tim) Cheng) [21] [25] [26] [32] [39] [40] [43] [52] [54] [56] [57] [59]
14Rajiv Dutta [8]
15Hongbing Fan [70]
16Nobuo Funabiki [84]
17Duane Gatlin [16]
18Lukas P. P. P. van Ginneken [37] [62]
19Stan Grygiel [49] [50]
20Hein Ha [36]
21Sybille Hellebrand [53]
22Ming-Fu Hsiao [101] [109] [113] [114] [125]
23Bo Hu [85] [93] [96] [106] [111] [112] [120] [121] [124] [125] [127] [136] [143] [148]
24TingTing Hwang [33]
25Hailin Jiang [112] [144] [150] [156] [163] [165] [178]
26Yi-Min Jiang [52]
27Lech Józwiak [49] [50]
28Dominik Kasprowicz [174]
29Alex Kondratyev [119] [121] [137] [141]
30Joseph N. Kozhaya [177]
31Angela Krstic [52]
32Ernest S. Kuh [4] [9] [10] [13]
33Yu-Min Kuo [168] [175] [179]
34Mike Tien-Chien Lee [24] [40] [54] [55] [56] [59]
35Jeong-Tyng Li [2]
36Chih-Chang Lin [16] [23] [24] [26] [31] [40] [44] [55] [56] [60]
37Shen Lin [10] [13]
38Yi-Wei Lin [170] [174]
39Qinghua Liu [106] [112] [127] [130] [138] [145] [149] [151] [155] [157]
40Stephen I. Long [67]
41Tadeusz Luba [49] [50]
42Luca Macchiarulo [74] [75] [76] [103] [128]
43Francois Maire [181]
44Fillia Makedon [7]
45Rahul Malvi [50]
46Wojciech Maly [170] [174]
47Christophe Matheron [181]
48Vishal J. Mehta [162] [171] [172] [180]
49Nilesh A. Modi [173]
50Arindam Mukherjee [67] [74] [79] [83] [84] [88] [99] [103] [104] [105]
51Sani R. Nassif [150]
52Miroslawa Nowicka [50]
53Ganapathy Parthasarathy [79] [82] [90]
54Massoud Pedram [9]
55Marek A. Perkowski [49] [50]
56Andrzej Pfitzner [174]
57Janusz Rajski [48] [53] [65] [69] [108] [115] [129] [134] [142] [158] [162] [171] [172] [180]
58Yajun Ran [118] [119] [132] [135] [137] [139] [141] [144] [153] [159] [160]
59Majid Sarrafzadeh [11] [22]
60Shih-Min Shu [128]
61Shih-Ming Shu [75]
62Amit Singh [66] [74] [79] [82] [83] [84] [88] [90] [91] [97] [103]
63Yu-Shih Su [169]
64Peter Suaris (Peter Ramyalal Suaris) [77]
65Ranganathan Sudhakar [67]
66Tom Tsan-Kuo Tarng [1] [4]
67Aida Todri [166] [167] [176] [177] [181]
68 Tompson [65]
69Chien-Chung Tsai [14] [20] [35] [38] [41] [47]
70Chung-Kuan Tsai [110] [147] [161]
71Kun-Han Tsai [48] [53] [69] [108] [115] [129] [134] [142] [158] [162] [171] [172] [180]
72Kuo-Hui Tsai [65]
73Kenneth H. Tseng [119] [141]
74Shuji Tsukiyama [34]
75Ashok Vittal [19] [28] [29] [36] [42] [46] [61] [64]
76Da-Chung Wang [169]
77Deborah C. Wang [39] [57]
78Kai Wang [86] [99] [117] [123] [125] [131] [133] [140] [144] [146] [156]
79Kai-Ping Wang [61] [64]
80Zhi Wang [50]
81Zhiyuan Wang [108] [115] [129] [134] [142] [158] [162]
82Yosinori Watanabe [119] [121] [137] [141]
83Shih-Hung Weng [175]
84Chak-Kuen Wong (C. K. Wong) [70]
85Nam Sung Woo [21] [43]
86Yu-Liang Wu (David Yu-Liang Wu) [18] [27] [30] [34] [45] [70]
87Tong Xiao [68] [71] [73] [80] [87]
88Sherry Yang [61] [64]
89Chao-Yang Yeh [107] [116] [122] [126] [152] [154] [164]
90Yue Zeng [148]
91Jin S. Zhang [50]

Colors in the list of coauthors

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)