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Srilatha Manne Vis

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*2008
14EERavi Bhargava, Ben Serebrin, Francesco Spadini, Srilatha Manne: Accelerating two-dimensional page walks for virtualized systems. ASPLOS 2008: 26-35
2007
13EEPaul Racunas, Kypros Constantinides, Srilatha Manne, Shubhendu S. Mukherjee: Perturbation-based Fault Screening. HPCA 2007: 169-180
2002
12EEEric Borch, Eric Tune, Srilatha Manne, Joel S. Emer: Loose Loops Sink Chips. HPCA 2002: 299-310
11EEJoel S. Emer, Pritpal Ahuja, Eric Borch, Artur Klauser, Chi-Keung Luk, Srilatha Manne, Shubhendu S. Mukherjee, Harish Patil, Steven Wallace, Nathan L. Binkert, Roger Espasa, Toni Juan: Asim: A Performance Model Framework. IEEE Computer 35(2): 68-76 (2002)
2001
10EER. Iris Bahar, Srilatha Manne: Power and energy reduction via pipeline balancing. ISCA 2001: 218-229
9 Artur Klauser, Srilatha Manne, Dirk Grunwald: Selective Branch Inversion: Confidence Estimation for Branch Predictors. International Journal of Parallel Programming 29(1): 81-110 (2001)
1999
8EESrilatha Manne, Artur Klauser, Dirk Grunwald: Branch Prediction Using Selective Branch Inversion. IEEE PACT 1999: 48-56
1998
7EEDirk Grunwald, Artur Klauser, Srilatha Manne, Andrew R. Pleszkun: Confidence Estimation for Speculation Control. ISCA 1998: 122-131
6EESrilatha Manne, Artur Klauser, Dirk Grunwald: Pipeline Gating: Speculation Control for Energy Reduction. ISCA 1998: 132-141
5EER. Iris Bahar, Gianluca Albera, Srilatha Manne: Power and performance tradeoffs using various caching strategies. ISLPED 1998: 64-69
1997
4EESrilatha Manne, Dirk Grunwald, Fabio Somenzi: Remembrance of Things Past: Locality and Memory in BDDs. DAC 1997: 196-201
1996
3EEOlivier Coudert, Ramsey W. Haddad, Srilatha Manne: New Algorithms for Gate Sizing: A Comparative Study. DAC 1996: 734-739
1995
2EESrilatha Manne, Abelardo Pardo, R. Iris Bahar, Gary D. Hachtel, Fabio Somenzi, Enrico Macii, Massimo Poncino: Computing the Maximum Power Cycles of a Sequential Circuit. DAC 1995: 23-28
1EEAbelardo Pardo, R. Iris Bahar, Srilatha Manne, Peter Feldmann, Gary D. Hachtel, Fabio Somenzi: CMOS dynamic power estimation based on collapsible current source transistor modeling. ISLPD 1995: 111-116

Coauthor Index

1Pritpal Ahuja [11]
2Gianluca Albera [5]
3R. Iris Bahar [1] [2] [5] [10]
4Ravi Bhargava [14]
5Nathan L. Binkert [11]
6Eric Borch [11] [12]
7Kypros Constantinides [13]
8Olivier Coudert [3]
9Joel S. Emer [11] [12]
10Roger Espasa [11]
11Peter Feldmann [1]
12Dirk Grunwald [4] [6] [7] [8] [9]
13Gary D. Hachtel [1] [2]
14Ramsey W. Haddad [3]
15Toni Juan [11]
16Artur Klauser [6] [7] [8] [9] [11]
17Chi-Keung Luk [11]
18Enrico Macii [2]
19Shubhendu S. Mukherjee [11] [13]
20Abelardo Pardo [1] [2]
21Harish Patil [11]
22Andrew R. Pleszkun [7]
23Massimo Poncino [2]
24Paul Racunas [13]
25Ben Serebrin [14]
26Fabio Somenzi [1] [2] [4]
27Francesco Spadini [14]
28Eric Tune [12]
29Steven Wallace [11]

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Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)