| * | 2009 |
|---|
| 8 | EE | Sungmin Bae,
Prasanth Mangalagiri,
Narayanan Vijaykrishnan:
Exploiting clock skew scheduling for FPGA.
DATE 2009: 1524-1529 |
| 2008 |
|---|
| 7 | EE | Prasanth Mangalagiri,
Karthik Sarpatwari,
Aditya Yanamandra,
Vijaykrishnan Narayanan,
Yuan Xie,
Mary Jane Irwin,
Osama Awadel Karim:
A low-power phase change memory based hybrid cache architecture.
ACM Great Lakes Symposium on VLSI 2008: 395-398 |
| 6 | EE | Prasanth Mangalagiri,
Sungmin Bae,
Krishnan Ramakrishnan,
Yuan Xie,
Vijaykrishnan Narayanan:
Thermal-aware reliability analysis for platform FPGAs.
ICCAD 2008: 722-727 |
| 5 | EE | Suresh Srinivasan,
Krishnan Ramakrishnan,
Prasanth Mangalagiri,
Yuan Xie,
Vijaykrishnan Narayanan,
Mary Jane Irwin,
Karthik Sarpatwari:
Toward Increasing FPGA Lifetime.
IEEE Trans. Dependable Sec. Comput. 5(2): 115-127 (2008) |
| 2007 |
|---|
| 4 | EE | Jungsub Kim,
Prasanth Mangalagiri,
Kevin M. Irick,
Mahmut T. Kandemir,
Vijay Narayanan,
K. Sobti,
Lanping Deng,
Chaitali Chakrabarti,
Nikos Pitsianis,
Xiaobai Sun:
TANOR: A Tool for Accelerating N-Body Simulations on Reconfigurable Platforms.
FPL 2007: 68-73 |
| 3 | EE | Suresh Srinivasan,
Prasanth Mangalagiri,
Yuan Xie,
Narayanan Vijaykrishnan:
FPGA routing architecture analysis under variations.
ICCD 2007: 152-157 |
| 2 | EE | K. Sobti,
Lanping Deng,
Chaitali Chakrabarti,
Nikos Pitsianis,
Xiaobai Sun,
Jungsub Kim,
Prasanth Mangalagiri,
Kevin M. Irick,
Mahmut T. Kandemir,
Vijay Narayanan:
Efficient Function Evaluations with Lookup Tables for Structured Matrix Operations.
SiPS 2007: 463-468 |
| 2006 |
|---|
| 1 | EE | Suresh Srinivasan,
Prasanth Mangalagiri,
Yuan Xie,
Narayanan Vijaykrishnan,
Karthik Sarpatwari:
FLAW: FPGA lifetime awareness.
DAC 2006: 630-635 |
