| 2006 |
|---|
| 63 | EE | Jeffrey E. Nelson,
Thomas Zanon,
Rao Desineni,
Jason G. Brown,
N. Patil,
Wojciech Maly,
R. D. (Shawn) Blanton:
Extraction of defect density and size distributions from wafer sort test results.
DATE 2006: 913-918 |
| 62 | EE | Jeffrey E. Nelson,
Thomas Zanon,
Jason G. Brown,
Osei Poku,
R. D. (Shawn) Blanton,
Wojciech Maly,
Brady Benware,
Chris Schuermyer:
Extracting Defect Density and Size Distributions from Product ICs.
IEEE Design & Test of Computers 23(5): 390-400 (2006) |
| 2004 |
|---|
| 61 | EE | Yangdong (Steven) Deng,
Wojciech Maly:
2.5D system integration: a design driven system implementation schema.
ASP-DAC 2004: 450-455 |
| 60 | EE | Thomas J. Vogels,
Thomas Zanon,
Rao Desineni,
R. D. (Shawn) Blanton,
Wojciech Maly,
Jason G. Brown,
Jeffrey E. Nelson,
Y. Fei,
X. Huang,
Padmini Gopalakrishnan,
Mahim Mishra,
V. Rovner,
S. Tiwary:
Benchmarking Diagnosis Algorithms With a Diverse Set of IC Deformations.
ITC 2004: 508-517 |
| 2003 |
|---|
| 59 | EE | Yangdong Deng,
Wojciech Maly:
Physical Design of the "2.5D" Stacked System.
ICCD 2003: 211-217 |
| 58 | EE | Thomas J. Vogels,
Wojciech Maly,
R. D. (Shawn) Blanton:
Progressive Bridge Identification.
ITC 2003: 309-318 |
| 57 | EE | Wojciech Maly,
Anne E. Gattiker,
Thomas Zanon,
Thomas J. Vogels,
R. D. (Shawn) Blanton,
Thomas M. Storey:
Deformations of IC Structure in Test and Yield Learning.
ITC 2003: 856-865 |
| 2002 |
|---|
| 56 | EE | Ronald D. Blanton,
John T. Chen,
Rao Desineni,
Kumar N. Dwarakanath,
Wojciech Maly,
Thomas J. Vogels:
Fault Tuples in Diagnosis of Deep-Submicron Circuits.
ITC 2002: 233-241 |
| 55 | EE | Pranab K. Nag,
Anne E. Gattiker,
Sichao Wei,
Ronald D. Blanton,
Wojciech Maly:
Modeling the Economics of Testing: A DFT Perspective.
IEEE Design & Test of Computers 19(1): 29-41 (2002) |
| 2001 |
|---|
| 54 | EE | Wojciech Maly:
IC Design in High-Cost Nanometer-Technologies Era.
DAC 2001: 9-14 |
| 53 | EE | Yangdong Deng,
Wojciech Maly:
Interconnect characteristics of 2.5-D system integration scheme.
ISPD 2001: 171-175 |
| 52 | EE | Wojciech Maly:
Quality of Design from an IC Manufacturing Perspective.
ISQED 2001: 235-236 |
| 51 | | John T. Chen,
Jitendra Khare,
Ken Walker,
Saghir A. Shaikh,
Janusz Rajski,
Wojciech Maly:
Test response compression and bitmap encoding for embedded memories in manufacturing process monitoring.
ITC 2001: 258-267 |
| 50 | EE | John T. Chen,
Wojciech Maly,
Janusz Rajski,
Omar Kebichi,
Jitendra Khare:
Enabling Embedded Memory Diagnosis via Test Response Compression.
VTS 2001: 292-298 |
| 2000 |
|---|
| 49 | EE | Peng Li,
Pranab K. Nag,
Wojciech Maly:
Cost based tradeoff analysis of standard cell designs.
SLIP 2000: 129-135 |
| 1999 |
|---|
| 48 | EE | Witold A. Pleskacz,
Charles H. Ouyang,
Wojciech Maly:
A DRC-based algorithm for extraction of critical areas for opens in large VLSI circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(2): 151-162 (1999) |
| 47 | EE | Mariusz Niewczas,
Wojciech Maly,
Andrzej J. Strojwas:
An algorithm for determining repetitive patterns in very large IC layouts.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(4): 494-501 (1999) |
| 1998 |
|---|
| 46 | EE | Wojciech Maly,
Pranab K. Nag,
Hans T. Heineken,
Jitendra Khare:
Design-Manufacturing Interface: Part I - Vision.
DATE 1998: 550-556 |
| 45 | EE | Wojciech Maly,
Pranab K. Nag,
Charles H. Ouyang,
Hans T. Heineken,
Jitendra Khare,
P. Simon:
Design-Manufacturing Interface: Part II - Applications.
DATE 1998: 557-562 |
| 44 | EE | Hans T. Heineken,
Wojciech Maly:
Performance - Manufacturability Tradeoffs in IC Design.
DATE 1998: 563- |
| 43 | EE | Mariusz Niewczas,
Wojciech Maly,
Andrzej J. Strojwas:
A pattern matching algorithm for verification and analysis of very large IC layouts.
ISPD 1998: 129-134 |
| 42 | EE | Wojciech Maly:
Moore's law and physical design of ICs.
ISPD 1998: 36 |
| 41 | EE | Anne E. Gattiker,
Wojciech Maly:
Toward understanding "Iddq-only" fails.
ITC 1998: 174-183 |
| 1997 |
|---|
| 40 | EE | Hans T. Heineken,
Jitendra Khare,
Wojciech Maly,
Pranab K. Nag,
Charles H. Ouyang,
Witold A. Pleskacz:
CAD at the Design-Manufacturing Interface.
DAC 1997: 321-326 |
| 39 | EE | Witold A. Pleskacz,
Wojciech Maly:
Improved Yield Model for Submicron Domain.
DFT 1997: 2-10 |
| 38 | EE | Witold A. Pleskacz,
Wojciech Maly,
Hans T. Heineken:
Detection of Yield Trends.
DFT 1997: 62-68 |
| 37 | | Phil Nigh,
Wayne M. Needham,
Kenneth M. Butler,
Peter C. Maxwell,
Robert C. Aitken,
Wojciech Maly:
So What Is an Optimal Test Mix? A Discussion of the SEMATECH Methods Experiment.
ITC 1997: 1037-1038 |
| 36 | EE | Anne E. Gattiker,
Wojciech Maly:
Current signatures: application [to CMOS].
ITC 1997: 1168-1177 |
| 35 | | Anne E. Gattiker,
Wojciech Maly:
Current Signatures: Application.
ITC 1997: 156-165 |
| 34 | | Sichao Wei,
Pranab K. Nag,
Ronald D. Blanton,
Anne E. Gattiker,
Wojciech Maly:
To DFT or Not to DFT?
ITC 1997: 557-566 |
| 33 | EE | Aiman H. El-Maleh,
Thomas E. Marchok,
Janusz Rajski,
Wojciech Maly:
Behavior and testability preservation under the retiming transformation.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(5): 528-543 (1997) |
| 1996 |
|---|
| 32 | EE | Hans T. Heineken,
Wojciech Maly:
Interconnect yield model for manufacturability prediction in synthesis of standard cell based designs.
ICCAD 1996: 368-373 |
| 31 | EE | Wojciech Maly,
Hans T. Heineken,
Jitendra Khare,
Pranab K. Nag:
Design for manufacturability in submicron domain.
ICCAD 1996: 690-697 |
| 30 | EE | Thomas E. Marchok,
Wojciech Maly:
Modeling the Difficulty of Sequential Automatic Test Pattern Generation.
ICCD 1996: 261- |
| 29 | | Wojciech Maly:
New and Not-So-New Test Challenges of the Next Decade.
ITC 1996: 11 |
| 28 | | Thomas W. Williams,
R. H. Dennard,
Rohit Kapur,
M. Ray Mercer,
Wojciech Maly:
IDDQ Test: Sensitivity Analysis of Scaling.
ITC 1996: 786-792 |
| 27 | EE | Anne E. Gattiker,
Wojciech Maly:
Current signatures [VLSI circuit testing].
VTS 1996: 112-117 |
| 26 | EE | Jitendra Khare,
Wojciech Maly,
Nathan Tiday:
Fault characterization of standard cell libraries using inductive contamination.
VTS 1996: 405-413 |
| 25 | EE | Wojciech Maly:
The future of IC design, testing, and manufacturing.
IEEE Design & Test of Computers 13(4): 8, 89-91 (1996) |
| 24 | EE | Thomas E. Marchok,
Aiman H. El-Maleh,
Wojciech Maly,
Janusz Rajski:
A complexity analysis of sequential ATPG.
IEEE Trans. on CAD of Integrated Circuits and Systems 15(11): 1409-1423 (1996) |
| 1995 |
|---|
| 23 | EE | Aiman H. El-Maleh,
Thomas E. Marchok,
Janusz Rajski,
Wojciech Maly:
On Test Set Preservation of Retimed Circuits.
DAC 1995: 176-182 |
| 22 | | Jitendra Khare,
Wojciech Maly:
Inductive Contamination Analysis (ICA) with SRAM Application.
ITC 1995: 552-560 |
| 21 | EE | Thomas E. Marchok,
Aiman H. El-Maleh,
Janusz Rajski,
Wojciech Maly:
Testability Implications of Performance-Driven Logic Synthesis.
IEEE Design & Test of Computers 12(2): 32-39 (1995) |
| 1994 |
|---|
| 20 | EE | Wojciech Maly:
Cost of Silicon Viewed from VLSI Design Perspective.
DAC 1994: 135-142 |
| 19 | | Wojciech Maly:
Integration of Design, Manufacturing and Testing.
ITC 1994: 1017 |
| 18 | | Anne E. Gattiker,
Wojciech Maly:
Feasibility Study of Smart Substrate Multichip Modules.
ITC 1994: 41-49 |
| 17 | EE | Wojciech Maly,
Derek Feltham,
Anne E. Gattiker,
Mark D. Hobaugh,
Kenneth Backus,
Michael E. Thomas:
Smart-Substrate Multichip-Module Systems.
IEEE Design & Test of Computers 11(2): 64-73 (1994) |
| 1993 |
|---|
| 16 | EE | Samir Naik,
Frank Agricola,
Wojciech Maly:
Failure Analysis of High-Density CMOS SRAMs: Using Realistic Defect Modeling and I/Sub DDQ/ Testing.
IEEE Design & Test of Computers 10(2): 13-23 (1993) |
| 1992 |
|---|
| 15 | | Wojciech Maly:
Prospects for WSI: A Manufacturing Perspective.
IEEE Computer 25(4): 58-65 (1992) |
| 1991 |
|---|
| 14 | | Wojciech Maly:
What is Design for Manufacturability (DFM)? (Panel Abstract).
DAC 1991: 252 |
| 13 | | Wojciech Maly:
Improving the Quality of Test Education.
ITC 1991: 1119 |
| 12 | | Thomas M. Storey,
Wojciech Maly,
John Andrews,
Myron Miske:
Stuck Fault and Current Testing Comparison Using CMOS Chip Test.
ITC 1991: 311-318 |
| 11 | | Anne Meixner,
Wojciech Maly:
Fault Modeling for the Testing of Mixed Integrated Circuits.
ITC 1991: 564-572 |
| 1990 |
|---|
| 10 | | Thomas M. Storey,
Wojciech Maly:
CMOS Bridging Fault Detection.
ITC 1990: 1123-1132 |
| 9 | EE | Phil Nigh,
Wojciech Maly:
Test Generation for Current Testing (CMOS ICs).
IEEE Design & Test of Computers 7(1): 26-38 (1990) |
| 1989 |
|---|
| 8 | | Wojciech Maly,
Samir B. Naik:
Process Monitoring Oriented IC Testing.
ITC 1989: 527-532 |
| 1987 |
|---|
| 7 | EE | Wojciech Maly:
Realistic Fault Modeling for VLSI Testing.
DAC 1987: 173-180 |
| 1986 |
|---|
| 6 | EE | Wojciech Maly:
Optimal order of the VLSI IC testing sequence.
DAC 1986: 560-566 |
| 5 | EE | Wojciech Maly,
Andrzej J. Strojwas,
Stephen W. Director:
VLSI Yield Prediction and Estimation: A Unified Framework.
IEEE Trans. on CAD of Integrated Circuits and Systems 5(1): 114-130 (1986) |
| 1985 |
|---|
| 4 | EE | Wojciech Maly,
Zygmunt Pizlo:
Tolerance Assignment for IC Selection Tests.
IEEE Trans. on CAD of Integrated Circuits and Systems 4(2): 156-162 (1985) |
| 3 | EE | Wojciech Maly:
Modeling of Lithography Related Yield Losses for CAD of VLSI Circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 4(3): 166-177 (1985) |
| 1984 |
|---|
| 2 | | Wojciech Maly,
F. Joel Ferguson,
John Paul Shen:
Systematic Characterization of Physical Defects for Fault Analysis of MOS IC Cells.
ITC 1984: 390-399 |
| 1982 |
|---|
| 1 | EE | Wojciech Maly,
Andrzej J. Strojwas:
Statistical Simulation of the IC Manufacturing Process.
IEEE Trans. on CAD of Integrated Circuits and Systems 1(3): 120-131 (1982) |
