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Amitava Majumdar Vis

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*2007
25EEYifeng Cui, Reagan Moore, Kim Olsen, Amit Chourasia, Philip Maechling, Bernard Minster, Steven M. Day, Yuanfang Hu, Jing Zhu, Amitava Majumdar, Thomas Jordan: Enabling Very-Large Scale Earthquake Simulations on Parallel Machines. International Conference on Computational Science (1) 2007: 46-53
2006
24EEAmitava Majumdar, Wei-Yu Chen, Jun Guo: Hold time validation on silicon and the relevance of hazards in timing analysis. DAC 2006: 326-331
23EETharaka Devadithya, Kim Baldridge, Adam Birnbaum, Amitava Majumdar, Dong Ju Choi, Richard Wolski, Simon K. Warfield, Neculai Archip: On-Demand High Performance Computing: Image Guided Neuro-Surgery Feasibility Study. ICPADS (2) 2006: 97-102
2005
22EEAmitava Majumdar, Adam Birnbaum, Dong Ju Choi, Abhishek Trivedi, Simon K. Warfield, Kim Baldridge, Petr Krysl: A Dynamic Data Driven Grid System for Intra-operative Image Guided Neurosurgery. International Conference on Computational Science (2) 2005: 672-679
2003
21EEOlivier Caty, Ismet Bayraktaroglu, Amitava Majumdar, Richard Lee, John Bell, Lisa Curhan: Instruction Based BIST for Board/System Level Test of External Memories and Internconnects. ITC 2003: 961-970
2002
20EEIshwar Parulkar, Thomas A. Ziaja, Rajesh Pendurkar, Anand D'Souza, Amitava Majumdar: A Scalable, Low Cost Design-for-Test Architecture for UltraSPARC? Chip Multi-Processors. ITC 2002: 726-735
19EEYuni K. Dewaraja, Michael Ljungberg, Amitava Majumdar, Abhijit Bose, Kenneth F. Koral: A parallel Monte Carlo code for planar and SPECT imaging: implementation, verification and applications in 131I SPECT. Computer Methods and Programs in Biomedicine 67(2): 115-124 (2002)
2001
18 Kamran Zarrineh, Thomas A. Ziaja, Amitava Majumdar: Automatic Generation and Validation of Memory Test Models for High Performance Microprocessors. ICCD 2001: 526-529
2000
17EEAmitava Majumdar: arallel Performance Study of Monte Carlo Photon Transport Code on Shared-, Distributed-, and Distributed-Shared-Memory Architectures. IPDPS 2000: 93-
16EEDimitri Kagaris, Spyros Tragoudas, Amitava Majumdar: Test-set partitioning for multi-weighted random LFSRs. Integration 30(1): 65-75 (2000)
1998
15EEDimitrios Kagaris, Spyros Tragoudas, Amitava Majumdar: On-Chip Test Embedding for Multi-Weighted Random LFSRs. DFT 1998: 135-
14EEAmitava Majumdar, Michio Komoda, Tim Ayres: Ground Bounce Considerations in DC Parametric Test Generation Using Boundary Scan. VTS 1998: 86-91
1997
13EERahul Simha, Amitava Majumdar: An urn model with applications to database performance evaluation. Computers & OR 24(4): 289-300 (1997)
1996
12 Dimitrios Kagaris, Spyros Tragoudas, Amitava Majumdar: On the Use of Counters for Reproducing Deterministic Test Sets. IEEE Trans. Computers 45(12): 1405-1419 (1996)
11 Amitava Majumdar: On Evaluating and Optimizing Weights for Weighted Random Pattern Testing. IEEE Trans. Computers 45(8): 904-916 (1996)
1995
10 Amitava Majumdar, Sarma B. K. Vrudhula: Fault Coverage and Test Length Estimation for Random Pattern Testing. IEEE Trans. Computers 44(2): 234-247 (1995)
1994
9 Amitava Majumdar: WRAPTure: A Tool for Evaluation and Optimization of Weights for Weighted Random Pattern Testing. ICCD 1994: 288-291
8 Rahul Simha, Amitava Majumdar: On Lookahead in the List Update Problem. Inf. Process. Lett. 50(2): 105-110 (1994)
7EEAmitava Majumdar, Sarma B. K. Vrudhula: Techniques for estimating test length under random test. J. Electronic Testing 5(2-3): 285-297 (1994)
1993
6 Amitava Majumdar, Sarma Sastry: Statistical Analysis of Controllability. VLSI Design 1993: 55-60
5EEAmitava Majumdar, Sarma Sastry: Probabilistic characterization of controllability in general homogeneous circuits. Computer-Aided Design 25(2): 76-93 (1993)
4EEAmitava Majumdar, Sarma B. K. Vrudhula: Analysis of signal probability in logic circuits using stochastic models. IEEE Trans. VLSI Syst. 1(3): 365-379 (1993)
1992
3EEAmitava Majumdar, Sarma Sastry: On the Distribution of Fault Coverage and Test length in Random Testing of Combinational Circuits. DAC 1992: 341-346
1991
2EESarma Sastry, Amitava Majumdar: A Branching Process Model for Observability Analysis of Combinational Circuits. DAC 1991: 452-457
1EESarma Sastry, Amitava Majumdar: Test efficiency analysis of random self-test of sequential circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 10(3): 390-398 (1991)

Coauthor Index

1Neculai Archip [23]
2Tim Ayres [14]
3Kim Baldridge [22] [23]
4Ismet Bayraktaroglu [21]
5John Bell [21]
6Adam Birnbaum [22] [23]
7Abhijit Bose [19]
8Olivier Caty [21]
9Wei-Yu Chen [24]
10Dong Ju Choi [22] [23]
11Amit Chourasia [25]
12Yifeng Cui [25]
13Lisa Curhan [21]
14Anand D'Souza [20]
15Steven M. Day [25]
16Tharaka Devadithya [23]
17Yuni K. Dewaraja [19]
18Jun Guo [24]
19Yuanfang Hu [25]
20Thomas Jordan [25]
21Dimitrios Kagaris (Dimitri Kagaris) [12] [15] [16]
22Michio Komoda [14]
23Kenneth F. Koral [19]
24Petr Krysl [22]
25Richard Lee [21]
26Michael Ljungberg [19]
27Philip Maechling [25]
28Bernard Minster [25]
29Reagan Moore (Reagan W. Moore) [25]
30Kim Olsen [25]
31Ishwar Parulkar [20]
32Rajesh Pendurkar [20]
33Sarma Sastry [1] [2] [3] [5] [6]
34Rahul Simha [8] [13]
35Spyros Tragoudas [12] [15] [16]
36Abhishek Trivedi [22]
37Sarma B. K. Vrudhula [4] [7] [10]
38Simon K. Warfield [22] [23]
39Richard Wolski [23]
40Kamran Zarrineh [18]
41Jing Zhu [25]
42Thomas A. Ziaja [18] [20]

Colors in the list of coauthors

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)