| 2007 |
|---|
| 10 | EE | Ruibing Lu,
Aiqun Cao,
Cheng-Kok Koh:
SAMBA-Bus: A High Performance Bus Architecture for System-on-Chips.
IEEE Trans. VLSI Syst. 15(1): 69-79 (2007) |
| 2006 |
|---|
| 9 | EE | Aiqun Cao,
Ruibing Lu,
Chen Li,
Cheng-Kok Koh:
Postlayout optimization for synthesis of Domino circuits.
ACM Trans. Design Autom. Electr. Syst. 11(4): 797-821 (2006) |
| 8 | EE | Ruibing Lu,
Cheng-Kok Koh:
Performance analysis of latency-insensitive systems.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(3): 469-483 (2006) |
| 2005 |
|---|
| 7 | EE | Ruibing Lu,
Aiqun Cao,
Cheng-Kok Koh:
Improving the scalability of SAMBA bus architecture.
ASP-DAC 2005: 1164-1167 |
| 6 | EE | Aiqun Cao,
Ruibing Lu,
Cheng-Kok Koh:
Post-layout logic duplication for synthesis of domino circuits with complex gates.
ASP-DAC 2005: 260-265 |
| 2004 |
|---|
| 5 | EE | Ruibing Lu,
Cheng-Kok Koh:
A high performance bus communication architecture through bus splitting.
ASP-DAC 2004: 751-755 |
| 2003 |
|---|
| 4 | EE | Ruibing Lu,
Cheng-Kok Koh:
Interconnect Planning with Local Area Constrained Retiming.
DATE 2003: 10442-10447 |
| 3 | EE | Ruibing Lu,
Cheng-Kok Koh:
Performance Optimization of Latency Insensitive Systems Through Buffer Queue Sizing of Communication Channels.
ICCAD 2003: 227-231 |
| 2 | EE | Ruibing Lu,
Cheng-Kok Koh:
SAMBA-Bus: A High Performance Bus Architecture for System-on-Chips.
ICCAD 2003: 8-12 |
| 2002 |
|---|
| 1 | EE | Ruibing Lu,
Guoan Zhong,
Cheng-Kok Koh,
Kai-Yuan Chao:
Flip-Flop and Repeater Insertion for Early Interconnect Planning.
DATE 2002: 690-695 |
