Gabriel H. Loh Vis

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41EEMichael B. Healy, Hsien-Hsin S. Lee, Gabriel H. Loh, Sung Kyu Lim: Thermal optimization in multi-granularity multi-core floorplanning. ASP-DAC 2009: 43-48
40EESamantika Subramaniam, Anne Bracy, Hong Wang, Gabriel H. Loh: Criticality-based optimizations for efficient load processing. HPCA 2009: 419-430
39EEYuejian Xie, Gabriel H. Loh: PIPP: promotion/insertion pseudo-partitioning of multi-core shared caches. ISCA 2009: 174-183
38EEGabriel H. Loh, Samantika Subramaniam, Yuejian Xie: Zesto: A cycle-level simulator for highly detailed microarchitecture exploration. ISPASS 2009: 53-64
37EEGabriel H. Loh: A modular 3d processor for flexible product design and technology migration. Conf. Computing Frontiers 2008: 159-170
36EESamantika Subramaniam, Milos Prvulovic, Gabriel H. Loh: PEEP: Exploiting predictability of memory dependences in SMT processors. HPCA 2008: 137-148
35EEGabriel H. Loh: 3D-Stacked Memory Architectures for Multi-core Processors. ISCA 2008: 453-464
34EEGabriel H. Loh, Daniel A. Jiménez: Modulo Path History for the Reduction of Pipeline Overheads in Path-based Neural Branch Predictors. International Journal of Parallel Programming 36(2): 267-286 (2008)
33EEKiran Puttaswamy, Gabriel H. Loh: Scalability of 3D-Integrated Arithmetic Units in High-Performance Microprocessors. DAC 2007: 622-625
32EEKiran Puttaswamy, Gabriel H. Loh: Thermal Herding: Microarchitecture Techniques for Controlling Hotspots in High-Performance 3D-Integrated Processors. HPCA 2007: 193-204
31EEPeter G. Sassone, Jeff Rupley, Edward Brekelbaum, Gabriel H. Loh, Bryan Black: Matrix scheduler reloaded. ISCA 2007: 335-346
30EEPeter G. Sassone, D. Scott Wills, Gabriel H. Loh: Static strands: Safely exposing dependence chains for increasing embedded power efficiency. ACM Trans. Embedded Comput. Syst. 6(4): (2007)
29EEGabriel H. Loh, Yuan Xie, Bryan Black: Processor Design in 3D Die-Stacking Technologies. IEEE Micro 27(3): 31-48 (2007)
28EEMichael B. Healy, Mario Vittes, Mongkol Ekpanyapong, Chinnakrishnan S. Ballapuram, Sung Kyu Lim, Hsien-Hsin S. Lee, Gabriel H. Loh: Multiobjective Microarchitectural Floorplanning for 2-D and 3-D ICs. IEEE Trans. on CAD of Integrated Circuits and Systems 26(1): 38-52 (2007)
27EEKiran Puttaswamy, Gabriel H. Loh: Dynamic instruction schedulers in a 3-dimensional integration technology. ACM Great Lakes Symposium on VLSI 2006: 153-158
26EEKiran Puttaswamy, Gabriel H. Loh: Thermal analysis of a 3D die-stacked high-performance microprocessor. ACM Great Lakes Symposium on VLSI 2006: 19-24
25EEChinnakrishnan S. Ballapuram, Kiran Puttaswamy, Gabriel H. Loh, Hsien-Hsin S. Lee: Entropy-based low power data TLB design. CASES 2006: 304-311
24EEMichael B. Healy, Mario Vittes, Mongkol Ekpanyapong, Chinnakrishnan S. Ballapuram, Sung Kyu Lim, Hsien-Hsin S. Lee, Gabriel H. Loh: Microarchitectural floorplanning under performance and thermal tradeoff. DATE 2006: 1288-1293
23EESamantika Subramaniam, Gabriel H. Loh: Store vectors for scalable memory dependence prediction and scheduling. HPCA 2006: 65-76
22EEKiran Puttaswamy, Gabriel H. Loh: The impact of 3-dimensional integration on the design of arithmetic units. ISCAS 2006
21EEGabriel H. Loh: Revisiting the performance impact of branch predictor latencies. ISPASS 2006: 59-69
20EEKiran Puttaswamy, Gabriel H. Loh: Implementing Register Files for High-Performance Microprocessors in a Die-Stacked (3D) Technology. ISVLSI 2006: 384-392
19EESamantika Subramaniam, Gabriel H. Loh: Fire-and-Forget: Load/Store Scheduling with No Store Queue at All. MICRO 2006: 273-284
18EERanjith Subramanian, Yannis Smaragdakis, Gabriel H. Loh: Adaptive Caches: Effective Shaping of Cache Behavior to Workloads. MICRO 2006: 385-396
17EEBryan Black, Murali Annavaram, Ned Brekelbaum, John DeVale, Lei Jiang, Gabriel H. Loh, Don McCaule, Pat Morrow, Donald W. Nelson, Daniel Pantuso, Paul Reed, Jeff Rupley, Sadasivan Shankar, John Paul Shen, Clair Webb: Die Stacking (3D) Microarchitecture. MICRO 2006: 469-479
16EEDaniel A. Jiménez, Gabriel H. Loh: Controlling the Power and Area of Neural Branch Predictors for Practical Implementation in High-Performance Processors. SBAC-PAD 2006: 55-62
15EEYuan Xie, Gabriel H. Loh, Bryan Black, Kerry Bernstein: Design space exploration for 3D architectures. JETC 2(2): 65-103 (2006)
14EEKiran Puttaswamy, Gabriel H. Loh: Implementing Caches in a 3D Technology for High Performance Processors. ICCD 2005: 525-532
13EEGabriel H. Loh: A Simple Divide-and-Conquer Approach for Neural-Class Branch Prediction. IEEE PACT 2005: 243-254
12EEGabriel H. Loh: Simulation Differences Between Academia and Industry: A Branch Prediction Case Study. ISPASS 2005: 21-31
11EEPeter G. Sassone, D. Scott Wills, Gabriel H. Loh: Static strands: safely collapsing dependence chains for increasing embedded power efficiency. LCTES 2005: 127-136
10EEGabriel H. Loh, Dana S. Henry, Arvind Krishnamurthy: Exploiting Bias in the Hysteresis Bit of 2-bit Saturating Counters in Branch Predictors. J. Instruction-Level Parallelism 5: (2003)
9EEGabriel H. Loh: Width-Partitioned Load Value Predictors. J. Instruction-Level Parallelism 5: (2003)
8EEGabriel H. Loh, Dana S. Henry: Applying Machine Learning for Ensemble Branch Predictors. IEA/AIE 2002: 264-274
7EEGabriel H. Loh, Dana S. Henry: Predicting Conditional Branches With Fusion-Based Hybrid Predictors. IEEE PACT 2002: 165-
6EEDana S. Henry, Gabriel H. Loh, Rahul Sami: Speculative Clustered Caches for Clustered Processors. ISHPC 2002: 281-290
5EEGabriel H. Loh: Exploiting data-width locality to increase superscalar execution bandwidth. MICRO 2002: 395-405
4EEBradley C. Kuszmaul, Dana S. Henry, Gabriel H. Loh: A Comparison of Asymptotically Scalable Superscalar Processors. Theory Comput. Syst. 35(2): 129-150 (2002)
3EEGabriel H. Loh: A time-stamping algorithm for efficient performance estimation of superscalar processors. SIGMETRICS/Performance 2001: 72-81
2EEDana S. Henry, Bradley C. Kuszmaul, Gabriel H. Loh, Rahul Sami: Circuits for wide-window superscalar processors. ISCA 2000: 236-247
1EEBradley C. Kuszmaul, Dana S. Henry, Gabriel H. Loh: A Comparison of Scalable Superscalar Processors. SPAA 1999: 126-137

Coauthor Index

1Murali Annavaram [17]
2Chinnakrishnan S. Ballapuram [24] [25] [28]
3Kerry Bernstein [15]
4Bryan Black [15] [17] [29] [31]
5Anne Bracy [40]
6Edward Brekelbaum [31]
7Ned Brekelbaum [17]
8John DeVale [17]
9Mongkol Ekpanyapong [24] [28]
10Michael B. Healy [24] [28] [41]
11Dana S. Henry [1] [2] [4] [6] [7] [8] [10]
12Lei Jiang [17]
13Daniel A. Jiménez [16] [34]
14Arvind Krishnamurthy [10]
15Bradley C. Kuszmaul [1] [2] [4]
16Hsien-Hsin S. Lee [24] [25] [28] [41]
17Sung Kyu Lim [24] [28] [41]
18Don McCaule [17]
19Pat Morrow [17]
20Donald W. Nelson [17]
21Daniel Pantuso [17]
22Milos Prvulovic [36]
23Kiran Puttaswamy [14] [20] [22] [25] [26] [27] [32] [33]
24Paul Reed [17]
25Jeff Rupley [17] [31]
26Rahul Sami [2] [6]
27Peter G. Sassone [11] [30] [31]
28Sadasivan Shankar [17]
29John Paul Shen [17]
30Yannis Smaragdakis [18]
31Samantika Subramaniam [19] [23] [36] [38] [40]
32Ranjith Subramanian [18]
33Mario Vittes [24] [28]
34Hong Wang [40]
35Clair Webb [17]
36D. Scott Wills [11] [30]
37Yuan Xie [15] [29]
38Yuejian Xie [38] [39]

Colors in the list of coauthors

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)