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Jien-Chung Lo Vis

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*2006
37EEChuen-Song Chen, Jien-Chung Lo, Tian Xia: An indirect current sensing technique for IDDQ and IDDT tests. ACM Great Lakes Symposium on VLSI 2006: 235-240
36EEChuen-Song Chen, Jien-Chung Lo, Tian Xia: Equivalent IDDQ Tests for Systems with Regulated Power Supply. DFT 2006: 291-299
35EEJien-Chung Lo, Cecilia Metra, Fabrizio Lombardi: Guest Editors' Introduction: Special Section on Design and Test of Systems-on-Chip (SoC). IEEE Trans. Computers 55(2): 97-98 (2006)
2005
34EEJien-Chung Lo, Yu-Lun Wan, Eiji Fujiwara: Transient Behavior of the Encoding/Decoding Circuits of Error Correcting Codes. DFT 2005: 120-130
33EETian Xia, Jien-Chung Lo: On-chip short-time interval measurement system for high-speed signal timing characterization. Journal of Systems Architecture 51(4): 265-276 (2005)
2004
32EESeok-Bum Ko, Jien-Chung Lo: Efficient Realization of Parity Prediction Functions in FPGAs. J. Electronic Testing 20(5): 489-499 (2004)
2003
31EETian Xia, Jien-Chung Lo: On-Chip Short-Time Interval Measurement for High-Speed Signal Timing Characterization. Asian Test Symposium 2003: 326-331
30EESeok-Bum Ko, Jien-Chung Lo: A Novel Technology Mapping Method for AND/XOR Expressions. ISMVL 2003: 133-138
2002
29EETian Xia, Jien-Chung Lo: On-Chip Jitter Measurement for Phase Locked Loops. DFT 2002: 399-407
28EESeok-Bum Ko, Jien-Chung Lo: Efficient Decomposition Techniques for FPGAs. HiPC 2002: 630-642
27EEJien-Chung Lo: Analysis of a BICS-Only Concurrent Error Detection Method. IEEE Trans. Computers 51(3): 241-253 (2002)
26EESeok-Bum Ko, Yu-Yau Guo, Jien-Chung Lo: Studies of the SEMATECH IDDq test data. Journal of Systems Architecture 47(10): 831-846 (2002)
2001
25EESeok-Bum Ko, Tian Xia, Jien-Chung Lo: Efficient Parity Prediction in FPGA. DFT 2001: 176-181
24EEJien-Chung Lo, William D. Armitage, Corbet S. Johnson: Using Atomic Force Microscopy for Deep-Submicron Failure Analysis. IEEE Design & Test of Computers 18(1): 10-18 (2001)
2000
23EEShengli Li, Kai Zhang, Jien-Chung Lo: The 2nd Order Analysis of IDDQ Test Data. DFT 2000: 376-
22EEAugustus K. Uht, Jien-Chung Lo, Ying Sun, James C. Daly, James Kowalski: Building Real Computer Systems. IEEE Micro 20(3): 48-56 (2000)
21EECecilia Metra, Jien-Chung Lo: Intermediacy Prediction for High Speed Berger Code Checkers. J. Electronic Testing 16(6): 607-615 (2000)
1999
20EEWilliam D. Armitage, Jien-Chung Lo: Erasure Error Correction with Hardware Detection. DFT 1999: 293-301
1998
19EEYu-Yau Guo, Jien-Chung Lo: Challenges of Built-In Current Sensor Designs. DFT 1998: 192-
18EEJien-Chung Lo: Highly Reliable Systems with Differential Built-In Current Sensors. DFT 1998: 261-269
17EEJien-Chung Lo: Online Current Testing. IEEE Design & Test of Computers 15(4): 49-56 (1998)
16 Jien-Chung Lo: Correction to ``A Fast Binary Adder with Conditional Carry Generation'' IEEE Transaction on Computers 46(2) 248-253 (1997). IEEE Trans. Computers 47(12): 1425 (1998)
1997
15EEYu-Yau Guo, Jien-Chung Lo, Cecilia Metra: Fast and area-time efficient Berger code checkers. DFT 1997: 110-118
14 Jien-Chung Lo: A Fast Binary Adder with Conditional Carry Generation. IEEE Trans. Computers 46(2): 248-253 (1997)
1996
13 Jien-Chung Lo, Suchai Thanawastien, T. R. N. Rao: Berger Check Prediction for Array Multipliers and Array Dividers. IEEE Trans. Computers 45(3): 383 (1996)
12 Jien-Chung Lo, Eiji Fujiwara: Probability to Achieve TSC Goal. IEEE Trans. Computers 45(4): 450-460 (1996)
11 Jien-Chung Lo: A Hyper Optimal Encoding Scheme for Self-Checking Circuits. IEEE Trans. Computers 45(9): 1022-1030 (1996)
1995
10EEJien-Chung Lo, James C. Daly, Michael Nicolaidis: A strongly code disjoint built-in current sensor for strongly fault-secure static CMOS realizations. IEEE Trans. on CAD of Integrated Circuits and Systems 14(11): 1402-1407 (1995)
1994
9 Jien-Chung Lo: Reliable Floating-Point Arithmetic Algorithms for Error-Coded Operands. IEEE Trans. Computers 43(4): 400-412 (1994)
1993
8 Jien-Chung Lo, Eiji Fujiwara: A Probabilistic Measurement for Totally Self-Checking Circuits. DFT 1993: 263-270
7 Jien-Chung Lo: Fault-Tolerant Content Addressable Memory. ICCD 1993: 193-196
6 Jien-Chung Lo, Suchai Thanawastien, T. R. N. Rao: Berger Check Prediction for Array Multipliers and Array Dividers. IEEE Trans. Computers 42(7): 892-896 (1993)
5 T. R. N. Rao, Gui Liang Feng, Mahadev S. Kolluru, Jien-Chung Lo: Novel Totally Self-Checking Berger Code Checker Designs Based on Generalized Berger Code Partitioning. IEEE Trans. Computers 42(8): 1020-1024 (1993)
1992
4 Jien-Chung Lo, James C. Daly, Michael Nicolaidis: Design of Static CMOS Self-Checking Circuits using Built-In Current Sensing. FTCS 1992: 104-111
3 Jien-Chung Lo: Reliable Floating-Point Arithmetic Algorithms for Berger Encoded Operands. ICCD 1992: 110-113
2EEJien-Chung Lo, Suchai Thanawastien, T. R. N. Rao, Michael Nicolaidis: An SFS Berger check prediction ALU and its application to self-checking processor designs. IEEE Trans. on CAD of Integrated Circuits and Systems 11(4): 525-540 (1992)
1990
1 Jien-Chung Lo, Suchai Thanawastien: On the Design of Combinational Totally Self-Checking I-out-of3 Code Checkers. IEEE Trans. Computers 39(3): 387-393 (1990)

Coauthor Index

1William D. Armitage [20] [24]
2Chuen-Song Chen [36] [37]
3James C. Daly [4] [10] [22]
4Gui Liang Feng [5]
5Eiji Fujiwara [8] [12] [34]
6Yu-Yau Guo [15] [19] [26]
7Corbet S. Johnson [24]
8Seok-Bum Ko [25] [26] [28] [30] [32]
9Mahadev S. Kolluru [5]
10James Kowalski [22]
11Shengli Li [23]
12Fabrizio Lombardi [35]
13Cecilia Metra [15] [21] [35]
14Michael Nicolaidis [2] [4] [10]
15T. R. N. Rao (Thammavarapu R. N. Rao) [2] [5] [6] [13]
16Ying Sun [22]
17Suchai Thanawastien [1] [2] [6] [13]
18Augustus K. Uht [22]
19Yu-Lun Wan [34]
20Tian Xia [25] [29] [31] [33] [36] [37]
21Kai Zhang [23]

Colors in the list of coauthors

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)