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C. L. Liu Vis

Chung Laung (Dave) Liu

劉炯朗

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*2005
106EEC. L. Liu: The High Walls have Crumpled. VLSI Design 2005: 21-
2003
105EEAli Pinar, C. L. Liu: Compacting sequences with invariant transition frequencies. ACM Trans. Design Autom. Electr. Syst. 8(2): 214-221 (2003)
104EEKi-Wook Kim, Seong-Ook Jung, Unni Narayanan, C. L. Liu, Sung-Mo Kang: Noise-aware interconnect power optimization in domino logic synthesis. IEEE Trans. VLSI Syst. 11(1): 79-89 (2003)
103EEKi-Wook Kim, Seong-Ook Jung, Taewhan Kim, Prashant Saxena, C. L. Liu, S.-M. S. Kang: Coupling delay optimization by temporal decorrelation using dual threshold voltage technique. IEEE Trans. VLSI Syst. 11(5): 879-887 (2003)
2002
102EEKi-Wook Kim, Taewhan Kim, TingTing Hwang, Sung-Mo Kang, C. L. Liu: Logic transformation for low-power synthesis. ACM Trans. Design Autom. Electr. Syst. 7(2): 265-283 (2002)
101EEKi-Wook Kim, Taewhan Kim, C. L. Liu, Sung-Mo Kang: Domino logic synthesis based on implication graph. IEEE Trans. on CAD of Integrated Circuits and Systems 21(2): 232-240 (2002)
100EEKi-Seok Chung, Taewhan Kim, C. L. Liu: A Complete Model for Glitch Analysis in Logic Circuits. Journal of Circuits, Systems, and Computers 11(2): 137-154 (2002)
99EEKi-Seok Chung, Rajesh K. Gupta, Taewhan Kim, C. L. Liu: Synthesis and Optimization of Combinational Interface Circuits. VLSI Signal Processing 31(3): 243-261 (2002)
2001
98EEKi-Wook Kim, Seong-Ook Jung, Prashant Saxena, C. L. Liu, Sung-Mo Kang: Coupling Delay Optimization by Temporal Decorrelation using Dual Threshold Voltage Technique. DAC 2001: 732-737
97EEYi-Yu Liu, Kuo-Hua Wang, TingTing Hwang, C. L. Liu: Binary decision diagram with minimum expected path length. DATE 2001: 708-712
96EEChau-Shen Chen, TingTing Hwang, C. L. Liu: Architecture driven circuit partitioning. IEEE Trans. VLSI Syst. 9(2): 383-389 (2001)
95EEPrashant Saxena, C. L. Liu: Optimization of the maximum delay of global interconnects duringlayer assignment. IEEE Trans. on CAD of Integrated Circuits and Systems 20(4): 503-515 (2001)
94EEKi-Seok Chung, Taewhan Kim, C. L. Liu: G-vector: A New Model for Glitch Analysis in Logic Circuits. VLSI Signal Processing 27(3): 235-251 (2001)
2000
93EEJunhyung Um, Taewhan Kim, C. L. Liu: A fine-grained arithmetic optimization technique for high-performance/low-power data path synthesis. DAC 2000: 98-103
92 Ki-Wook Kim, Kwang-Hyun Baek, Naresh R. Shanbhag, C. L. Liu, Sung-Mo Kang: Coupling-Driven Signal Encoding Scheme for Low-Power Interface Design. ICCAD 2000: 318-321
91EEKi-Wook Kim, Seong-Ook Jung, Unni Narayanan, C. L. Liu, Sung-Mo Kang: Noise-aware power optimization for on-chip interconnect. ISLPED 2000: 108-113
90EEPrashant Saxena, C. L. Liu: A postprocessing algorithm for crosstalk-driven wire perturbation. IEEE Trans. on CAD of Integrated Circuits and Systems 19(6): 691-702 (2000)
1999
89EEPrashant Saxena, C. L. Liu: Crosstalk Minimization Using Wire Perturbations. DAC 1999: 100-103
88EEKi-Wook Kim, Sung-Mo Kang, TingTing Hwang, C. L. Liu: Logic Transformation for Low Power Synthesis. DATE 1999: 158-162
87EEKi-Wook Kim, C. L. Liu, Sung-Mo Kang: Implication graph based domino logic synthesis. ICCAD 1999: 111-114
86EEJunhyung Um, Taewhan Kim, C. L. Liu: Optimal allocation of carry-save-adders in arithmetic optimization. ICCAD 1999: 410-413
85EEC. L. Liu: From Time Sharing to Real Time-Sharing of a Really Good Time in the Last 40 Years. IEEE Real-Time Systems Symposium 1999: 5
84EEChaeryung Park, Taewhan Park, C. L. Liu: An efficient data path synthesis algorithm for behavioral-level power optimization. ISCAS (1) 1999: 294-297
83EEPrashant Saxena, Peichen Pan, C. L. Liu: The Retiming of Single-Phase Clocked Circuits Containing Level-Sensitive Latches. VLSI Design 1999: 402-407
82 Peichen Pan, C. L. Liu: Partial Scan with Preselected Scan Signals. IEEE Trans. Computers 48(9): 1000-1005 (1999)
1998
81EEPrashant Saxena, C. L. Liu: A performance-driven layer assignment algorithm for multiple interconnect trees. ICCAD 1998: 124-127
80EEChau-Shen Chen, TingTing Hwang, C. L. Liu: Architecture driven circuit partitioning. ICCAD 1998: 408-411
79EEAli Pinar, C. L. Liu: Power invariant vector sequence compaction. ICCAD 1998: 473-476
78EEUnni Narayanan, Peichen Pan, C. L. Liu: Low power logic synthesis under a general delay model. ISLPED 1998: 209-214
77EEKi-Seok Chung, C. L. Liu: Local transformation techniques for multi-level logiccircuits utilizing circuit symmetries for power reduction. ISLPED 1998: 215-220
76EEPeichen Pan, C. L. Liu: Optimal clock period FPGA technology mapping for sequential circuits. ACM Trans. Design Autom. Electr. Syst. 3(3): 437-462 (1998)
75EEPeichen Pan, Arvind K. Karandikar, C. L. Liu: Optimal clock period clustering for sequential circuits with retiming. IEEE Trans. on CAD of Integrated Circuits and Systems 17(6): 489-498 (1998)
74EEChaeryung Park, Taewhan Kim, C. L. Liu: Register Allocation - A Hierarchical Reduction Approach. VLSI Signal Processing 19(3): 269-285 (1998)
1997
73EEChau-Shen Chen, TingTing Hwang, C. L. Liu: Low Power FPGA Design - A Re-engineering Approach. DAC 1997: 656-661
72EEUnni Narayanan, C. L. Liu: Low power logic synthesis for XOR based circuits. ICCAD 1997: 570-574
71 Arvind K. Karandikar, Peichen Pan, C. L. Liu: Optimal Clock Period Clustering for Sequential Circuits with Retiming. ICCD 1997: 122-127
70 Peichen Pan, Sai-keung Dong, C. L. Liu: Optimal Graph Constraint Reduction for Symbolic Layout Compaction. Algorithmica 18(4): 560-574 (1997)
69EEYachyang Sun, Ting-Chi Wang, Chak-Kuen Wong, C. L. Liu: Routing for symmetric FPGAs and FPICs. IEEE Trans. on CAD of Integrated Circuits and Systems 16(1): 20-31 (1997)
68EEAnmol Mathur, C. L. Liu: Timing-driven placement for regular architectures. IEEE Trans. on CAD of Integrated Circuits and Systems 16(6): 597-608 (1997)
1996
67EEPeichen Pan, C. L. Liu: Optimal Clock Period FPGA Technology Mapping for Sequential Circuits. DAC 1996: 720-725
66EEXiangfeng Chen, Peichen Pan, C. L. Liu: Desensitization for Power Reduction in Sequential Circuits. DAC 1996: 795-800
65EEVamsi Boppana, Prashant Saxena, Prithviraj Banerjee, W. Kent Fuchs, C. L. Liu: A Parallel Algorithm for the Technology Mapping of LUT-Based FPGAs. Euro-Par, Vol. I 1996: 828-831
64EEPeichen Pan, C. L. Liu: Technology Mapping of Sequential Circuits for LUT-Based FPGAs for Performance. FPGA 1996: 58-64
63EEKi-Seok Chung, Rajesh K. Gupta, C. L. Liu: An algorithm for synthesis of system-level interface circuits. ICCAD 1996: 442-447
62EESue-Hong Chow, Yi-Cheng Ho, TingTing Hwang, C. L. Liu: Low power realization of finite state machines - a decomposition approach. ACM Trans. Design Autom. Electr. Syst. 1(3): 315-340 (1996)
61 Peichen Pan, Weiping Shi, C. L. Liu: Area Minimization for Hierarchical Floorplans. Algorithmica 15(6): 550-571 (1996)
60EETong Gao, C. L. Liu: Minimum crosstalk channel routing. IEEE Trans. on CAD of Integrated Circuits and Systems 15(5): 465-474 (1996)
59EETaewhan Kim, C. L. Liu: An integrated algorithm for incremental data path synthesis. VLSI Signal Processing 12(3): 265-285 (1996)
1995
58EEPeichen Pan, C. L. Liu: Partial Scan with Pre-selected Scan Signals. DAC 1995: 189-194
57EEAnmol Mathur, K. C. Chen, C. L. Liu: Applications of Slack Neighborhood Graphs to Timing Driven Optimization Problems in FPGAs. FPGA 1995: 118-124
56EEAnmol Mathur, K. C. Chen, C. L. Liu: Re-engineering of timing constrained placements for regular architectures. ICCAD 1995: 485-490
55EERan Libeskind-Hadas, Nimish Shrivastava, Rami G. Melhem, C. L. Liu: Optimal Reconfiguration Algorithms for Real-Time Fault-Tolerant Processor Arrays. IEEE Trans. Parallel Distrib. Syst. 6(5): 498-511 (1995)
54EEPeichen Pan, C. L. Liu: Area minimization for floorplans. IEEE Trans. on CAD of Integrated Circuits and Systems 14(1): 123-132 (1995)
1994
53EEYachyang Sun, C. L. Liu: Routing in a New 2-Dimensional FPGA/FPIC Routing Architecture. DAC 1994: 171-176
52EESrilata Raman, C. L. Liu, Larry G. Jones: A delay driven FPGA placement algorithm. EURO-DAC 1994: 277-282
51EEAnmol Mathur, C. L. Liu: Compression-relaxation: a new approach to performance driven placement for regular architectures. ICCAD 1994: 130-136
50EEPeichen Pan, Weiping Shi, C. L. Liu: Area minimization for hierarchical floorplans. ICCAD 1994: 436-440
49EETong Gao, C. L. Liu: Minimum crosstalk switchbox routing. ICCAD 1994: 610-615
48EETaewhan Kim, Noritake Yonezawa, Jane W.-S. Liu, C. L. Liu: A scheduling algorithm for conditional resource sharing-a hierarchical reduction approach. IEEE Trans. on CAD of Integrated Circuits and Systems 13(4): 425-438 (1994)
1993
47EETaewhan Kim, C. L. Liu: Utilization of Multiport Memories in Data Path Synthesis. DAC 1993: 298-302
46EEPeichen Pan, Sai-keung Dong, C. L. Liu: Optimal Graph Constraint Reduction for Symbolic Layout Compaction. DAC 1993: 401-406
45EEYachyang Sun, Ting-Chi Wang, Chak-Kuen Wong, C. L. Liu: Routing for symmetric FPGAs and FPICs. ICCAD 1993: 486-490
44EETong Gao, C. L. Liu: Minimum crosstalk channel routing. ICCAD 1993: 692-696
43EEWei Kuan Shih, Jane W.-S. Liu, C. L. Liu: Modified Rate-Monotonic Algorithm for Scheduling Periodic Jobs with Deferred Deadlines. IEEE Trans. Software Eng. 19(12): 1171-1179 (1993)
42EEJason Cong, Bryan Preas, C. L. Liu: Physical models and efficient algorithms for over-the-cell routing in standard cell design. IEEE Trans. on CAD of Integrated Circuits and Systems 12(5): 723-734 (1993)
1992
41EETong Gao, Pravin M. Vaidya, C. L. Liu: A Performance Driven Macro-Cell Placement Algorithm. DAC 1992: 147-152
40EEPeichen Pan, C. L. Liu: Area minimization for general floorplans. ICCAD 1992: 606-609
39 Yachyang Sun, C. L. Liu: An Area Minimizer for Floorplans with L-Shaped Regions. ICCD 1992: 383-386
1991
38 Yachyang Sun, Sai-keung Dong, Shinji Sato, C. L. Liu: A Channel Router for Single Layer Customization Technology. ICCAD 1991: 436-439
37 Tong Gao, Pravo M. Vaidya, C. L. Liu: A New Performance Driven Placement Algorithm. ICCAD 1991: 44-47
36 Taewhan Kim, Jane W.-S. Liu, C. L. Liu: A Scheduling Algorithm for Conditional Resource Sharing. ICCAD 1991: 84-87
35EEJason Cong, C. L. Liu: On the k-layer planar subset and topological via minimization problems. IEEE Trans. on CAD of Integrated Circuits and Systems 10(8): 972-981 (1991)
34 Philip K. McKinley, N. Hasan, Ran Libeskind-Hadas, C. L. Liu: Disjoint Covers in Replicated Heterogeneous Arrays. SIAM J. Discrete Math. 4(2): 281-292 (1991)
1990
33EEJason Cong, Bryan Preas, C. L. Liu: General Models and Algorithms for Over-the-Cell Routing in Standard Cell Design. DAC 1990: 709-715
32EEJason Cong, C. L. Liu: On the k-layer planar subset and via minimization problems. EURO-DAC 1990: 459-463
31EEXianjin Yao, C. L. Liu: Solution of a module orientation and rotation problem. EURO-DAC 1990: 584-588
30EEJason Cong, C. L. Liu: Over-the-cell channel routing. IEEE Trans. on CAD of Integrated Circuits and Systems 9(4): 408-418 (1990)
1989
29EERan Libeskind-Hadas, C. L. Liu: Solutions to the Module Orientation and Rotation Problems by Neural Computation Networks. DAC 1989: 400-405
28 D. F. Wong, C. L. Liu: Floorplan Design of VLSI Circuits. Algorithmica 4(2): 263-291 (1989)
27EEXiaojun Shen, Y. Z. Cai, C. L. Liu, Clyde P. Kruskal: Generalized latin squares I. Discrete Applied Mathematics 25(1-2): 155-178 (1989)
26EEXianjin Yao, Masaaki Yamada, C. L. Liu: A new approach to the pin assignment problem. IEEE Trans. on CAD of Integrated Circuits and Systems 8(9): 999-1006 (1989)
1988
25EEXianji Yao, Masaaki Yamada, C. L. Liu: A New Approach to the Pin Assignment Problem. DAC 1988: 566-572
24EEJason Cong, Martin D. F. Wong, C. L. Liu: A new approach to three- or four-layer channel routing. IEEE Trans. on CAD of Integrated Circuits and Systems 7(10): 1094-1104 (1988)
1987
23EED. F. Wong, C. L. Liu: Array Optimization for VLSI Synthesis. DAC 1987: 537-543
1986
22EED. F. Wong, C. L. Liu: A new algorithm for floorplan design. DAC 1986: 101-107
21 J. L. Lewandowski, C. L. Liu, Jane W.-S. Liu: An Algorithmic Proof of a Generalization of the Birkhoff-Von Neumann Theorem. J. Algorithms 7(3): 323-330 (1986)
1985
20 Prakash V. Ramanan, C. L. Liu: Permutation Representation of k-Ary Trees. Theor. Comput. Sci. 38: 83-98 (1985)
1984
19EEJ. R. Egan, C. L. Liu: Bipartite Folding and Partitioning of a PLA. IEEE Trans. on CAD of Integrated Circuits and Systems 3(3): 191-199 (1984)
18 Prakash V. Ramanan, Jitender S. Deogun, C. L. Liu: A Personnel Assignment Problem. J. Algorithms 5(1): 132-144 (1984)
1983
17 W.-D. Wei, C. L. Liu: On a Periodic Maintenance Problem. Oper. Res. Lett. 2(2): 90-93 (1983)
16 D. T. Lee, C. L. Liu, C. K. Wong: (g 0, g 1, ... g k)-Trees and Unary OL Systems. Theor. Comput. Sci. 22: 209-217 (1983)
1982
15 C. L. Liu, Jane W.-S. Liu, Arthur L. Liestman: Scheduling with Slack Time. Acta Inf. 17: 31-41 (1982)
1980
14 C. L. Liu: Generation of trees. CLAAP 1980: 45-53
1978
13 Jane W.-S. Liu, C. L. Liu: Performance Analysis of Multiprocessor Systems Containing Functionally Dedicated Processors. Acta Inf. 10: 95-104 (1978)
1976
12 C. L. Liu: Deterministic Job Scheduling in Computing Systems. Performance 1976: 241-254
1974
11 Jane W.-S. Liu, C. L. Liu: Bounds on Scheduling Algorithms for Heterogeneous Comnputing Systems. IFIP Congress 1974: 349-353
10 N. F. Chen, C. L. Liu: On a Class of Scheduling Algorithms for Multiprocessors Computing Systems. Sagamore Computer Conference 1974: 1-16
1973
9EEC. K. Wong, C. L. Liu, J. Apter: A drum scheduling algorithm. Automatentheorie und Formale Sprachen 1973: 267-275
8EEC. L. Liu, James W. Layland: Scheduling Algorithms for Multiprogramming in a Hard-Real-Time Environment. J. ACM 20(1): 46-61 (1973)
1972
7 C. L. Liu: Optimal Scheduling on Multi-Processor Computing Systems FOCS 1972: 155-160
6 C. L. Liu: Analysis and Synthesis of Sorting Algorithms. SIAM J. Comput. 1(4): 290-304 (1972)
1971
5 C. L. Liu: Analysis of Sorting Algorithms FOCS 1971: 207-215
1969
4 C. L. Liu: A Note on Definite Stochastic Sequential Machines Information and Control 14(4): 407-421 (1969)
3EEC. L. Liu: Lattice Functions, Pair Algebras, and Finite-State Machines. J. ACM 16(3): 442-454 (1969)
1966
2 C. L. Liu: Pair Algebra and Its Application FOCS 1966: 103-112
1964
1 C. L. Liu: Sequential-machine realization using feedback shift registers FOCS 1964: 209-227

Coauthor Index

1J. Apter [9]
2Kwang-Hyun Baek [92]
3Prithviraj Banerjee (Prith Banerjee) [65]
4Vamsi Boppana [65]
5Y. Z. Cai [27]
6Chau-Shen Chen [73] [80] [96]
7K. C. Chen [56] [57]
8N. F. Chen [10]
9Xiangfeng Chen [66]
10Sue-Hong Chow [62]
11Ki-Seok Chung [63] [77] [94] [99] [100]
12Jason Cong [24] [30] [32] [33] [35] [42]
13Jitender S. Deogun [18]
14Sai-keung Dong [38] [46] [70]
15J. R. Egan [19]
16W. Kent Fuchs [65]
17Tong Gao [37] [41] [44] [49] [60]
18Rajesh K. Gupta (Rajesh Gupta) [63] [99]
19N. Hasan [34]
20Yi-Cheng Ho [62]
21TingTing Hwang [62] [73] [80] [88] [96] [97] [102]
22Larry G. Jones [52]
23Seong-Ook Jung [91] [98] [103] [104]
24S.-M. S. Kang [103]
25Sung-Mo Kang [87] [88] [91] [92] [98] [101] [102] [104]
26Arvind K. Karandikar [71] [75]
27Ki-Wook Kim [87] [88] [91] [92] [98] [101] [102] [103] [104]
28Taewhan Kim [36] [47] [48] [59] [74] [86] [93] [94] [99] [100] [101] [102] [103]
29Clyde P. Kruskal [27]
30James W. Layland [8]
31D. T. Lee (Der-Tsai Lee) [16]
32J. L. Lewandowski [21]
33Ran Libeskind-Hadas [29] [34] [55]
34Arthur L. Liestman [15]
35Jane W.-S. Liu [11] [13] [15] [21] [36] [43] [48]
36Yi-Yu Liu [97]
37Anmol Mathur [51] [56] [57] [68]
38Philip K. McKinley [34]
39Rami G. Melhem [55]
40Unni Narayanan [72] [78] [91] [104]
41Peichen Pan [40] [46] [50] [54] [58] [61] [64] [66] [67] [70] [71] [75] [76] [78] [82] [83]
42Chaeryung Park [74] [84]
43Taewhan Park [84]
44Ali Pinar [79] [105]
45Bryan Preas [33] [42]
46Srilata Raman [52]
47Prakash V. Ramanan [18] [20]
48Shinji Sato [38]
49Prashant Saxena [65] [81] [83] [89] [90] [95] [98] [103]
50Naresh R. Shanbhag [92]
51Xiaojun Shen [27]
52Weiping Shi [50] [61]
53Wei Kuan Shih [43]
54Nimish Shrivastava [55]
55Yachyang Sun [38] [39] [45] [53] [69]
56Junhyung Um [86] [93]
57Pravin M. Vaidya [41]
58Pravo M. Vaidya [37]
59Kuo-Hua Wang [97]
60Ting-Chi Wang [45] [69]
61W.-D. Wei [17]
62Chak-Kuen Wong (C. K. Wong) [9] [16] [45] [69]
63Martin D. F. Wong (D. F. Wong) [22] [23] [24] [28]
64Masaaki Yamada [25] [26]
65Xianji Yao [25]
66Xianjin Yao [26] [31]
67Noritake Yonezawa [48]

Colors in the list of coauthors

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)