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David M. Lewis Vis

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*2005
29EEDavid M. Lewis, Elias Ahmed, Gregg Baeckler, Vaughn Betz, Mark Bourgeault, David Cashman, David R. Galloway, Mike Hutton, Christopher Lane, Andy Lee, Paul Leventis, Sandy Marquardt, Cameron McClintock, Ketan Padalia, Bruce Pedersen, Giles Powell, Boris Ratchev, Srinivas Reddy, Jay Schleicher, Kevin Stevens, Richard Yuan, Richard Cliff, Jonathan Rose: The Stratix II logic and routing architecture. FPGA 2005: 14-20
2004
28EEMichael Hutton, Jay Schleicher, David M. Lewis, Bruce Pedersen, Richard Yuan, Sinan Kaptanoglu, Gregg Baeckler, Boris Ratchev, Ketan Padalia, Mark Bourgeault, Andy Lee, Henry Kim, Rahul Saini: Improving FPGA Performance and Area Using an Adaptive Logic Module. FPL 2004: 135-144
2003
27EEDavid M. Lewis, Vaughn Betz, David Jefferson, Andy Lee, Christopher Lane, Paul Leventis, Sandy Marquardt, Cameron McClintock, Bruce Pedersen, Giles Powell, Srinivas Reddy, Chris Wysocki, Richard Cliff, Jonathan Rose: The StratixTM routing and logic architecture. FPGA 2003: 12-20
2002
26EEGuy G. Lemieux, David M. Lewis: Circuit design of routing switches. FPGA 2002: 19-28
25EEGuy G. Lemieux, David M. Lewis: Analytical Framework for Switch Block Design. FPL 2002: 122-131
2001
24EEGuy G. Lemieux, David M. Lewis: Using sparse crossbars within LUT. FPGA 2001: 59-68
2000
23EEL. Louis Zhang, Qiang Wang, David M. Lewis: Design of a VLIW Compute Accelerator on the Transmogrifier-2. FCCM 2000: 3-12
22EEGuy G. Lemieux, Paul Leventis, David M. Lewis: Generating highly-routable sparse crossbars for PLDs. FPGA 2000: 155-164
1999
21EEAndy Gean Ye, David M. Lewis: Procedural Texture Mapping on FPGAs. FPGA 1999: 112-120
1998
20EEDavid M. Lewis, David R. Galloway, Marcus van Ierssel, Jonathan Rose, Paul Chow: The Transmogrifier-2: a 1 million gate rapid-prototyping system. IEEE Trans. VLSI Syst. 6(2): 188-198 (1998)
1997
19EEQiang Wang, David M. Lewis: Automated field-programmable compute accelerator design using partial evaluation. FCCM 1997: 145-154
18EEDavid M. Lewis, David R. Galloway, Marcus van Ierssel, Jonathan Rose, Paul Chow: The Transmogrifier-2: A 1 Million Gate Rapid Prototyping System. FPGA 1997: 53-61
1996
17EEVi Cuong Chan, David M. Lewis: Area-Speed Tradeoffs for Hierarchical Field-Programmable Gate Arrays. FPGA 1996: 51-57
1994
16 Aditya A. Aggarwal, David M. Lewis: Routing Architectures for Hierarchical Field Programmable Gate Arrays. ICCD 1994: 475-478
15 David M. Lewis: Interleaved Memory Function Interpolators with Application to an Accurate LNS Arithmetic Unit. IEEE Trans. Computers 43(8): 974-982 (1994)
1993
14 David M. Lewis, Marcus van Ierssel, Daniel H. Wong: A Field Programmable Accelerator for Compiled-Code Applications. ICCD 1993: 491-496
13EEDavid M. Lewis: An accurate LNS arithmetic unit using interleaved memory function interpolator. IEEE Symposium on Computer Arithmetic 1993: 2-9
12 David A. Johns, David M. Lewis, D. Cherepacha: Highly Selective "Analog" Filters Using Delta Sigma Based IIR Filtering. ISCAS 1993: 1302-1305
11EEAhmet N. Parlakbilek, David M. Lewis: A multiple-strength multiple-delay compiled-code logic simulator. IEEE Trans. on CAD of Integrated Circuits and Systems 12(12): 1937-1946 (1993)
1992
10EEDavid M. Lewis: A compiled-code hardware accelerator for circuit simulation. IEEE Trans. on CAD of Integrated Circuits and Systems 11(5): 555-565 (1992)
1991
9 Zvonko G. Vranesic, Michael Stumm, David M. Lewis, Ron White: Hector: A Hierarchically Structured Shared-memory Multiprocessor. IEEE Computer 24(1): 72-79 (1991)
8EEDavid M. Lewis: A hierarchical compiled code event-driven logic simulator. IEEE Trans. on CAD of Integrated Circuits and Systems 10(6): 726-737 (1991)
1990
7 Brian W. Thomson, E. Stewart Lee, Peter I. P. Boulton, Michael Stumm, David M. Lewis: Using Deducibility in Secure Network Modelling. ESORICS 1990: 117-123
6 David M. Lewis: An Architecture for Addition and Subtraction of Long Word Length Numbers in the Logarithmic Number System. IEEE Trans. Computers 39(11): 1325-1336 (1990)
5EEDavid M. Lewis: Device model approximation using 2N trees. IEEE Trans. on CAD of Integrated Circuits and Systems 9(1): 30-38 (1990)
1988
4EEDavid M. Lewis: A Programmable Hardware Accelerator for Compiled Electrical Simulation. DAC 1988: 172-177
3EEDavid M. Lewis: Hardware accelerators for timing simulation of VLSI digital circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 7(11): 1134-1149 (1988)
1986
2 David M. Lewis, David R. Galloway, Robert J. Francis, Brian W. Thomson: Swamp: A Fast Processor for Smalltalk-80. OOPSLA 1986: 131-139
1985
1EEDavid M. Lewis: A hardware engine for analogue mode simulation of MOS digital circuits. DAC 1985: 345-351

Coauthor Index

1Aditya A. Aggarwal [16]
2Elias Ahmed [29]
3Gregg Baeckler [28] [29]
4Vaughn Betz [27] [29]
5Peter I. P. Boulton [7]
6Mark Bourgeault [28] [29]
7David Cashman [29]
8Vi Cuong Chan [17]
9D. Cherepacha [12]
10Paul Chow [18] [20]
11Richard Cliff [27] [29]
12Robert J. Francis [2]
13David R. Galloway [2] [18] [20] [29]
14Michael Hutton (Michael D. Hutton, Mike Hutton) [28] [29]
15Marcus van Ierssel [14] [18] [20]
16David Jefferson [27]
17David A. Johns [12]
18Sinan Kaptanoglu [28]
19Henry Kim [28]
20Christopher Lane [27] [29]
21Andy Lee [27] [28] [29]
22E. Stewart Lee [7]
23Guy G. Lemieux [22] [24] [25] [26]
24Paul Leventis [22] [27] [29]
25Sandy Marquardt [27] [29]
26Cameron McClintock [27] [29]
27Ketan Padalia [28] [29]
28Ahmet N. Parlakbilek [11]
29Bruce Pedersen [27] [28] [29]
30Giles Powell [27] [29]
31Boris Ratchev [28] [29]
32Srinivas Reddy [27] [29]
33Jonathan Rose [18] [20] [27] [29]
34Rahul Saini [28]
35Jay Schleicher [28] [29]
36Kevin Stevens [29]
37Michael Stumm [7] [9]
38Brian W. Thomson [2] [7]
39Zvonko G. Vranesic [9]
40Qiang Wang [19] [23]
41Ron White [9]
42Daniel H. Wong [14]
43Chris Wysocki [27]
44Andy Gean Ye [21]
45Richard Yuan [28] [29]
46L. Louis Zhang [23]

Colors in the list of coauthors

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)