Régis Leveugle Vis

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61EERégis Leveugle, A. Calvez, Paolo Maistri, Pierre Vanhauwaert: Statistical fault injection: Quantified error and confidence. DATE 2009: 502-506
60EEPaolo Maistri, Régis Leveugle: Double-Data-Rate Computation as a Countermeasure against Fault Analysis. IEEE Trans. Computers 57(11): 1528-1539 (2008)
59EERégis Leveugle, Abdelaziz Ammari, V. Maingot, E. Teyssou, Pascal Moitrel, Christophe Mourtel, Nathalie Feyt, Jean-Baptiste Rigaud, Assia Tria: Experimental evaluation of protections against laser-induced faults and consequences on fault modeling. DATE 2007: 1587-1592
58EEMichele Portolan, Régis Leveugle: Effective Checkpoint and Rollback Using Hardware/OS Collaboration. DFT 2007: 370-378
57EEPaolo Maistri, Pierre Vanhauwaert, Régis Leveugle: Evaluation of Register-Level Protection Techniques for the Advanced Encryption Standard by Multi-Level Fault Injections. DFT 2007: 499-507
56EEPaolo Maistri, Pierre Vanhauwaert, Régis Leveugle: A Novel Double-Data-Rate AES Architecture Resistant against Fault Injection. FDTC 2007: 54-61
55EEYannick Monnet, Marc Renaudin, Régis Leveugle: Formal Analysis of Quasi Delay Insensitive Circuits Behavior in the Presence of SEUs. IOLTS 2007: 113-120
54EERégis Leveugle: Early Analysis of Fault-based Attack Effects in Secure Circuits. IEEE Trans. Computers 56(10): 1431-1434 (2007)
53 Régis Leveugle, V. Maingot: On the Use of Information Redundancy When Designing Secure Chips. DDECS 2006: 141-142
52 Pierre Vanhauwaert, Régis Leveugle, Philippe Roche: A Flexible SoPC-based Fault Injection Environment. DDECS 2006: 192-197
51EEAbdelaziz Ammari, Régis Leveugle, B. Nicolescu, Yvon Savaria: Evaluation of a Software-Based Error Detection Technique by RT-Level Fault Injection. DELTA 2006: 488-493
50EEYannick Monnet, Marc Renaudin, Régis Leveugle, Christophe Clavier, Pascal Moitrel: Case Study of a Fault Attack on Asynchronous DES Crypto-Processors. FDTC 2006: 88-97
49EEYannick Monnet, Marc Renaudin, Régis Leveugle, Nathalie Feyt, Pascal Moitrel, F. M'Buwa Nzenguet: Practical Evaluation of Fault Countermeasures on an Asynchronous DES Crypto Processor. IOLTS 2006: 125-130
48EEPierre Vanhauwaert, Régis Leveugle, Philippe Roche: Reduced Instrumentation and Optimized Fault Injection Control for Dependability Analysis. VLSI-SoC 2006: 391-396
47EEYannick Monnet, Marc Renaudin, Régis Leveugle: Designing Resistant Circuits against Malicious Faults Injection Using Asynchronous Logic. IEEE Trans. Computers 55(9): 1104-1115 (2006)
46EEYannick Monnet, Marc Renaudin, Régis Leveugle: Asynchronous circuits transient faults sensitivity evaluation. DAC 2005: 863-868
45EEMichele Portolan, Régis Leveugle: Towards a Secure and Reliable System. EUC 2005: 1085-1098
44EERégis Leveugle: Introduction to the Special Session on Secure Implementations. IOLTS 2005: 115
43EEYannick Monnet, Marc Renaudin, Régis Leveugle: Hardening Techniques against Transient Faults for Asynchronous Circuits. IOLTS 2005: 129-134
42EERégis Leveugle, Yervant Zorian, Luca Breveglieri, André K. Nieuwland, Klaus Rothbart, Jean-Pierre Seifert: On-Line Testing for Secure Implementations: Design and Validation. IOLTS 2005: 211
41EEMichele Portolan, Régis Leveugle: On the Need for Common Evaluation Methods for Fault Tolerance Costs in Microprocessors. IOLTS 2005: 247-252
40EERégis Leveugle: A New Approach for Early Dependability Evaluation Based on Formal Property Checking and Controlled Mutations. IOLTS 2005: 260-265
39EELorena Anghel, Régis Leveugle, Pierre Vanhauwaert: Evaluation of SET and SEU Effects at Multiple Abstraction Levels. IOLTS 2005: 309-312
38EEAbdelaziz Ammari, K. Hadjiat, Régis Leveugle: Combined Fault Classification and Error Propagation Analysis to Refine RT-Level Dependability Evaluation. J. Electronic Testing 21(4): 365-376 (2005)
37EERégis Leveugle, Abdelaziz Ammari: Early SEU Fault Injection in Digital, Analog and Mixed Signal Circuits: A Global Flow. DATE 2004: 590-595
36EERégis Leveugle, D. Cimonnet, Abdelaziz Ammari: System-Level Dependability Analysis with RT-Level Fault Injection Accuracy. DFT 2004: 451-458
35EEYannick Monnet, Marc Renaudin, Régis Leveugle: Asynchronous Circuits Sensitivity to Fault Injection. IOLTS 2004: 121-128
34EEMichele Portolan, Régis Leveugle: Operating System Function Reuse to Achieve Low-Cost Fault Tolerance. IOLTS 2004: 167-174
33EEAbdelaziz Ammari, K. Hadjiat, Régis Leveugle: On Combining Fault Classification and Error Propagation Analysis in RT-Level Dependability Evaluation. IOLTS 2004: 227-232
32EEAbdelaziz Ammari, Régis Leveugle, Matteo Sonza Reorda, Massimo Violante: Detailed Comparison of Dependability Analyses Performed at RT and Gate Levels. DFT 2003: 336-343
31EERégis Leveugle, Lörinc Antoni, Béla Fehér: Dependability Analysis: A New Application for Run-Time Reconfiguration. IPDPS 2003: 173
30EERégis Leveugle, K. Hadjiat: Multi-Level Fault Injections in VHDL Descriptions: Alternative Approaches and Experiments. J. Electronic Testing 19(5): 559-575 (2003)
29EERégis Leveugle, Glenn H. Chapman: Special section on defect and fault tolerance in VLSI systems. Microelectronics Journal 34(1): 1 (2003)
28EERégis Leveugle: Automatic Modifications of High Level VHDL Descriptions for Fault Detection or Tolerance. DATE 2002: 837-841
27EELörinc Antoni, Régis Leveugle, Béla Fehér: Using Run-Time Reconfiguration for Fault Injection in Hardware Prototypes. DFT 2002: 245-253
26EERégis Leveugle, K. Hadjiat: Multi-Level Fault Injection Experiments Based on VHDL Descriptions: A Case Study. IOLTW 2002: 107-111
25EERégis Leveugle: A Low-Cost Hardware Approach to Dependability Validation of Ips. DFT 2001: 242-249
24EERaoul Velazco, Régis Leveugle, O. Calvo: Upset-Like Fault Injection in VHDL Descriptions: A Method and Preliminary Results. DFT 2001: 259-
23EERégis Leveugle, R. Cercueil: High Level Modifications of VHDL Descriptions for On-Line Test or Fault Tolerance. DFT 2001: 84-
22EELörinc Antoni, Régis Leveugle, Béla Fehér: Using Run-Time Reconfiguration for Fault Injection in Hardware Prototypes. DFT 2000: 405-413
21EERégis Leveugle: Fault Injection in VHDL Descriptions and Emulation. DFT 2000: 414-
20EEAlejandro Chagoya, Régis Leveugle: Experiments on Multimedia Support of VLSI Design teaching in the MODEM Project. MSE 1999: 82-83
19EEX. Wendling, H. Chauvet, Lionel Revéret, R. Rochet, Régis Leveugle: Automatic and Optimized Synthesis of Dataparts with Fault Detection or Tolerance Capabilities. DFT 1997: 195-203
18EEX. Wendling, R. Rochet, Régis Leveugle: Standard and ROM-based synthesis of FSMs with control flow checking capabilities. VTS 1996: 81-86
17 Régis Leveugle, R. Rochet, Gabriele Saucier: Alternative Approaches to Fault Detection in FSMs. DFT 1994: 271-279
16 T. Michel, Régis Leveugle, Gabriele Saucier, R. Doucet, P. Chapier: Taking Advantage of ASICs to Improve Dependability with Very Low Overheads. EDAC-ETC-EUROASIC 1994: 14-18
15 C. Safinia, Régis Leveugle, Gabriele Saucier: Taking Advantage of High Level Functional Information to Refine Timing Analysis and Timing Modeling. EDAC-ETC-EUROASIC 1994: 349-353
14 Régis Leveugle, Zahava Koren, Israel Koren, Gabriele Saucier, Norbert Wehn: The Hyeti Defect Tolerant Microprocessor: A Practical Experiment and its Cost-Effectiveness Analysis. IEEE Trans. Computers 43(12): 1398-1406 (1994)
13EERégis Leveugle: Optimized State Assignment of single fault Tolerant FSMs Based on SEC Codes. DAC 1993: 14-18
12 R. Rochet, Régis Leveugle, Gabriele Saucier: Analysis and Comparison of Fault Tolerant FSM Architectures Based on SEC Codes. DFT 1993: 9-16
11 Régis Leveugle, R. Rochet, Gabriele Saucier, L. Martinez, C. Pitot: A Synthesis Tool for Fault-Tolerant Finite State Machines. FTCS 1993: 502-511
10 Régis Leveugle, X. Delord, Gabriele Saucier: Influence of Error Correlations on the Signature Analysis Aliasing. ICCD 1993: 584-587
9 Régis Leveugle: Test of single fault tolerant controllers in VLSI circuits. VLSI 1993: 123-132
8 Régis Leveugle, C. Safina: Generation of optimized datapaths: bit-slice versus standard cells. Synthesis for Control Dominated Circuits 1992: 153-166
7 C. Safina, Régis Leveugle: Clocking scheme selection for circuits made up of a controller and a datapath. Synthesis for Control Dominated Circuits 1992: 293-308
6 Pierre Abouzeid, Régis Leveugle, Gabriele Saucier: Logic Synthesis for Automatic Layout. Synthesis for Control Dominated Circuits 1992: 335-343
5 L. Gerbaux, Régis Leveugle, Gabriele Saucier: Synthesis of large controllers using ROM or PLA generators. Synthesis for Control Dominated Circuits 1992: 47-59
4 T. Michel, Régis Leveugle, Gabriele Saucier: A New Approach to Control Flow Checking Without Program Modification. FTCS 1991: 334-343
3 Margot Karam, Régis Leveugle, Gabriele Saucier: Hierarchical Test Generation Based on Delayed Propagation. ITC 1991: 739-747
2 Régis Leveugle, Gabriele Saucier: Optimized Synthesis of Concurrently Checked Controllers. IEEE Trans. Computers 39(4): 419-425 (1990)
1 Régis Leveugle, Gabriele Saucier: Optimized Synthesis of Dedicated Controllers with Concurrent Checking Capabilities. ITC 1989: 355-363

Coauthor Index

1Pierre Abouzeid [6]
2Abdelaziz Ammari [32] [33] [36] [37] [38] [51] [59]
3Lorena Anghel [39]
4Lörinc Antoni [22] [27] [31]
5Luca Breveglieri [42]
6A. Calvez [61]
7O. Calvo [24]
8R. Cercueil [23]
9Alejandro Chagoya [20]
10P. Chapier [16]
11Glenn H. Chapman [29]
12H. Chauvet [19]
13D. Cimonnet [36]
14Christophe Clavier [50]
15X. Delord [10]
16R. Doucet [16]
17Béla Fehér [22] [27] [31]
18Nathalie Feyt [49] [59]
19L. Gerbaux [5]
20K. Hadjiat [26] [30] [33] [38]
21Margot Karam [3]
22Israel Koren [14]
23Zahava Koren [14]
24V. Maingot [53] [59]
25Paolo Maistri [56] [57] [60] [61]
26L. Martinez [11]
27T. Michel [4] [16]
28Pascal Moitrel [49] [50] [59]
29Yannick Monnet [35] [43] [46] [47] [49] [50] [55]
30Christophe Mourtel [59]
31B. Nicolescu [51]
32André K. Nieuwland [42]
33F. M'Buwa Nzenguet [49]
34C. Pitot [11]
35Michele Portolan [34] [41] [45] [58]
36Marc Renaudin [35] [43] [46] [47] [49] [50] [55]
37Matteo Sonza Reorda [32]
38Lionel Revéret [19]
39Jean-Baptiste Rigaud [59]
40Philippe Roche [48] [52]
41R. Rochet [11] [12] [17] [18] [19]
42Klaus Rothbart [42]
43C. Safina [7] [8]
44C. Safinia [15]
45Gabriele Saucier [1] [2] [3] [4] [5] [6] [10] [11] [12] [14] [15] [16] [17]
46Yvon Savaria [51]
47Jean-Pierre Seifert [42]
48E. Teyssou [59]
49Assia Tria [59]
50Pierre Vanhauwaert [39] [48] [52] [56] [57] [61]
51Raoul Velazco [24]
52Massimo Violante [32]
53Norbert Wehn [14]
54X. Wendling [18] [19]
55Yervant Zorian [42]

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Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)