Guy G. Lemieux Vis

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21EEJohnny Tsung Lin Ho, Guy G. Lemieux: PERG-Rx: a hardware pattern-matching engine supporting limited regular expressions. FPGA 2009: 257-260
20EEPaul Teehan, Guy G. Lemieux, Mark R. Greenstreet: Towards reliable 5Gbps wave-pipelined and 3Gbps surfing interconnect in 65nm FPGAs. FPGA 2009: 43-52
19EEGuy G. Lemieux, Tarek A. El-Ghazawi: Designing with extreme parallelism. FPGA 2008: 1-2
18EETarek A. El-Ghazawi, Guy G. Lemieux: Extreme parallel architectures for the masses. FPGA 2008: 127-128
17EEJulien Lamoureux, Guy G. Lemieux, Steven J. E. Wilton: GlitchLess: Dynamic Power Minimization in FPGAs Through Edge Alignment and Glitch Filtering. IEEE Trans. VLSI Syst. 16(11): 1521-1534 (2008)
16EEDavid Grant, Guy G. Lemieux: Perturb+mutate: Semisynthetic circuit generation for incremental placement and routing. TRETS 1(3): (2008)
15EEJulien Lamoureux, Guy G. Lemieux, Steven J. E. Wilton: GlitchLess: an active glitch minimization technique for FPGAs. FPGA 2007: 156-165
14EEDavid Yeager, Darius Chiu, Guy G. Lemieux: Congestion estimation and localization in FPGAS: a visual tool for interconnect prediction. SLIP 2007: 33-40
13EEPaul Teehan, Mark R. Greenstreet, Guy G. Lemieux: A Survey and Taxonomy of GALS Design Styles. IEEE Design & Test of Computers 24(5): 418-428 (2007)
12EEDavid Grant, Scott Chin, Guy G. Lemieux: Semi-Synthetic Circuit Generation Using Graph Monomorphism for Testing Incremental Placement and Incremental Routing Tools. FPL 2006: 1-4
11EEMarvin Tom, David Leong, Guy G. Lemieux: Un/DoPack: re-clustering of large system-on-chip designs with interconnect variation for low-cost FPGAs. ICCAD 2006: 680-687
10EEMarvin Tom, Guy G. Lemieux: Logic block clustering of large designs for channel-width constrained FPGAs. DAC 2005: 726-731
9 Anthony J. Yu, Guy G. Lemieux: Defect-Tolerant FPGA Switch Block and Connection Block with Fine-Grain Redundancy for Yield Enhancement. FPL 2005: 255-262
8 Anthony J. Yu, Guy G. Lemieux: FPGA Defect Tolerance: Impact of Granularity. FPT 2005: 189-196
7EEGuy G. Lemieux, David M. Lewis: Circuit design of routing switches. FPGA 2002: 19-28
6EEGuy G. Lemieux, David M. Lewis: Analytical Framework for Switch Block Design. FPL 2002: 122-131
5EEGuy G. Lemieux, David M. Lewis: Using sparse crossbars within LUT. FPGA 2001: 59-68
4EEGuy G. Lemieux, Paul Leventis, David M. Lewis: Generating highly-routable sparse crossbars for PLDs. FPGA 2000: 155-164
3EER. Grindley, Tarek S. Abdelrahman, Stephen Dean Brown, S. Caranci, D. DeVries, Benjamin Gamsa, A. Grbic, M. Gusat, R. Ho, Orran Krieger, Guy G. Lemieux, K. Loveless, Naraig Manjikian, P. McHardy, Sinisa Srbljic, Michael Stumm, Zvonko G. Vranesic, Zeljko Zilic: The NUMAchine Multiprocessor. ICPP 2000: 487-496
2EEA. Grbic, Stephen Dean Brown, S. Caranci, R. Grindley, M. Gusat, Guy G. Lemieux, K. Loveless, Naraig Manjikian, Sinisa Srbljic, Michael Stumm, Zvonko G. Vranesic, Zeljko Zilic: Design and Implementation of the NUMAchine Multiprocessor. DAC 1998: 66-69
1EEGuy G. Lemieux, Stephen Dean Brown, Daniel Vranesic: On two-step routing for FPGAS. ISPD 1997: 60-66

Coauthor Index

1Tarek S. Abdelrahman [3]
2Stephen Dean Brown [1] [2] [3]
3S. Caranci [2] [3]
4Scott Chin [12]
5Darius Chiu [14]
6D. DeVries [3]
7Tarek A. El-Ghazawi [18] [19]
8Benjamin Gamsa [3]
9David Grant [12] [16]
10A. Grbic [2] [3]
11Mark R. Greenstreet [13] [20]
12R. Grindley [2] [3]
13M. Gusat [2] [3]
14Johnny Tsung Lin Ho [21]
15R. Ho [3]
16Orran Krieger [3]
17Julien Lamoureux [15] [17]
18David Leong [11]
19Paul Leventis [4]
20David M. Lewis [4] [5] [6] [7]
21K. Loveless [2] [3]
22Naraig Manjikian [2] [3]
23P. McHardy [3]
24Sinisa Srbljic [2] [3]
25Michael Stumm [2] [3]
26Paul Teehan [13] [20]
27Marvin Tom [10] [11]
28Daniel Vranesic [1]
29Zvonko G. Vranesic [2] [3]
30Steven J. E. Wilton [15] [17]
31David Yeager [14]
32Anthony J. Yu [8] [9]
33Zeljko Zilic [2] [3]

Colors in the list of coauthors

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)