Miriam Leeser Vis

*	2009
66		David R. Kaeli, Miriam Leeser: Proceedings of 2nd Workshop on General Purpose Processing on Graphics Processing Units, GPGPU 2009, Washington, DC, USA, March 8, 2009 ACM 2009
65	EE	Abderrahmane Bennis, Miriam Leeser, Gilead Tadmor: Implementing a Highly Parameterized Digital PIV System on Reconfigurable Hardware. ASAP 2009: 32-37
64	EE	Perhaad Mistry, Sherman Braganza, David R. Kaeli, Miriam Leeser: Accelerating phase unwrapping and affine transformations for optical quadrature microscopy using CUDA. GPGPU 2009: 28-37
	2008
63	EE	Sherman Braganza, Miriam Leeser: An efficient implementation of a phase unwrapping kernel on reconfigurable hardware. ASAP 2008: 138-143
62	EE	Mary Ellen Fuess, Miriam Leeser, Tim Leonard: An FPGA Implementation of Explicit-State Model Checking. FCCM 2008: 119-126
61	EE	Sherman Braganza, Miriam Leeser: An Efficient Implementation of a Phase Unwrapping Kernel on Reconfigurable Hardware. FCCM 2008: 316-317
60	EE	Xiaojun Wang, Miriam Leeser: Efficient FPGA implementation of qr decomposition using a systolic array architecture. FPGA 2008: 260
59	EE	Joshua Noseworthy, Miriam Leeser: Efficient Communication Between the Embedded Processor and the Reconfigurable Logic on an FPGA. IEEE Trans. VLSI Syst. 16(8): 1083-1090 (2008)
58	EE	David R. Kaeli, Miriam Leeser: Special issue: General-purpose processing using graphics processing units. J. Parallel Distrib. Comput. 68(10): 1305-1306 (2008)
57	EE	David R. Kaeli, Miriam Leeser: Acknowledgment to special issue reviewers. J. Parallel Distrib. Comput. 68(10): 1402 (2008)
	2007
56	EE	Sherman Braganza, Miriam Leeser: The 1D Discrete Cosine Transform For Large Point Sizes Implemented On Reconfigurable Hardware. ASAP 2007: 101-106
55	EE	Xiaojun Wang, Miriam Leeser: K-means Clustering for Multispectral Images Using Floating-Point Divide. FCCM 2007: 151-162
54	EE	Nicholas Moore, Albert Conti, Miriam Leeser, Laurie A. Smith King: Writing Portable Applications that Dynamically Bind at Run Time to Reconfigurable Hardware. FCCM 2007: 229-238
53	EE	Nicholas Moore, Albert Conti, Miriam Leeser, Laurie A. Smith King: Vforce: An Extensible Framework for Reconfigurable Supercomputing. IEEE Computer 40(3): 39-49 (2007)
	2006
52		Joshua Noseworthy, Miriam Leeser: Efficient Use of Communications Between an FPGAs Embedded Processor and its Reconfigurable Logic. ERSA 2006: 191-197
51	EE	Xiaojun Wang, Sherman Braganza, Miriam Leeser: Advanced Components in the Variable Precision Floating-Point Library. FCCM 2006: 249-258
50	EE	Haiqian Yu, Miriam Leeser: Automatic Sliding Window Operation Optimization for FPGA-Based. FCCM 2006: 76-88
49	EE	Joshua Noseworthy, Miriam Leeser: Efficient use of communications between an FPGA's embedded processor and its reconfigurable logic. FPGA 2006: 233
48	EE	Ben Cordes, Miriam Leeser, Eric Miller, Richard W. Linderman: Poster reception - Improving the performance of parallel backprojection on a reconfigurable supercomputer. SC 2006: 149
47	EE	Peter Soderquist, Miriam Leeser, Juan Carlos Rojas: Enabling MPEG-2 video playback in embedded systems through improved data cache efficiency. IEEE Transactions on Multimedia 8(1): 81-89 (2006)
	2005
46	EE	Ben Cordes, Jennifer G. Dy, Miriam Leeser, James Goebel: Enabling a RealTime Solution for Neuron Detection with Reconfigurable Hardware (abstract only). FPGA 2005: 264
45	EE	Ben Cordes, Jennifer G. Dy, Miriam Leeser, James Goebel: Enabling a Real-Time Solution for Neuron Detection with Reconfigurable Hardware. IEEE International Workshop on Rapid System Prototyping 2005: 128-134
44	EE	Miriam Leeser, Srdjan Coric, Eric Miller, Haiqian Yu, Marc Trepanier: Parallel-Beam Backprojection: An FPGA Implementation Optimized for Medical Imaging. VLSI Signal Processing 39(3): 295-311 (2005)
	2004
43		Laurie A. Smith King, Miriam Leeser, Heather Quinn: Dynamo: A Runtime Partitioning System. ERSA 2004: 145-154
42	EE	Miriam Leeser, Shawn Miller, Haiqian Yu: Smart Camera Based on Reconfigurable Hardware Enables Diverse Real-Time Applications. FCCM 2004: 147-155
41	EE	Wang Chen, Panos Kosmas, Miriam Leeser, Carey Rappaport: An FPGA implementation of the two-dimensional finite-difference time-domain (FDTD) algorithm. FPGA 2004: 213-222
	2003
40	EE	Juan Carlos Rojas, Miriam Leeser: Programming portable optimized multimedia applications. ACM Multimedia 2003: 291-294
39	EE	Heather Quinn, Laurie A. Smith King, Miriam Leeser, Waleed Meleis: Runtime Assignment of Reconfigurable Hardware Components for Image Processing Pipelines. FCCM 2003: 173-
	2002
38	EE	Srdjan Coric, Miriam Leeser, Eric Miller, Marc Trepanier: Parallel-beam backprojection: an FPGA implementation optimized for medical imaging. FPGA 2002: 217-226
37	EE	Pavle Belanovic, Miriam Leeser: A Library of Parameterized Floating-Point Modules and Their Use. FPL 2002: 657-666
	2001
36	EE	Mike Estlick, Miriam Leeser, James Theiler, John J. Szymanski: Algorithmic transformations in the implementation of K- means clustering on reconfigurable hardware. FPGA 2001: 103-110
35		Laurie A. Smith King, Heather Quinn, Miriam Leeser, Demetris G. Galatopoullos, Elias S. Manolakos: Run-Time Execution of Reconfigurable Hardware in a Java Environment. ICCD 2001: 380-387
34	EE	Silviu M. S. A. Chiricescu, Miriam Leeser, Mankuan Michael Vai: Design and analysis of a dynamically reconfigurable three-dimensional FPGA. IEEE Trans. VLSI Syst. 9(1): 186-196 (2001)
	2000
33	EE	Ali M. Shankiti, Miriam Leeser: Implementing a RAKE receiver for wireless communications on an FPGA-based computer system. FPGA 2000: 145-151
32	EE	Yanbing Li, Miriam Leeser: HML, a novel hardware description language and its translation to VHDL. IEEE Trans. VLSI Syst. 8(1): 1-8 (2000)
31	EE	Shantanu Tarafdar, Miriam Leeser: A data-centric approach to high-level synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 19(11): 1251-1267 (2000)
	1998
30	EE	Shantanu Tarafdar, Miriam Leeser: The DT-Model: High-Level Synthesis Using Data Transfers. DAC 1998: 114-117
29	EE	Goran Doncev, Miriam Leeser, Shantanu Tarafdar: High Level Synthesis for Designing Custom Computing Hardware. FCCM 1998: 326-328
28	EE	Shantanu Tarafdar, Miriam Leeser, Zixin Yin: Integrating floorplanning in data-transfer based high-level synthesis. ICCAD 1998: 412-417
27	EE	Goran Doncev, Miriam Leeser, Shantanu Tarafdar: Truly Rapid Prototyping Requires High-Level Synthesis. International Workshop on Rapid System Prototyping 1998: 101-
26	EE	Miriam Leeser, Waleed Meleis, Mankuan Michael Vai, Silviu M. S. A. Chiricescu, Weidong Xu, Paul M. Zavracky: Rothko: A Three-Dimensional FPGA. IEEE Design & Test of Computers 15(1): 16-23 (1998)
	1997
25	EE	Peter Soderquist, Miriam Leeser: Optimizing the Data Cache Performance of a Software MPEG-2 Video Decoder. ACM Multimedia 1997: 291-301
24	EE	Waleed Meleis, Miriam Leeser, Paul M. Zavracky, Mankuan Michael Vai: Architectural Design of a Three Dimensional FPGA. ARVLSI 1997: 256-269
23		Miriam Leeser, Waleed Meleis, Mankuan Michael Vai, Paul M. Zavracky: Rothko: A three dimensional FPGA architecture, its fabrication, and design tools. FPL 1997: 21-30
22		Peter Soderquist, Miriam Leeser: Memory Traffic and Data Cache Behavior of an MPEG-2 Software Decoder. ICCD 1997: 417-422
	1996
21		Peter Soderquist, Miriam Leeser: Area and Performance Tradeoffs in Floating-Point Divide and Square-Root Implementations. ACM Comput. Surv. 28(3): 518-564 (1996)
	1995
20	EE	Miriam Leeser, John W. O'Leary: Verification of a subtractive radix-2 square root algorithm and implementation. ICCD 1995: 526-531
19	EE	Peter Soderquist, Miriam Leeser: An Area/Performance Comparison of Subtractive and Multiplicative Divide/Square Root Implementations. IEEE Symposium on Computer Arithmetic 1995: 132-139
18		Andrés Takach, Wayne Wolf, Miriam Leeser: An Automaton Model for Scheduling Constraints in Synchronous Machines. IEEE Trans. Computers 44(1): 1-12 (1995)
17	EE	Mark Aagaard, Miriam Leeser: Verifying a Logic-Synthesis Algorithm and Implementation: A Case Study in Software Verification. IEEE Trans. Software Eng. 21(10): 822-833 (1995)
	1994
16	EE	Mark H. Linderman, Miriam Leeser: Simulation of digital circuits in the presence of uncertainty. ICCAD 1994: 248-251
15		Mark Aagaard, Miriam Leeser: Reasoning About Pipelines with Structural Hazards. TPCD 1994: 13-32
14		John W. O'Leary, Miriam Leeser, Jason Hickey, Mark Aagaard: Non-Restoring Integer Square Root: A Case Study in Design by Principled Optimization. TPCD 1994: 52-71
13		Mark Aagaard, Miriam Leeser: A Methodology for Efficient Hardware Verification. Formal Methods in System Design 5(1/2): 95-117 (1994)
12	EE	Mark Aagaard, Miriam Leeser: PBS: proven Boolean simplification. IEEE Trans. on CAD of Integrated Circuits and Systems 13(4): 459-470 (1994)
	1993
11		John W. O'Leary, Mark H. Linderman, Miriam Leeser, Mark Aagaard: HML: A Hardware Description Language Based on Standard ML. CHDL 1993: 327-334
10	EE	Mark Aagaard, Miriam Leeser, Phillip J. Windley: Toward a Super Duper Hardware Tactic. HUG 1993: 399-412
9		Mark Aagaard, Miriam Leeser: A Framework for Specifying and Designing Pipelines. ICCD 1993: 548-551
8	EE	Miriam Leeser, Richard Chapman, Mark Aagaard, Mark H. Linderman, Stephan Meier: High level synthesis and generating FPGAs with the BEDROC system. VLSI Signal Processing 6(2): 191-214 (1993)
7	EE	Miriam Leeser: High level synthesis and generation FPGAs with the BEDROC system. VLSI Signal Processing 6(3): 7 (1993)
	1992
6	EE	Mark Aagaard, Miriam Leeser: Verifying a Logic Synthesis Tool in Nuprl: A Case Study in Software Verification. CAV 1992: 69-81
5		Mark Aagaard, Miriam Leeser: A Methodology for Reusable Hardware Proofs. TPHOLs 1992: 177-196
	1991
4		Mark Aagaard, Miriam Leeser: A Formally Verified System for Logic Synthesis. ICCD 1991: 346-350
	1990
3		Miriam Leeser, Geoffrey Brown: Hardware Specification, Verification and Synthesis: Mathematical Aspects, Mathematical Science Institute Workshop, Cornall University, Ithaca, New York, USA, July 5-7, 1989, Proceedings Springer 1990
	1989
2	EE	Geoffrey M. Brown, Miriam Leeser: From Programs to Transistors: Verifying Hardware Synthesis Tools. Hardware Specification, Verification and Synthesis 1989: 129-151
1	EE	Miriam Leeser: Reasoning about the function and timing of integrated circuits with interval temporal logic. IEEE Trans. on CAD of Integrated Circuits and Systems 8(12): 1233-1246 (1989)

Coauthor Index

1	Mark Aagaard	[4] [5] [6] [8] [9] [10] [11] [12] [13] [14] [15] [17]
2	Pavle Belanovic	[37]
3	Abderrahmane Bennis	[65]
4	Sherman Braganza	[51] [56] [61] [63] [64]
5	Geoffrey Brown	[3]
6	Geoffrey M. Brown	[2]
7	Richard Chapman	[8]
8	Wang Chen	[41]
9	Silviu M. S. A. Chiricescu	[26] [34]
10	Albert Conti	[53] [54]
11	Ben Cordes	[45] [46] [48]
12	Srdjan Coric	[38] [44]
13	Goran Doncev	[27] [29]
14	Jennifer G. Dy	[45] [46]
15	Mike Estlick	[36]
16	Mary Ellen Fuess	[62]
17	Demetris G. Galatopoullos	[35]
18	James Goebel	[45] [46]
19	Jason Hickey	[14]
20	David R. Kaeli	[57] [58] [64] [66]
21	Laurie A. Smith King	[35] [39] [43] [53] [54]
22	Panos Kosmas	[41]
23	Tim Leonard	[62]
24	Yanbing Li	[32]
25	Mark H. Linderman	[8] [11] [16]
26	Richard W. Linderman	[48]
27	Elias S. Manolakos	[35]
28	Stephan Meier	[8]
29	Waleed Meleis	[23] [24] [26] [39]
30	Eric Miller	[38] [44] [48]
31	Shawn Miller	[42]
32	Perhaad Mistry	[64]
33	Nicholas Moore	[53] [54]
34	Joshua Noseworthy	[49] [52] [59]
35	John W. O'Leary	[11] [14] [20]
36	Heather Quinn	[35] [39] [43]
37	Carey Rappaport	[41]
38	Juan Carlos Rojas	[40] [47]
39	Ali M. Shankiti	[33]
40	Peter Soderquist	[19] [21] [22] [25] [47]
41	John J. Szymanski	[36]
42	Gilead Tadmor	[65]
43	Andrés Takach	[18]
44	Shantanu Tarafdar	[27] [28] [29] [30] [31]
45	James Theiler	[36]
46	Marc Trepanier	[38] [44]
47	Mankuan Michael Vai	[23] [24] [26] [34]
48	Xiaojun Wang	[51] [55] [60]
49	Phillip J. Windley	[10]
50	Wayne Wolf	[18]
51	Weidong Xu	[26]
52	Zixin Yin	[28]
53	Haiqian Yu	[42] [44] [50]
54	Paul M. Zavracky	[23] [24] [26]

Colors in the list of coauthors