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Jens Leenstra Vis

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*2008
11EEMelanie Elm, Hans-Joachim Wunderlich, Michael E. Imhof, Christian G. Zoellin, Jens Leenstra, Nicolas Mäding: Scan chain clustering for test power reduction. DAC 2008: 828-833
2007
10EEMichael E. Imhof, Christian G. Zoellin, Hans-Joachim Wunderlich, Nicolas Mäding, Jens Leenstra: Scan Test Planning for Power Reduction. DAC 2007: 521-526
9EEBrian K. Flachs, Shigehiro Asano, Sang H. Dhong, H. Peter Hofstee, Gilles Gervais, Roy Kim, Tien Le, Peichun Liu, Jens Leenstra, John S. Liberty, Brad W. Michael, Hwa-Joon Oh, Silvia M. Müller, Osamu Takahashi, Koji Hirairi, Atsushi Kawasumi, Hiroaki Murakami, Hiromi Noro, Shoji Onishi, Juergen Pille, Joel Silberman, Suksoon Yong, Akiyuki Hatakeyama, Yukio Watanabe, Naoka Yano, Daniel A. Brokenshire, Mohammad Peyravian, VanDung To, Eiji Iwata: Microarchitecture and implementation of the synergistic processor in 65-nm and 90-nm SOI. IBM Journal of Research and Development 51(5): 529-544 (2007)
8EELee Eisen, John Wesley Ward III, Hans-Werner Tast, Nicolas Mäding, Jens Leenstra, Silvia M. Müller, Christian Jacobi, Jochen Preiss, Eric M. Schwarz, Steven R. Carlough: IBM POWER6 accelerators: VMX and DFU. IBM Journal of Research and Development 51(6): 663-684 (2007)
7EEJoachim Fenkes, Tobias Gemmeke, Jens Leenstra: Efficiency of Low Power Circuit Techniques in a 65 nm SOI-Process. J. Low Power Electronics 3(1): 54-59 (2007)
2006
6EENicolas Mäding, Jens Leenstra, Juergen Pille, R. Sautter, S. Büttner, S. Ehrenreich, W. Haller: The vector fixed point unit of the synergistic processor element of the cell architecture processor. DATE Designers' Forum 2006: 244-248
2001
5 Michael Kessler, Gundolf Kiefer, Jens Leenstra, Knut Schünemann, Thomas Schwarz, Hans-Joachim Wunderlich: Using a hierarchical DfT methodology in high frequency processor designs for improved delay fault testability. ITC 2001: 461-469
2000
4EEDavid H. Allen, Sang H. Dhong, H. Peter Hofstee, Jens Leenstra, Kevin J. Nowka, Daniel L. Stasiak, Dieter F. Wendel: Custom circuit design as a driver of microprocessor performance. IBM Journal of Research and Development 44(6): 799-822 (2000)
1997
3EEJörg A. Walter, Jens Leenstra, Gerhard Döttling, Bernd Leppla, Hans-Jürgen Münster, Kevin W. Kark, Bruce Wile: Hierarchical Random Simulation Approach for the Verification of S/390 CMOS Multiprocessors. DAC 1997: 89-94
1991
2 Jens Leenstra, Lambert Spaanenburg: Hierarchical Test Program Development for Scan Testable Circuits. ITC 1991: 375-384
1989
1 Jens Leenstra, Lambert Spaanenburg: On the Design and Test of Asynchronous Macros Embedded in Synchronous Systems. ITC 1989: 838-845

Coauthor Index

1David H. Allen [4]
2Shigehiro Asano [9]
3Daniel A. Brokenshire [9]
4S. Büttner [6]
5Steven R. Carlough [8]
6Sang H. Dhong [4] [9]
7Gerhard Döttling [3]
8S. Ehrenreich [6]
9Lee Eisen [8]
10Melanie Elm [11]
11Joachim Fenkes [7]
12Brian K. Flachs [9]
13Tobias Gemmeke [7]
14Gilles Gervais [9]
15W. Haller [6]
16Akiyuki Hatakeyama [9]
17Koji Hirairi [9]
18H. Peter Hofstee [4] [9]
19Michael E. Imhof [10] [11]
20Eiji Iwata [9]
21Christian Jacobi [8]
22Kevin W. Kark [3]
23Atsushi Kawasumi [9]
24Michael Kessler [5]
25Gundolf Kiefer [5]
26Roy Kim [9]
27Tien Le [9]
28Bernd Leppla [3]
29John S. Liberty [9]
30Peichun Liu [9]
31Nicolas Mäding [6] [8] [10] [11]
32Brad W. Michael [9]
33Silvia M. Müller [8] [9]
34Hans-Jürgen Münster [3]
35Hiroaki Murakami [9]
36Hiromi Noro [9]
37Kevin J. Nowka [4]
38Hwa-Joon Oh [9]
39Shoji Onishi [9]
40Mohammad Peyravian [9]
41Juergen Pille [6] [9]
42Jochen Preiss [8]
43R. Sautter [6]
44Knut Schünemann [5]
45Eric M. Schwarz [8]
46Thomas Schwarz [5]
47Joel Silberman [9]
48Lambert Spaanenburg [1] [2]
49Daniel L. Stasiak [4]
50Osamu Takahashi [9]
51Hans-Werner Tast [8]
52VanDung To [9]
53Jörg A. Walter [3]
54John Wesley Ward III [8]
55Yukio Watanabe [9]
56Dieter F. Wendel [4]
57Bruce Wile [3]
58Hans-Joachim Wunderlich [5] [10] [11]
59Naoka Yano [9]
60Suksoon Yong [9]
61Christian G. Zoellin [10] [11]

Colors in the list of coauthors

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)