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Roy Lane Vis

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*2002
1EEJoel Grodstein, Rachid Rayess, Tad Truex, Linda Shattuck, Sue Lowell, Dan Bailey, David Bertucci, Gabriel P. Bischoff, Daniel E. Dever, Mike Gowan, Roy Lane, Brian Lilly, Krishna Nagalla, Rahul Shah, Emily Shriver, Shi-Huang Yin, Shannon V. Morton: Power and CAD considerations for the 1.75mbyte, 1.2ghz L2 cache on the alpha 21364 CPU. ACM Great Lakes Symposium on VLSI 2002: 1-6

Coauthor Index

1Dan Bailey [1]
2David Bertucci [1]
3Gabriel P. Bischoff [1]
4Daniel E. Dever [1]
5Mike Gowan [1]
6Joel Grodstein [1]
7Brian Lilly [1]
8Sue Lowell [1]
9Shannon V. Morton [1]
10Krishna Nagalla [1]
11Rachid Rayess [1]
12Rahul Shah [1]
13Linda Shattuck [1]
14Emily Shriver [1]
15Tad Truex [1]
16Shi-Huang Yin [1]

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)