| * | 2009 |
|---|
| 11 | EE | Terrence S. T. Mak,
Peter Y. K. Cheung,
Wayne Luk,
Kai-Pui Lam:
A DP-network for optimal dynamic routing in network-on-chip.
CODES+ISSS 2009: 119-128 |
| 2007 |
|---|
| 10 | EE | Terrence S. T. Mak,
Kai-Pui Lam,
H. S. Ng,
G. Rachmuth,
C.-S. Poon:
A Current-Mode Analog Circuit for Reinforcement Learning Problems.
ISCAS 2007: 1301-1304 |
| 9 | EE | Terrence S. T. Mak,
N. Pete Sedcole,
Peter Y. K. Cheung,
Wayne Luk,
Kai-Pui Lam:
A Hybrid Analog-Digital Routing Network for NoC Dynamic Routing.
NOCS 2007: 173-182 |
| 2006 |
|---|
| 8 | EE | H. S. Ng,
Kai-Pui Lam:
How Does Sample Size Affect GARCH Models?
JCIS 2006 |
| 2004 |
|---|
| 7 | EE | Terrence S. T. Mak,
Kai-Pui Lam:
Embedded Computation of Maximum-Likelihood Phylogeny Inference Using Platform FPGA.
CSB 2004: 512-514 |
| 6 | EE | Terrence S. T. Mak,
Kai-Pui Lam:
FPGA-Based Computation for Maximum Likelihood Phylogenetic Tree Evaluation.
FPL 2004: 1076-1079 |
| 5 | EE | Terrence S. T. Mak,
Kai-Pui Lam:
On Computing Maximum Likelihood Phylogeny Using FPGA p.
FPL 2004: 1188 |
| 2003 |
|---|
| 4 | EE | Terrence S. T. Mak,
Kai-Pui Lam:
High Speed GAML-based Phylogenetic Tree Reconstruction Using HW/SW Codesign.
CSB 2003: 470-473 |
| 3 | EE | H. S. Ng,
Sui-Tung Mak,
Kai-Pui Lam:
Field programmable gate arrays and analog implementation of BRIN for optimization problems.
ISCAS (5) 2003: 73-76 |
| 2002 |
|---|
| 2 | EE | Kai-Pui Lam,
Sui-Tung Mak:
On Computing Transitive-Closure Equivalence Sets Using a Hybrid GA-DP Approach.
FPL 2002: 935-944 |
| 1 | EE | Ki Chan,
Boon Toh Low,
Wai Lam,
Kai-Pui Lam:
Extracting Causation Knowledge from Natural Language Texts.
PAKDD 2002: 555-560 |
