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Kanishka Lahiri Vis

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*2008
32EEKrishna Sekar, Kanishka Lahiri, Anand Raghunathan, Sujit Dey: Dynamically Configurable Bus Topologies for High-Performance On-Chip Communication. IEEE Trans. VLSI Syst. 16(10): 1413-1426 (2008)
2007
31EESaumya Chandra, Kanishka Lahiri, Anand Raghunathan, Sujit Dey: System-on-Chip Power Management Considering Leakage Power Variations. DAC 2007: 877-882
30EEMohammad Ali Ghodrat, Kanishka Lahiri, Anand Raghunathan: Accelerating System-on-Chip Power Analysis Using Hybrid Power Estimation. DAC 2007: 883-886
29EENikhil Bansal, Kanishka Lahiri, Anand Raghunathan: Automatic Power Modeling of Infrastructure IP for System-on-Chip Power Analysis. VLSI Design 2007: 513-520
28EENikil Dutt, Kaustav Banerjee, Luca Benini, Kanishka Lahiri, Sudeep Pasricha: Tutorial 5: SoC Communication Architectures: Technology, Current Practice, Research, and Trends. VLSI Design 2007: 8
2006
27EEBren Mochocki, Kanishka Lahiri, Srihari Cadambi, Xiaobo Sharon Hu: Signature-based workload estimation for mobile 3D graphics. DAC 2006: 592-597
26EEBren Mochocki, Kanishka Lahiri, Srihari Cadambi: Power analysis of mobile 3D graphics. DATE 2006: 502-507
25EEPhillip Stanley-Marbell, Kanishka Lahiri, Anand Raghunathan: Adaptive data placement in an embedded multiprocessor thread library. DATE 2006: 698-699
24EEKrishna Sekar, Kanishka Lahiri, Anand Raghunathan, Sujit Dey: Integrated data relocation and bus reconfiguration for adaptive system-on-chip platforms. DATE 2006: 728-733
23EESaumya Chandra, Kanishka Lahiri, Anand Raghunathan, Sujit Dey: Considering process variations during system-level power analysis. ISLPED 2006: 342-345
22EEKanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana: The LOTTERYBUS on-chip communication architecture. IEEE Trans. VLSI Syst. 14(6): 596-608 (2006)
2005
21EEAbhishek Mitra, Marcello Lajolo, Kanishka Lahiri: SOFTENIT: a methodology for boosting the software content of system-on-chip designs. ACM Great Lakes Symposium on VLSI 2005: 361-366
20EEKrishna Sekar, Kanishka Lahiri, Anand Raghunathan, Sujit Dey: FLEXBUS: a high-performance system-on-chip communication architecture with a dynamically configurable topology. DAC 2005: 571-574
19EENikhil Bansal, Kanishka Lahiri, Anand Raghunathan, Srimat T. Chakradhar: Power Monitors: A Framework for System-Level Power Estimation Using Heterogeneous Power Models. VLSI Design 2005: 579-585
2004
18EEKanishka Lahiri, Anand Raghunathan: Power analysis of system-level on-chip communication architectures. CODES+ISSS 2004: 236-241
17EEKrishna Sekar, Kanishka Lahiri, Sujit Dey: Configurable Platforms With Dynamic Platform Management: An Efficient Alternative to Application-Specific System-on-Chips. VLSI Design 2004: 307-
16EEKanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana, Sujit Dey: Design of high-performance system-on-chips using communication architecture tuners. IEEE Trans. on CAD of Integrated Circuits and Systems 23(5): 620-636 (2004)
15EEKanishka Lahiri, Anand Raghunathan, Sujit Dey: Efficient power profiling for battery-driven embedded system design. IEEE Trans. on CAD of Integrated Circuits and Systems 23(6): 919-932 (2004)
14EEKanishka Lahiri, Anand Raghunathan, Sujit Dey: Design space exploration for optimizing on-chip communication architectures. IEEE Trans. on CAD of Integrated Circuits and Systems 23(6): 952-961 (2004)
2003
13EEKrishna Sekar, Kanishka Lahiri, Sujit Dey: Dynamic Platform Management for Configurable Platform-Based System-on-Chips. ICCAD 2003: 641-649
2002
12EEKanishka Lahiri, Anand Raghunathan, Sujit Dey: Fast system-level power profiling for battery-efficient system design. CODES 2002: 157-162
11EEKanishka Lahiri, Sujit Dey, Anand Raghunathan: Communication architecture based power management for battery efficient system design. DAC 2002: 691-696
10EEKanishka Lahiri, Anand Raghunathan, Sujit Dey, Debashis Panigrahi: Embedded Tutorial: Battery-Driven System Design: A New Frontier in Low Power Design. VLSI Design 2002: 261-267
9EEKanishka Lahiri, Sujit Dey, Anand Raghunathan: Communication-Based Power Management. IEEE Design & Test of Computers 19(4): 118-130 (2002)
2001
8EEKanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana: LOTTERYBUS: A New High-Performance Communication Architecture for System-on-Chip Designs. DAC 2001: 15-20
7EEKanishka Lahiri, Sujit Dey, Anand Raghunathan: Evaluation of the Traffic-Performance Characteristics of System-on-Chip Communication Architectures. VLSI Design 2001: 29-35
6EEDebashis Panigrahi, Sujit Dey, Ramesh R. Rao, Kanishka Lahiri, Carla-Fabiana Chiasserini, Anand Raghunathan: Battery Life Estimation of Mobile Embedded Systems. VLSI Design 2001: 57-63
5EEKanishka Lahiri, Anand Raghunathan, Sujit Dey: System-level performance analysis for designing on-chipcommunication architectures. IEEE Trans. on CAD of Integrated Circuits and Systems 20(6): 768-783 (2001)
2000
4EEKanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana, Sujit Dey: Communication architecture tuners: a methodology for the design of high-performance communication architectures for systems-on-chips. DAC 2000: 513-518
3 Kanishka Lahiri, Anand Raghunathan, Sujit Dey: Efficient Exploration of the SoC Communication Architecture Design Space. ICCAD 2000: 424-430
2EEKanishka Lahiri, Sujit Dey, Anand Raghunathan: Performance Analysis of Systems with Multi-Channel Communication Architectures. VLSI Design 2000: 530-537
1999
1EEKanishka Lahiri, Anand Raghunathan, Sujit Dey: Fast performance analysis of bus-based system-on-chip communication architectures. ICCAD 1999: 566-573

Coauthor Index

1Kaustav Banerjee [28]
2Nikhil Bansal [19] [29]
3Luca Benini [28]
4Srihari Cadambi [26] [27]
5Srimat T. Chakradhar [19]
6Saumya Chandra [23] [31]
7Carla-Fabiana Chiasserini [6]
8Sujit Dey [1] [2] [3] [4] [5] [6] [7] [9] [10] [11] [12] [13] [14] [15] [16] [17] [20] [23] [24] [31] [32]
9Nikil D. Dutt (Nikil Dutt) [28]
10Mohammad Ali Ghodrat [30]
11Xiaobo Sharon Hu (Xiaobo Hu) [27]
12Marcello Lajolo [21]
13Ganesh Lakshminarayana [4] [8] [16] [22]
14Abhishek Mitra [21]
15Bren Mochocki [26] [27]
16Debashis Panigrahi [6] [10]
17Sudeep Pasricha [28]
18Anand Raghunathan [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [14] [15] [16] [18] [19] [20] [22] [23] [24] [25] [29] [30] [31] [32]
19Ramesh R. Rao [6]
20Krishna Sekar [13] [17] [20] [24] [32]
21Phillip Stanley-Marbell [25]

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)