Kimmo Kuusilinna Vis

*	2009
25	EE	Eero Aho, Jari Nikara, Petri A. Tuominen, Kimmo Kuusilinna: A case for multi-channel memories in video recording. DATE 2009: 934-939
	2008
24	EE	Jarno Vanne, Eero Aho, Timo D. Hämäläinen, Kimmo Kuusilinna: A Parallel Memory System for Variable Block-Size Motion Estimation Algorithms. IEEE Trans. Circuits Syst. Video Techn. 18(4): 538-543 (2008)
	2007
23	EE	Erno Salminen, Tero Kangas, Vesa Lahtinen, Jouni Riihimäki, Kimmo Kuusilinna, Timo D. Hämäläinen: Benchmarking mesh and hierarchical bus networks in system-on-chip context. Journal of Systems Architecture 53(8): 477-488 (2007)
22	EE	Eero Aho, Jarno Vanne, Timo D. Hämäläinen, Kimmo Kuusilinna: Configurable implementation of parallel memory based real-time video downscaler. Microprocessors and Microsystems 31(5): 283-292 (2007)
	2006
21	EE	Tero Kangas, Petri Kukkala, Heikki Orsila, Erno Salminen, Marko Hännikäinen, Timo D. Hämäläinen, Jouni Riihimäki, Kimmo Kuusilinna: UML-based multiprocessor SoC design framework. ACM Trans. Embedded Comput. Syst. 5(2): 281-320 (2006)
20	EE	Jarno Vanne, Eero Aho, Timo Hämäläinen, Kimmo Kuusilinna: A High-Performance Sum of Absolute Difference Implementation for Motion Estimation. IEEE Trans. Circuits Syst. Video Techn. 16(7): 876-883 (2006)
19	EE	Erno Salminen, Tero Kangas, Timo D. Hämäläinen, Jouni Riihimäki, Vesa Lahtinen, Kimmo Kuusilinna: HIBI Communication Network for System-on-Chip. VLSI Signal Processing 43(2-3): 185-205 (2006)
18	EE	Tero Kangas, Timo D. Hämäläinen, Kimmo Kuusilinna: Scalable Architecture for SoC Video Encoders. VLSI Signal Processing 44(1-2): 79-95 (2006)
	2005
17	EE	Eero Aho, Jarno Vanne, Kimmo Kuusilinna, Timo Hämäläinen: Block-level parallel processing for scaling evenly divisible frames. ISCAS (2) 2005: 1134-1137
16	EE	Erno Salminen, Tero Kangas, Jouni Riihimäki, Vesa Lahtinen, Kimmo Kuusilinna, Timo D. Hämäläinen: Benchmarking Mesh and Hierarchical Bus Networks in System-on-Chip Context. SAMOS 2005: 354-363
15	EE	Eero Aho, Jarno Vanne, Kimmo Kuusilinna, Timo D. Hämäläinen: Comments on "Winscale: an image-scaling algorithm using an area pixel Model". IEEE Trans. Circuits Syst. Video Techn. 15(3): 454-455 (2005)
	2004
14	EE	Erno Salminen, Vesa Lahtinen, Tero Kangas, Jouni Riihimäki, Kimmo Kuusilinna, Timo D. Hämäläinen: HIBI v.2 Communication Network for System-on-Chip. SAMOS 2004: 413-422
13	EE	Tero Kangas, Jouni Riihimäki, Erno Salminen, Vesa Lahtinen, Heikki Orsila, Kimmo Kuusilinna, Timo D. Hämäläinen: A Communication-Centric Design Flow for HIBI-Based SoCs. SAMOS 2004: 474-483
	2003
12	EE	Jouni Riihimäki, Väinö Helminen, Kimmo Kuusilinna, Timo D. Hämäläinen: Distributing SoC Simulations over a Network of Computers. DSD 2003: 447-450
11	EE	Chen Chang, Kimmo Kuusilinna, Brian C. Richards, Robert W. Brodersen: Implementation of BEE: a real-time large-scale hardware emulation engine. FPGA 2003: 91-99
10	EE	Chen Chang, Kimmo Kuusilinna, Brian C. Richards, Allen Chen, Nathan Chan, Robert W. Brodersen, Borivoje Nikolic: Rapid Design and Analysis of Communication Systems Using the BEE Hardware Emulation Environment. IEEE International Workshop on Rapid System Prototyping 2003: 148-
9	EE	Vesa Lahtinen, Erno Salminen, Kimmo Kuusilinna, Timo D. Hämäläinen: Comparison of synthesized bus and crossbar interconnection architectures. ISCAS (5) 2003: 433-436
	2002
8	EE	Jarno Vanne, Eero Aho, Kimmo Kuusilinna, Timo D. Hämäläinen: Enhanced Configurable Parallel Memory Architecture. DSD 2002: 28-37
7	EE	Tero Kangas, Kimmo Kuusilinna, Timo Hämäläinen: TDMA-based communication scheduling in system-on-chip video encoder. ISCAS (1) 2002: 369-372
6	EE	Vesa Lahtinen, Kimmo Kuusilinna, Timo Hämäläinen: Optimizing finite state machines for system-on-chip communication. ISCAS (1) 2002: 485-488
5	EE	Jouni Riihimäki, Erno Salminen, Kimmo Kuusilinna, Timo Hämäläinen: Parameter optimization tool for enhancing on-chip network performance. ISCAS (4) 2002: 61-64
4	EE	Kimmo Kuusilinna, Jarno K. Tanskanen, Timo Hämäläinen, Jarkko Niittylahti: Configurable parallel memory architecture for multimedia computers. Journal of Systems Architecture 47(14-15): 1089-1115 (2002)
3	EE	Vesa Lahtinen, Kimmo Kuusilinna, Tero Kangas, Timo Hämäläinen: Interconnection scheme for continuous-media systems-on-a-chip. Microprocessors and Microsystems 26(3): 123-138 (2002)
	2001
2	EE	Erno Salminen, Timo D. Hämäläinen, Tero Kangas, Kimmo Kuusilinna, Jukka Saarinen: Interfacing multiple processors in a system-on-chip video encoder. ISCAS (4) 2001: 478-481
	1999
1	EE	Kimmo Kuusilinna, Pasi Liimatainen, Timo Hämäläinen, Jukka Saarinen: Reconfiguration Mechanism for an IP Block Based Interconnection. EUROMICRO 1999: 1042-1045

Coauthor Index

1	Eero Aho	[8] [15] [17] [20] [22] [24] [25]
2	Robert W. Brodersen	[10] [11]
3	Nathan Chan	[10]
4	Chen Chang	[10] [11]
5	Allen Chen	[10]
6	Timo Hämäläinen (Timo D. Hämäläinen, Timo Sippala)	[1] [2] [3] [4] [5] [6] [7] [8] [9] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23] [24]
7	Marko Hännikäinen	[21]
8	Väinö Helminen	[12]
9	Tero Kangas	[2] [3] [7] [13] [14] [16] [18] [19] [21] [23]
10	Petri Kukkala	[21]
11	Vesa Lahtinen	[3] [6] [9] [13] [14] [16] [19] [23]
12	Pasi Liimatainen	[1]
13	Jarkko Niittylahti	[4]
14	Jari Nikara	[25]
15	Borivoje Nikolic	[10]
16	Heikki Orsila	[13] [21]
17	Brian C. Richards	[10] [11]
18	Jouni Riihimäki	[5] [12] [13] [14] [16] [19] [21] [23]
19	Jukka Saarinen	[1] [2]
20	Erno Salminen	[2] [5] [9] [13] [14] [16] [19] [21] [23]
21	Jarno K. Tanskanen	[4]
22	Petri A. Tuominen	[25]
23	Jarno Vanne	[8] [15] [17] [20] [22] [24]

Colors in the list of coauthors