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Sandip Kundu Vis

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*2009
77EEAarti Choudhary, Sandip Kundu: A process variation tolerant self-compensating FinFET based sense amplifier design. ACM Great Lakes Symposium on VLSI 2009: 161-164
76EEKelageri Nagaraj, Sandip Kundu: Process variation mitigation via post silicon clock tuning. ACM Great Lakes Symposium on VLSI 2009: 227-232
75EESpandana Remarsu, Sandip Kundu: On process variation tolerant low cost thermal sensor design in 32nm CMOS technology. ACM Great Lakes Symposium on VLSI 2009: 487-492
74EEAlodeep Sanyal, Abhisek Pan, Sandip Kundu: A study on impact of aggressor de-rating in the context of multiple crosstalk effects in circuits. ACM Great Lakes Symposium on VLSI 2009: 529-534
73EEKunal P. Ganeshpure, Ilia Polian, Sandip Kundu, Bernd Becker: Reducing temperature variability by routing heat pipes. ACM Great Lakes Symposium on VLSI 2009: 63-68
72EEKelageri Nagaraj, Sandip Kundu: A study on placement of post silicon clock tuning buffers for mitigating impact of process variation. DATE 2009: 292-295
71EEAswin Sreedhar, Sandip Kundu: On linewidth-based yield analysis for nanometer lithography. DATE 2009: 381-386
70EEAbhisek Pan, Omer Khan, Sandip Kundu: Improving yield and reliability of chip multiprocessors. DATE 2009: 490-495
69EEOmer Khan, Sandip Kundu: A self-adaptive system architecture to address transistor aging. DATE 2009: 81-86
68EEOmer Khan, Sandip Kundu: Hardware/software co-design architecture for thermal management of chip multiprocessors. DATE 2009: 952-957
67EEOmer Khan, Sandip Kundu: Predictive Thermal Management for Chip Multiprocessors Using Co-designed Virtual Machines. HiPEAC 2009: 293-307
66EEAlodeep Sanyal, Abhisek Pan, Sandip Kundu: A study on impact of loading effect on capacitive crosstalk noise. ISQED 2009: 696-701
65EEKunal P. Ganeshpure, Sandip Kundu: An ILP Based ATPG Technique for Multiple Aggressor Crosstalk Faults Considering the Effects of Gate Delays. VLSI Design 2009: 233-238
64EEAlodeep Sanyal, Kunal P. Ganeshpure, Sandip Kundu: An Improved Soft-Error Rate Measurement Technique. IEEE Trans. on CAD of Integrated Circuits and Systems 28(4): 596-600 (2009)
2008
63EEAswin Sreedhar, Alodeep Sanyal, Sandip Kundu: On Modeling and Testing of Lithography Related Open Faults in Nano-CMOS Circuits. DATE 2008: 616-621
62EESandip Kundu: The Guiding Light for Chip Testing. DDECS 2008: 1
61EEAbhisek Pan, James W. Tschanz, Sandip Kundu: A Low Cost Scheme for Reducing Silent Data Corruption in Large Arithmetic Circuit. DFT 2008: 343-351
60EEHyunbean Yi, Sandip Kundu: Core Test Wrapper Design to Reduce Test Application Time for Modular SoC Testing. DFT 2008: 412-420
59EEOmer Khan, Sandip Kundu: A framework for predictive dynamic temperature management of microprocessor systems. ICCAD 2008: 258-263
58EEAswin Sreedhar, Sandip Kundu: Modeling and analysis of non-rectangular transistors caused by lithographic distortions. ICCD 2008: 444-449
57EEAlodeep Sanyal, Sandip Kundu: A Built-in Test and Characterization Method for Circuit Marginality Related Failures. ISQED 2008: 838-843
56EEIrith Pomeranz, Sudhakar M. Reddy, Sandip Kundu: On Common-Mode Skewed-Load and Broadside Tests. VLSI Design 2008: 151-156
55EEPiet Engelke, Ilia Polian, Michel Renovell, Sandip Kundu, Bharath Seshadri, Bernd Becker: On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing. IEEE Trans. on CAD of Integrated Circuits and Systems 27(2): 327-338 (2008)
54EEAshesh Rastogi, Kunal P. Ganeshpure, Alodeep Sanyal, Sandip Kundu: On Composite Leakage Current Maximization. J. Electronic Testing 24(4): 405-420 (2008)
2007
53EEAshesh Rastogi, Wei Chen, Sandip Kundu: On Estimating Impact of Loading Effect on Leakage Current in Sub-65nm Scaled CMOS Circuits Based on Newton-Raphson Method. DAC 2007: 712-715
52EEKunal P. Ganeshpure, Sandip Kundu: Interactive presentation: Automatic test pattern generation for maximal circuit noise in multiple aggressor crosstalk faults. DATE 2007: 540-545
51EEAswin Sreedhar, Sandip Kundu: On modeling impact of sub-wavelength lithography on transistors. ICCD 2007: 84-90
50EEAlodeep Sanyal, Sandip Kundu: On Derating Soft Error Probability Based on Strength Filtering. IOLTS 2007: 152-160
49EEAlodeep Sanyal, Kunal P. Ganeshpure, Sandip Kundu: Accelerating Soft Error Rate Testing Through Pattern Selection. IOLTS 2007: 191-193
48EEAshesh Rastogi, Kunal P. Ganeshpure, Sandip Kundu: A Study on Impact of Leakage Current on Dynamic Power. ISCAS 2007: 1069-1072
47EEAlodeep Sanyal, Kunal P. Ganeshpure, Sandip Kundu: On Accelerating Soft-Error Detection by Targeted Pattern Generation. ISQED 2007: 723-728
46EEAshesh Rastogi, Wei Chen, Alodeep Sanyal, Sandip Kundu: An Efficient Technique for Leakage Current Estimation in Sub 65nm Scaled CMOS Circuits Based on Loading Effect. VLSI Design 2007: 583-588
45EEIlia Polian, Alejandro Czutro, Sandip Kundu, Bernd Becker: Power Droop Testing. IEEE Design & Test of Computers 24(3): 276-284 (2007)
2006
44EESandip Kundu: A design for failure analysis (DFFA) technique to ensure incorruptible signatures. DATE 2006: 309-310
43EEKunal P. Ganeshpure, Alodeep Sanyal, Sandip Kundu: A Pattern Generation Technique for Maximizing Power Supply Currents. ICCD 2006
42EEIlia Polian, Alejandro Czutro, Sandip Kundu, Bernd Becker: Power Droop Testing. ICCD 2006
41EESandip Kundu, Ilia Polian: An Improved Technique for Reducing False Alarms Due to Soft Errors. IOLTS 2006: 105-110
40EEDebasis Mitra, Subhasis Bhattacharjee, Susmita Sur-Kolay, Bhargab B. Bhattacharya, Sujit T. Zachariah, Sandip Kundu: Test Pattern Generation for Power Supply Droop Faults. VLSI Design 2006: 343-348
39EESandip Kundu: TTTC technical forum honoring Sudhakar M. Reddy. IEEE Design & Test of Computers 23(2): 167 (2006)
2005
38EESandip Kundu, Piet Engelke, Ilia Polian, Bernd Becker: On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing. Asian Test Symposium 2005: 266-271
37EEIlia Polian, Sandip Kundu, Jean Marc Gallière, Piet Engelke, Michel Renovell, Bernd Becker: Resistive Bridge Fault Model Evolution from Conventional to Ultra Deep Submicron Technologies. VTS 2005: 343-348
36EESandip Kundu, Sujit T. Zachariah, Yi-Shing Chang, Chandra Tirumurti: On modeling crosstalk faults. IEEE Trans. on CAD of Integrated Circuits and Systems 24(12): 1909-1915 (2005)
2004
35EEChandra Tirumurti, Sandip Kundu, Susmita Sur-Kolay, Yi-Shing Chang: A Modeling Approach for Addressing Power Supply Switching Noise Related Failures of Integrated Circuit. DATE 2004: 1078-1083
34EERob A. Rutenbar, Li-C. Wang, Kwang-Ting Cheng, Sandip Kundu: Static statistical timing analysis for latch-based pipeline designs. ICCAD 2004: 468-472
33EESandip Kundu, T. M. Mak, Rajesh Galivanche: Trends in manufacturing test methods and their implications. ITC 2004: 679-687
32 Rob Aitken, Stefan Eichenberger, Gary Maier, Sandip Kundu, Hank Walker: ITC 2003 Roundtable: Design for Manufacturability. IEEE Design & Test of Computers 21(2): 144-156 (2004)
31EEIrith Pomeranz, Sandip Kundu, Sudhakar M. Reddy: Masking of Unknown Output Values during Output Response Compression byUsing Comparison Units. IEEE Trans. Computers 53(1): 83-88 (2004)
30EEIrith Pomeranz, Sudhakar M. Reddy, Sandip Kundu: On the characterization and efficient computation of hard-to-detect bridging faults. IEEE Trans. on CAD of Integrated Circuits and Systems 23(12): 1640-1649 (2004)
29EESandip Kundu: Pitfalls of hierarchical fault simulation. IEEE Trans. on CAD of Integrated Circuits and Systems 23(2): 312-314 (2004)
2003
28EEBill Grundmann, Rajesh Galivanche, Sandip Kundu: Circuit and Platform Design Challenges in Technologies beyond 90nm. DATE 2003: 10044-10049
27EESujit T. Zachariah, Yi-Shing Chang, Sandip Kundu, Chandra Tirumurti: On Modeling Cross-Talk Faults. DATE 2003: 10490-10495
26EEIrith Pomeranz, Sudhakar M. Reddy, Sandip Kundu: On the Characterization of Hard-to-Detect Bridging Faults. DATE 2003: 11012-11019
25EEMasao Naruse, Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu: On-chip Compression of Output Responses with Unknown Values Using LFSR Reseeding. ITC 2003: 1060-1068
2002
24EEIrith Pomeranz, Sandip Kundu, Sudhakar M. Reddy: On output response compression in the presence of unknown output values. DAC 2002: 255-258
2001
23EEJing-Jia Liou, Kwang-Ting Cheng, Sandip Kundu, Angela Krstic: Fast Statistical Timing Analysis By Probabilistic Event Propagation. DAC 2001: 661-666
22EESitaram Yadavalli, Sandip Kundu: On Fault-Simulation Through Embedded Memories On Large Industrial Designs. VLSI Design 2001: 117-121
21EESandip Kundu, Sujit T. Zachariah, Sanjay Sengupta, Rajesh Galivanche: Test Challenges in Nanometer Technologies. J. Electronic Testing 17(3-4): 209-218 (2001)
2000
20EEJing-Jia Liou, Angela Krstic, Kwang-Ting Cheng, Deb Aditya Mukherjee, Sandip Kundu: Performance sensitivity analysis using statistical method and its applications to delay. ASP-DAC 2000: 587-592
1999
19EESreenivas Mandava, Sreejit Chakravarty, Sandip Kundu: On Detecting Bridges Causing Timing Failures. ICCD 1999: 400-406
1998
18 Anirudh Devgan, Sandip Kundu: Timing Analysis and Optimization: From Devices to Systems (Abstract of Embedded Tutorial). ASP-DAC 1998: 345
17EESandip Kundu: IDDQ Defect Detection in Deep Submicron CMOS ICs. Asian Test Symposium 1998: 150-152
16EESandip Kundu: GateMaker: a transistor to gate level model extractor for simulation, automatic test pattern generation and verification. ITC 1998: 372-
1997
15EESandip Kundu, Uttam Ghoshal: Inductance analysis of on-chip interconnects [deep submicron CMOS]. ED&TC 1997: 252-255
14EEAnirudh Devgan, Leon Stok, Sandip Kundu: Timing analysis and optimization: from devices to systems (tutorial). ICCAD 1997
1995
13EEVishwani D. Agrawal, Bernard Courtois, Fumiyasu Hirose, Sandip Kundu, Chung-Len Lee, Yinghua Min, P. Pal Chaudhuri: Panel: New Research Problems in the Emerging Test Technology. Asian Test Symposium 1995: 189-
1994
12EEJacob A. Abraham, Sandip Kundu, Janak H. Patel, Manuel A. d'Abreu, Bulent I. Dervisoglu, Marc E. Levitt, Hector R. Sucar, Ron G. Walther: Microprocessor Testing: Which Technique is Best? (Panel). DAC 1994: 294
11EEDaniel Brand, Anthony D. Drumm, Sandip Kundu, Prakash Narain: Incremental synthesis. ICCAD 1994: 14-18
10 Sandip Kundu: Multifault Testable Circuits Based on Binary Parity Diagrams. ICCD 1994: 363-366
9EELeendert M. Huisman, Sandip Kundu: Highly Reliable Symmetric Networks. IEEE Trans. Parallel Distrib. Syst. 5(1): 94-97 (1994)
1993
8 Ankan K. Pramanick, Sandip Kundu: Design of Scan-Based Path-Delay-Testable Sequential Circuits. ITC 1993: 962-971
1992
7 Sandip Kundu, Leendert M. Huisman, Indira Nair, Vijay S. Iyengar, Lakshmi N. Reddy: A Small Test Generator for Large Designs. ITC 1992: 30-40
1991
6EESandip Kundu, Sudhakar M. Reddy, Niraj K. Jha: Design of robustly testable combinational logic circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 10(8): 1036-1048 (1991)
1990
5EESandip Kundu, Sudhakar M. Reddy: Embedded Totally Self-Checking Checkers: A Practical Design. IEEE Design & Test of Computers 7(4): 5-12 (1990)
4 Sandip Kundu, Sudhakar M. Reddy: On Symmetric Error Correcting and All Unidirectional Error Detecting Codes. IEEE Trans. Computers 39(6): 752-761 (1990)
3EESandip Kundu, Sudhakar M. Reddy: Robust tests for parity trees. J. Electronic Testing 1(3): 191-200 (1990)
1989
2EESandip Kundu: Design of multioutput CMOS combinational logic circuits for robust testability. IEEE Trans. on CAD of Integrated Circuits and Systems 8(11): 1222-1226 (1989)
1988
1 Sandip Kundu, Sudhakar M. Reddy: Robust Tests for Parity Trees. ITC 1988: 680-687

Coauthor Index

1Jacob A. Abraham [12]
2Vishwani D. Agrawal [13]
3Robert C. Aitken (Rob Aitken) [32]
4Bernd Becker [37] [38] [42] [45] [55] [73]
5Subhasis Bhattacharjee [40]
6Bhargab B. Bhattacharya [40]
7Daniel Brand [11]
8Sreejit Chakravarty [19]
9Yi-Shing Chang [27] [35] [36]
10P. Pal Chaudhuri [13]
11Wei Chen [46] [53]
12Kwang-Ting Cheng (Kwang-Ting (Tim) Cheng) [20] [23] [34]
13Aarti Choudhary [77]
14Bernard Courtois [13]
15Alejandro Czutro [42] [45]
16Bulent I. Dervisoglu [12]
17Anirudh Devgan [14] [18]
18Anthony D. Drumm [11]
19Stefan Eichenberger [32]
20Piet Engelke [37] [38] [55]
21Rajesh Galivanche [21] [28] [33]
22Jean Marc Gallière [37]
23Kunal P. Ganeshpure [43] [47] [48] [49] [52] [54] [64] [65] [73]
24Uttam Ghoshal [15]
25Bill Grundmann [28]
26Fumiyasu Hirose [13]
27Leendert M. Huisman [7] [9]
28Vijay S. Iyengar [7]
29Niraj K. Jha [6]
30Omer Khan [59] [67] [68] [69] [70]
31Angela Krstic [20] [23]
32Chung-Len Lee [13]
33Marc E. Levitt [12]
34Jing-Jia Liou [20] [23]
35Gary Maier [32]
36T. M. Mak [33]
37Sreenivas Mandava [19]
38Yinghua Min [13]
39Debasis Mitra [40]
40Deb Aditya Mukherjee [20]
41Kelageri Nagaraj [72] [76]
42Indira Nair [7]
43Prakash Narain [11]
44Masao Naruse [25]
45Abhisek Pan [61] [66] [70] [74]
46Janak H. Patel [12]
47Ilia Polian [37] [38] [41] [42] [45] [55] [73]
48Irith Pomeranz [24] [25] [26] [30] [31] [56]
49Ankan K. Pramanick [8]
50Ashesh Rastogi [46] [48] [53] [54]
51Lakshmi N. Reddy [7]
52Sudhakar M. Reddy [1] [3] [4] [5] [6] [24] [25] [26] [30] [31] [56]
53Spandana Remarsu [75]
54Michel Renovell [37] [55]
55Rob A. Rutenbar [34]
56Alodeep Sanyal [43] [46] [47] [49] [50] [54] [57] [63] [64] [66] [74]
57Sanjay Sengupta [21]
58Bharath Seshadri [55]
59Aswin Sreedhar [51] [58] [63] [71]
60Leon Stok [14]
61Hector R. Sucar [12]
62Susmita Sur-Kolay [35] [40]
63Chandra Tirumurti [27] [35] [36]
64James W. Tschanz [61]
65Hank Walker [32]
66Ron G. Walther [12]
67Li-C. Wang [34]
68Sitaram Yadavalli [22]
69Hyunbean Yi [60]
70Sujit T. Zachariah [21] [27] [36] [40]
71Manuel A. d'Abreu [12]

Colors in the list of coauthors

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)