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Ivan S. Kourtev Vis

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*2009
17EEBaris Taskin, Ivan S. Kourtev: Multi-Phase Rotary Clock Synchronization of Level-Sensitive Circuits. Journal of Circuits, Systems, and Computers 18(5): 899-908 (2009)
2006
16EERaymond R. Hoare, Ivan S. Kourtev, Alex K. Jones: Technology Mapping for Field Programmable Gate Arrays using Content-Addressable Memory (CAM). FCCM 2006: 299-300
15EEBaris Taskin, Ivan S. Kourtev: Delay Insertion Method in Clock Skew Scheduling. IEEE Trans. on CAD of Integrated Circuits and Systems 25(4): 651-663 (2006)
14EEJoshua M. Lucas, Raymond Hoare, Ivan S. Kourtev, Alex K. Jones: Technology mapping for Field Programmable Gate Arrays using Content-Addressable Memory (CAM). Microprocessors and Microsystems 30(7): 445-456 (2006)
2005
13EEBaris Taskin, Ivan S. Kourtev: Delay insertion method in clock skew scheduling. ISPD 2005: 47-54
2004
12 Baris Taskin, Ivan S. Kourtev: Time borrowing and clock skew scheduling effects on multi-phase level-sensitive circuits. ISCAS (2) 2004: 617-620
11 Rajani Parthasarthy, Ivan S. Kourtev: Performance metrics for asynchronous digital circuits applicable to computer-aided design. ISCAS (5) 2004: 301-304
10 Baris Taskin, Ivan S. Kourtev: Linearization of the timing analysis and optimization of level-sensitive digital synchronous circuits. IEEE Trans. VLSI Syst. 12(1): 12-27 (2004)
9 Radu M. Secareanu, Scott Warner, Scott Seabridge, Cathie Burke, Juan Becerra, Thomas E. Watrobski, Christopher Morton, William Staub, Thomas Tellier, Ivan S. Kourtev, Eby G. Friedman: Substrate coupling in digital circuits in mixed-signal smart-power systems. IEEE Trans. VLSI Syst. 12(1): 67-78 (2004)
2003
8EERoy Mader, Ivan S. Kourtev: Reduced dynamic swing domino logic. ACM Great Lakes Symposium on VLSI 2003: 33-36
7EEIvan S. Kourtev, Raymond R. Hoare, Steven P. Levitan, Tom Cain, Bruce R. Childers, Donald M. Chiarulli, David L. Landis: Short Courses in System-on-a-Chip (SoC) Design. MSE 2003: 126-127
6EEHerman Schmit, Thomas Kroll, Max Khusid, Ivan S. Kourtev, Narayanan Vijaykrishnan, David L. Landis: The Sandbox Design Experience Course. MSE 2003: 39-40
2002
5EERoy Mader, Eby G. Friedman, Ami Litman, Ivan S. Kourtev: Large scale clock skew scheduling techniques for improved reliability of digital synchronous VLSI circuits. ISCAS (1) 2002: 357-360
4EEBaris Taskin, Ivan S. Kourtev: Performance optimization of single-phase level-sensitive circuits using time borrowing and non-zero clock skew. Timing Issues in the Specification and Synthesis of Digital Systems 2002: 111-118
3EEDimitrios Velenis, Kevin T. Tang, Ivan S. Kourtev, V. Adler, F. Baez, Eby G. Friedman: Demonstration of Speed and Power Enhancements on an Industrial Circuit Through Application of Clock Skew Scheduling. Journal of Circuits, Systems, and Computers 11(3): 231-246 (2002)
1999
2EERadu M. Secareanu, Ivan S. Kourtev, Juan Becerra, Thomas E. Watrobski, Christopher Morton, William Staub, Thomas Tellier, Eby G. Friedman: Noise Immunity of Digital Circuits in Mixed-Signal Smart Power Systems. Great Lakes Symposium on VLSI 1999: 314-317
1EEIvan S. Kourtev, Eby G. Friedman: Clock skew scheduling for improved reliability via quadratic programming. ICCAD 1999: 239-243

Coauthor Index

1V. Adler [3]
2F. Baez [3]
3Juan Becerra [2] [9]
4Cathie Burke [9]
5Tom Cain [7]
6Donald M. Chiarulli [7]
7Bruce R. Childers [7]
8Eby G. Friedman [1] [2] [3] [5] [9]
9Raymond R. Hoare (Raymond Hoare) [7] [14] [16]
10Alex K. Jones [14] [16]
11Max Khusid [6]
12Thomas Kroll [6]
13David L. Landis [6] [7]
14Steven P. Levitan [7]
15Ami Litman [5]
16Joshua M. Lucas [14]
17Roy Mader [5] [8]
18Christopher Morton [2] [9]
19Rajani Parthasarthy [11]
20Herman Schmit [6]
21Scott Seabridge [9]
22Radu M. Secareanu [2] [9]
23William Staub [2] [9]
24Kevin T. Tang [3]
25Baris Taskin [4] [10] [12] [13] [15] [17]
26Thomas Tellier [2] [9]
27Dimitrios Velenis [3]
28Narayanan Vijaykrishnan (Vijaykrishnan Narayanan) [6]
29Scott Warner [9]
30Thomas E. Watrobski [2] [9]

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Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)