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Hanpei Koike Vis

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*2009
24EESeid Hadi Rasouli, Hanpei Koike, Kaustav Banerjee: High-speed low-power FinFET based domino logic. ASP-DAC 2009: 829-834
2008
23EEShin-ichi O'Uchi, Meishoku Masahara, Kazuhiko Endo, Yongxun Liu, Takashi Matsukawa, Kunihiro Sakamoto, Toshihiro Sekigawa, Hanpei Koike, Eiichi Suzuki: FinFET-Based Flex-Vth SRAM Design for Drastic Standby-Leakage-Current Reduction. IEICE Transactions 91-C(4): 534-542 (2008)
22EEYohei Matsumoto, Masakazu Hioki, Takashi Kawanami, Hanpei Koike, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa: Suppression of Intrinsic Delay Variation in FPGAs using Multiple Configurations. TRETS 1(1): (2008)
2007
21EEYohei Matsumoto, Masakazu Hioki, Takashi Kawanami, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike: Performance and yield enhancement of FPGAs with within-die variation using multiple configurations. FPGA 2007: 169-177
20EETakashi Kawanami, Masakazu Hioki, Yohei Matsumoto, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike: Optimization of the Body Bias Voltage Set (BBVS) for Flex Power FPGA. IEICE Transactions 90-D(12): 1947-1955 (2007)
2006
19EEMasakazu Hioki, Takashi Kawanami, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike: Evaluation of granularity on threshold voltage control in flex power FPGA. FPGA 2006: 223
18EEYohei Matsumoto, Hanpei Koike, Akira Masaki: FPGAs with multidimensional mesh topology. FPGA 2006: 223
2004
17EETakashi Kawanami, Masakazu Hioki, Hiroshi Nagase, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike: Preliminary performance analysis of flex power FPGA, a power reconfigurable device with fine granularity. FPGA 2004: 257
1998
16EEHayato Yamana, Hanpei Koike, Yuetsu Kodama, Hirofumi Sakane, Yoshinori Yamaguchi: Fast Speculative Search Engine on the Highly Parallel Computer EM-X. SIGIR 1998: 390
1997
15EEYuetsu Kodama, Hirofumi Sakane, Hanpei Koike, Mitsuhisa Sato, Shuichi Sakai, Yoshinori Yamaguchi: Parallel Execution of Radix Sort Program Using Fine-Grain Communication. IEEE PACT 1997: 136-145
1994
14 Hidemoto Nakada, Takuya Araki, Hanpei Koike, Hidehiko Tanaka: A Fleng Compiler for PIE64. IFIP PACT 1994: 257-266
13 Jun'ichi Tatemura, Hanpei Koike, Hidehiko Tanaka: A Performance Debugger for a Parallel Logic Programming Language Fleng. Theory and Practice of Parallel Programming 1994: 284-299
1993
12 Kentaro Shimada, Hanpei Koike, Hidehiko Tanaka: The Instruction Set Architecture of the Inference Processor UNIRED II. Architectures and Compilation Techniques for Fine and Medium Grain Parallelism 1993: 117-128
11 Yasuo Hidaka, Hanpei Koike, Hidehiko Tanaka: Multiple Threads in Cyclic Register Windows. ISCA 1993: 131-142
10EEJun'ichi Tatemura, Hanpei Koike, Hidehiko Tanaka: Control and Data Flow Visualization for Parallel Logic Programs on a Multi-window Debugger HyperDEBU. PARLE 1993: 414-425
9 Kentaro Shimada, Hanpei Koike, Hidehiko Tanaka: UNIRED II: The High Performance Inference Processor for the Parallel Inference Machine PIE64. New Generation Comput. 11(3): 251-269 (1993)
1992
8 Kentaro Shimada, Hanpei Koike, Hidehiko Tanaka: UNIRED II: The High Performance Inference Processor for the Parallel Inference Machine PIE64. FGCS 1992: 715-722
7EEYasuo Hidaka, Hanpei Koike, Hidehiko Tanaka: Architecture of Parallel Management Kernel for PIE64. PARLE 1992: 685-700
6 Jun'ichi Tatemura, Hanpei Koike, Hidehiko Tanaka: HyperDEBU: A Multiwindow Debugger for Parallel Logic Programs. Programming Environments for Parallel Computing 1992: 87-105
1991
5 Yasuo Hidaka, Hanpei Koike, Jun'ichi Tatemura, Hidehiko Tanaka: A Static Load Partitioning Method based on Execution Profile for Committed Choice Languages. ISLP 1991: 470-484
1989
4 Lu Xu, Hanpei Koike, Hidehiko Tanaka: Distributed Garbage Collection for the Parallel Inference Machine PIE64. IFIP Congress 1989: 1161-1166
3 Lu Xu, Hanpei Koike, Hidehiko Tanaka: Distributed Garbage Collection for the Parallel Inference Engine PIE64. NACLP 1989: 922-941
1988
2 Hanpei Koike, Hidehiko Tanaka: Multi-Context Processing and Data Balancing Mechanism of the Parallel Inference Machine PIE64. FGCS 1988: 970-977
1986
1EEHanpei Koike, Hidehiko Tanaka: Fast Execution Mechanisms of Parallel Inference Engine PIE: PIEpelined Goal Rewriting and Goal Multicasting. LP 1986: 159-169

Coauthor Index

1Takuya Araki [14]
2Kaustav Banerjee [24]
3Kazuhiko Endo [23]
4Yasuo Hidaka [5] [7] [11]
5Masakazu Hioki [17] [19] [20] [21] [22]
6Takashi Kawanami [17] [19] [20] [21] [22]
7Yuetsu Kodama [15] [16]
8Yongxun Liu [23]
9Meishoku Masahara [23]
10Akira Masaki [18]
11Takashi Matsukawa [23]
12Yohei Matsumoto [18] [20] [21] [22]
13Hiroshi Nagase [17]
14Hidemoto Nakada [14]
15Tadashi Nakagawa [17] [19] [20] [21] [22]
16Shin-ichi O'Uchi [23]
17Seid Hadi Rasouli [24]
18Shuichi Sakai [15]
19Kunihiro Sakamoto [23]
20Hirofumi Sakane [15] [16]
21Mitsuhisa Sato [15]
22Toshihiro Sekigawa [17] [19] [20] [21] [22] [23]
23Kentaro Shimada [8] [9] [12]
24Eiichi Suzuki [23]
25Hidehiko Tanaka [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14]
26Jun'ichi Tatemura [5] [6] [10] [13]
27Toshiyuki Tsutsumi [17] [19] [20] [21] [22]
28Lu Xu [3] [4]
29Yoshinori Yamaguchi [15] [16]
30Hayato Yamana [16]

Colors in the list of coauthors

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)